CN102346341B - Array base plate, manufacturing method for array base plate, liquid crystal panel, liquid crystal display and driving method - Google Patents
Array base plate, manufacturing method for array base plate, liquid crystal panel, liquid crystal display and driving method Download PDFInfo
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Abstract
The invention discloses an array base plate, a manufacturing method for the array base plate, a liquid crystal panel, a liquid crystal display and a driving method. The array base plate comprises a grid line, data wires and a common electrode wire formed on a substrate base plate, wherein a pixel electrode and a thin-film transistor are formed in a pixel region limited by the grid line and the data wires. The array base plate also comprises a first grid line and switching elements which correspond to a plurality of data wire pairs in the data wires, wherein the data wire pairs consist of two data wires with contrary voltage reversed polarities, and the number of the data wire pairs is equal to one half of the data wires; the first grid line is arranged on at least one of the upper side and the lower side of the substrate base plate; and the switching elements are connected with the data wire pairs and the first grid line, and are used for conducting the data wire pairs corresponding to the switching elements under the control of the first grid line. By driving the first grid line and neutralizing charges of pixel electrodes of the data wires with contrary voltage reversed polarities, when the first grid line is turned off and the data wires are used for charging the pixel electrodes, the power consumption can be remarkably reduced.
Description
Technical field
The present invention relates to lcd technology, relate in particular to a kind of array base palte and manufacture method, liquid crystal panel, liquid crystal display and driving method.
Background technology
Liquid crystal display is current conventional flat-panel monitor, and wherein Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display is called for short TFT-LCD) is the main product in liquid crystal display.Liquid crystal panel is the vitals in liquid crystal display, mainly comprises array base palte and color membrane substrates that box is arranged, is filled with liquid crystal layer therebetween.
Fig. 1 is the electrical block diagram of existing array base palte, as shown in Figure 1, is formed with many grid lines 101 and the data line 102 that intersect in length and breadth on array base palte, encloses and forms a plurality of pixel cells 103 that matrix form is arranged.In each pixel cell 103, be equipped with TFT104.For the TFT104 in each pixel cell 103, its function is equivalent to a switching tube.The patterns such as grid line 101, data line 102 and pixel cell 103 are referred to as conductive pattern in the prior art, and formed grid electrode insulating layer and passivation layer are referred to as insulation course in forming the pattern processes such as grid line 101, data line 102 and pixel cell 103.Conductive pattern and insulation course can adopt existing technique to form.In the time will charging to certain a line pixel cell 103, can, by grid line 101 corresponding to this row by the TFT104 conducting of these row pixel cell 103 correspondences, then by 102 pairs of these row pixel cells 103 of data line, apply target voltage.After the pixel electrode of pixel cell 103 is fully charged, even if TFT104 disconnects, because the demonstration voltage being added on liquid crystal layer can be stored in the memory capacitance of each pixel cell 103, so liquid crystal layer can stably be worked.
Along with the continuous increase of liquid crystal panel size, the load of liquid crystal panel is corresponding increase also, causes power consumption significantly to rise, and therefore, the power consumption that how to reduce liquid crystal panel becomes problem demanding prompt solution.
Summary of the invention
The invention provides a kind of array base palte and manufacture method, liquid crystal panel, liquid crystal display and driving method, to reduce the power consumption of liquid crystal panel.
The invention provides a kind of array base palte, comprise the grid line being formed on underlay substrate, data line and public electrode wire, in the pixel region that described grid line and described data line limit, form pixel electrode and thin film transistor (TFT), also comprise: the first grid line and with a plurality of data lines in described data line to corresponding respectively on-off element, described data line equals half of described data line number to the number by opposite polarity two data lines of voltage reversal form and described data line is right, described the first grid line is arranged at least one side in the upper and lower both sides of described underlay substrate, described switch original paper and data line to and described the first grid line be connected, described on-off element is under the control of described the first grid line, by the data line corresponding with described on-off element to conducting.
The invention provides a kind of liquid crystal panel, comprise array base palte and color membrane substrates that box is arranged, between described array base palte and color membrane substrates, be filled with liquid crystal layer, described array base palte adopts above-mentioned array base palte.
The invention provides a kind of liquid crystal display, comprise outside framework and liquid crystal panel, described liquid crystal panel adopts above-mentioned liquid crystal panel.
The invention provides a kind of manufacture method of array base palte, be included in the step that forms conductive pattern on underlay substrate, also comprise:
While forming the grid line in described conductive pattern, in the both sides up and down of described underlay substrate, form described the first grid line and described first grid electrode;
While forming source electrode, the drain electrode of data line in described conductive pattern, thin film transistor (TFT), in the upper and lower both sides of described underlay substrate, form transistorized the first source electrode of described the first film and the first drain electrode, transistorized the first source electrode of described the first film is connected with a data line of described data line centering, and transistorized the first drain electrode of described two the first films is connected with another data line of described data line centering.
The invention provides a kind ofly for driving the driving method of above-mentioned liquid crystal display, comprising:
When driving grid line corresponding to every row pixel region, drive described the first grid line so that the on-off element connecting with described the first grid line by the data line corresponding with this on-off element to being communicated with;
Close described the first grid line, keep the grid line of driven row to open, and driving data lines is charged to this row pixel region.
Array base palte provided by the invention and manufacture method, liquid crystal panel, liquid crystal display and driving method, before data line charges to pixel electrode, can be by driving the first grid line respectively opposite polarity two data lines of voltage reversal to be communicated with, the pixel electrode that is connected respectively with opposite polarity two data lines of voltage reversal is communicated with, thus in and the electric charge of pixel electrode.Therefore,, closing the first grid line while adopting data line to charge to pixel electrode, can significantly reduce power consumption.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of existing array base palte;
Fig. 2 is the reversed polarity schematic diagram of existing polarity of voltage row reversion;
Fig. 3 is the reversed polarity schematic diagram of existing polarity of voltage point reversion;
Fig. 4 is the driving signal schematic representation of grid line in array base palte of the present invention, the first grid line and data line;
Fig. 5 is the equivalent circuit structure schematic diagram of array base palte embodiment mono-of the present invention;
Fig. 6 is the plan structure schematic diagram of array base palte embodiment bis-of the present invention;
Fig. 7 is the equivalent circuit structure schematic diagram of array base palte embodiment bis-of the present invention;
Fig. 8 is the process flow diagram of manufacturing method of array base plate embodiment mono-of the present invention;
Fig. 9 is the process flow diagram of the driving method embodiment mono-of liquid crystal display of the present invention.
Reference numeral:
101-grid line; 102-data line; 103-pixel cell;
104-TFT; 105-underlay substrate; 106-the first grid line;
107-the one TFT; 108-first grid electrode; 109-the first source electrode;
110-the first drain electrode.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Liquid crystal material in liquid crystal layer produces polarization and causes permanent destruction, and the polarity of voltage of liquid crystal deflection voltage, is also that the pressure reduction polarity between color membrane substrates and array base palte must be reversed every the schedule time.Fig. 2 is the reversed polarity schematic diagram of existing polarity of voltage row reversion, Fig. 3 is the reversed polarity schematic diagram of existing polarity of voltage point reversion, as shown in Figures 2 and 3, no matter be a reversion or row reversion, between adjacent pixel unit in same a line, the reversed polarity of its liquid crystal deflection voltage is contrary.For instance, on color membrane substrates, the representative value of public electrode voltages is 5V and is steady state value, in order to make the polarity absolute value contrary and liquid crystal deflection voltage of the liquid crystal deflection voltage of adjacent two pixel cells in same a line, be 1V, with these two pixel cells respectively the charging voltage of corresponding data line can be respectively 4V and 6V.For example, the charging voltage of the data line corresponding with the 1st row the 1st row pixel cell can be 4V, and the charging voltage of the data line corresponding with the 1st row the 2nd row pixel cell can be 6V, thereby make the liquid crystal deflection voltage of the 1st row the 1st row pixel cell be+1V, and the liquid crystal deflection voltage of the 1st row the 2nd row pixel cell is-1V.In upper once charging process, in order to make liquid crystal molecule, setover in the opposite direction, need to make the liquid crystal deflection voltage of the 1st row the 1st row pixel cell to be-1V, and the liquid crystal deflection voltage of the 1st row the 2nd row pixel cell is+1V, therefore, public electrode voltages is constant be 5V in the situation that, the liquid crystal deflection voltage corresponding with the 1st row the 1st row pixel cell need to be from+be changed to-1V of 1V, and the liquid crystal deflection voltage corresponding with the 1st row the 2nd row pixel cell need to be from-become+1V of 1V.Therefore, in this process, the pixel electrode of the 1st row the 1st row pixel cell need to supplement the electric charge of 2V, thus power hungry, and the pixel electrode of the 1st row the 2nd row pixel cell need to discharge the electric charge of 2V, thus waste power.Hence one can see that, when the polarity of voltage of liquid crystal deflection voltage changes, should expend more electric energy, also will waste much electricity, therefore causes the power consumption of liquid crystal panel larger.
Inventor finds by research, before polarity of voltage reversion, can will need to discharge unnecessary charge compensation on the pixel electrode of electric charge to the pixel electrode that need to supplement electric charge, thereby reduce the power consumption of liquid crystal panel.Still with foregoing for instance, current, public electrode voltages is constant be 5V in the situation that, the liquid crystal deflection voltage of the 1st row the 1st row pixel cell is+1V, and the liquid crystal deflection voltage of the 1st row the 2nd row pixel cell is-1V.In order to make the liquid crystal deflection voltage of the 1st row the 1st row pixel cell be-1V, and the liquid crystal deflection voltage of the 1st row the 2nd row pixel cell is+1V, before driving data lines is charged to the pixel electrode of each pixel cell, can be first by the data line data line conducting corresponding with the 1st row the 2nd row pixel cell corresponding to the 1st row the 1st row pixel cell, thus by two data lines by the charging neutrality on the pixel electrode of the pixel electrode of the 1st row the 1st row pixel cell and the 1st row the 2nd row pixel cell.Also now, the liquid crystal deflection voltage of the 1st row the 1st row pixel cell can be 0V, and the liquid crystal deflection voltage of the 1st row the 2nd row pixel cell is also 0V.So far, while adopting again data line to charge, only need be by liquid crystal deflection voltage corresponding to the 1st row the 2nd row pixel cell from bring up to+1V of 0V, and by liquid crystal deflection voltage corresponding to the 1st row the 1st row pixel cell from be reduced to-1V of 0V, but not as in prior art, need to be by liquid crystal deflection voltage corresponding to the 1st row the 2nd row pixel cell from-bring up to+1V of 1V, and by liquid crystal deflection voltage corresponding to the 1st row the 1st row pixel cell from be reduced to-1V of 1V.
Description according to above-mentioned principle, the present invention correspondingly provides a kind of array base palte, this array base palte, comprise the grid line being formed on underlay substrate, data line and public electrode wire, in the pixel region that grid line and data line limit, form pixel electrode and thin film transistor (TFT), this array base palte also comprises: the first grid line and with a plurality of data lines in described data line to corresponding respectively on-off element, described data line equals half of described data line number to the number by two opposite polarity two data lines of voltage reversal form and described data line is right, described the first grid line is arranged at least one side in the upper and lower both sides of described underlay substrate, described switch original paper and data line to and described the first grid line be connected, described on-off element is under the control of described the first grid line, by the data line corresponding with described on-off element to conducting.
Specifically, the present invention can arrange the first grid line on upside, downside or the upside of underlay substrate and downside, and this first grid line can be parallel with the grid line on underlay substrate.On this underlay substrate, be also provided with the several on-off elements that are connected with the first grid line, each on-off element is used for controlling a data line pair, and in the present invention, a data line is to being comprised of opposite polarity two data lines of voltage reversal.
For each on-off element, its concrete annexation can be, the control end of on-off element is connected with this first grid line, two links of on-off element respectively with the corresponding connection of two data lines of data line centering.Therefore, drive this first grid line, be the opening and closing of controllable switch element, when the first grid line is opened, the control end of on-off element can be on the first grid line the control of driving signal under by two link conductings of on-off element, thereby opposite polarity two data lines of voltage reversal are communicated with.Therefore, the quantity of on-off element can equal half of data line quantity, can adopt opposite polarity two data lines of voltage reversal to be one group all of data lines is divided, and each on-off element is connected with every pair of data lines.
Fig. 4 is the driving signal schematic representation of grid line in array base palte of the present invention, the first grid line and data line, as shown in Figure 4, take progressive scan mode as example, when the grid line of the first row pixel is opened, open the first grid line, now, for the first row pixel region, two data lines that are connected with same on-off element are communicated with, and the pixel electrode being also connected respectively with these two data lines is communicated with.Therefore, the electric charge on these two pixel electrodes can be realized neutralization.The state that keeps grid line to open, and closed the first grid line before data line is opened.By closing the first grid line, can be so that insulated from each other between data line, under the prerequisite of still opening at the grid line that keeps the first row pixel, then driving data lines is charged to the first row pixel.So far, can complete the charging process of the first row pixel region, to the charge type of the second row pixel seemingly, repeat no more.It should be noted that, in driving signal shown in Fig. 4, the opening time of the first grid line is identical with the start time of grid line, the shut-in time of the first grid line is identical with the time that data line is opened, as long as but it will be appreciated by persons skilled in the art that the duration of the first grid line in opening meets between the time point that the time point opened at grid line and data line open.
It should be noted that, for fear of signal delay, preferably, the present invention can adopt the structure that the first grid line is all set on the upside of underlay substrate and downside, when driving upper and lower two the first grid lines to open corresponding on-off element, can from both direction, neutralize by the electric charge to pixel electrode.
The present invention is not limited to the concrete connected mode of on-off element, only need to make each on-off element respectively with the opposite polarity data line of voltage reversal to being connected.The present invention is also not limited to the concrete structure of on-off element, as long as it can play on-off action, and can be by the opposite polarity data line of voltage reversal to being communicated with or disconnecting under the driving of the first grid line.In addition, the present invention neither limits the size of the liquid crystal deflection voltage of adjacent two pixel cells in same a line, also whether adjacent two pixel cell liquid crystal deflection voltages is not equated to limit.
Fig. 5 is the equivalent circuit structure schematic diagram of array base palte embodiment mono-of the present invention, as shown in Figure 5, the array base palte of the present embodiment can comprise the grid line 101 being formed on underlay substrate 105, data line 102 and public electrode wire (not shown), in the pixel region that grid line 101 and data line 102 limit, form pixel electrode 103 and TFT104, the array base palte of the present embodiment also comprises: the first grid line 106 and with a plurality of data lines in data line 102 to a corresponding respectively TFT107, this data line is to being comprised of opposite polarity two data lines 102 of voltage reversal, and the right number of this data line equals data line 102 numbers half, the first grid line 106 is arranged on underlay substrate 105 upsides, the first grid electrode 108 of each TFT107 is connected with the first grid line 106, the first source electrode 109 of each TFT107 is connected with opposite polarity two data lines of voltage reversal respectively with the first drain electrode 110.The first source electrode 109 that the one TFT107 has been shown in Fig. 5 of the present embodiment can be connected respectively with the 4th data line with article one data line accordingly with the first drain electrode 110, and the first source electrode 109 of another TFT107 can be connected respectively with the 3rd data line with second data line accordingly with the first drain electrode 110.As long as a unshowned TFT107 meets the above-mentioned principle being connected with opposite polarity two data lines of voltage reversal and is connected with corresponding data line in Fig. 5 of the present embodiment.
It should be noted that, what the on-off element in the present embodiment adopted is TFT switch, it will be understood by those skilled in the art that it can adopt other element that can realize arbitrarily switching function to realize, the achieved function class of itself and TFT switch seemingly, repeats no more herein.And above-mentioned the first grid line also can be arranged on the downside of underlay substrate, it is similar with the upside that is arranged on underlay substrate that it realizes principle, repeats no more herein.
The array base palte of the present embodiment, before data line charges to pixel electrode, can by drive the first grid line respectively by the opposite polarity data line of voltage reversal to being communicated with, the pixel electrode that is connected respectively with opposite polarity two data lines of voltage reversal is communicated with, thus in and the electric charge of pixel electrode.Therefore,, closing the first grid line while adopting data line to charge to pixel electrode, can significantly reduce power consumption.
Fig. 6 is the plan structure schematic diagram of array base palte embodiment bis-of the present invention, Fig. 7 is the equivalent circuit structure schematic diagram of array base palte embodiment bis-of the present invention, as shown in Figures 6 and 7, shown in the array base palte of the present embodiment and Fig. 5, the difference of array base palte is, for fear of signal delay, the present embodiment all arranges the first grid line 106 in the both sides up and down of underlay substrate 105, and, in order to reduce the charging neutrality time, the present embodiment is divided into one group according to order from left to right between two by data line adjacent in data line 102, the the first source electrode 109 that makes a TFT107 and the first drain electrode 110 are done the data line that forms to being connected with adjacent data line respectively, for example, in Fig. 6 and 7, two TFT107 are between adjacent article one data line and second data line, and two TFT107 first source electrodes 109 are connected with second data line with article one data line respectively with the first drain electrode 110, the first source electrode 109 of another two TFT107 is connected with the 4th data line with the 3rd data line respectively with the first drain electrode 110.
The array base palte of the present embodiment, before data line charges to pixel electrode, can be by driving the first grid line respectively opposite polarity two data lines of voltage reversal to be communicated with, the pixel electrode that is connected respectively with opposite polarity two data lines of voltage reversal is communicated with, thus in and the electric charge of pixel electrode.Therefore,, closing the first grid line while adopting data line to charge to pixel electrode, can significantly reduce power consumption.And the present embodiment, with respect to array base palte embodiment mono-, can shorten the charging neutrality time, avoids occurring signal delay.
The embodiment of the present invention also provides a kind of liquid crystal panel, comprise array base palte and color membrane substrates that box is arranged, between described array base palte and color membrane substrates, be filled with liquid crystal layer, and this array base palte can adopt the array base palte described in above-described embodiment one and embodiment bis-.This liquid crystal panel is before data line charges to pixel electrode, can be by driving the first grid line respectively opposite polarity two data lines of voltage reversal to be communicated with, the pixel electrode that is connected respectively with opposite polarity two data lines of voltage reversal is communicated with, thus in and the electric charge of pixel electrode.Therefore,, closing the first grid line while adopting data line to charge to pixel electrode, can significantly reduce power consumption.
The embodiment of the present invention also provides a kind of liquid crystal display, comprises outside framework and liquid crystal panel, and wherein liquid crystal panel can adopt above-mentioned liquid crystal panel, and the array base palte in this liquid crystal panel can adopt the array base palte described in above-described embodiment one and embodiment bis-.This liquid crystal display is before data line charges to pixel electrode, can be by driving the first grid line respectively opposite polarity two data lines of voltage reversal to be communicated with, the pixel electrode that is connected respectively with opposite polarity two data lines of voltage reversal is communicated with, thus in and the electric charge of pixel electrode.Therefore,, closing the first grid line while adopting data line to charge to pixel electrode, can significantly reduce power consumption.
The embodiment of the present invention also provides a kind of manufacture method of array base palte, is included in the step that forms conductive pattern on underlay substrate, also comprises:
While forming the grid line in described conductive pattern, in the both sides up and down of described underlay substrate, form described the first grid line and described first grid electrode;
While forming source electrode, the drain electrode of data line in described conductive pattern, thin film transistor (TFT), in the upper and lower both sides of described underlay substrate, form transistorized the first source electrode of described the first film and the first drain electrode, transistorized the first source electrode of described the first film is connected with a data line of described data line centering, and transistorized the first drain electrode of described two the first films is connected with another data line of described data line centering.
Because the concrete preparation technology of array base palte depends on the structure of array base palte itself, the application's technical scheme can have multiple embodiment accordingly, and typical four the mask composition techniques of take below describe as example.
Fig. 8 is the process flow diagram of manufacturing method of array base plate embodiment mono-of the present invention, and the present embodiment specifically be take and formed in embodiment bis-array base-plate structure and describe as example.In the following description, the alleged composition technique of the present invention comprises the techniques such as photoresist coating, mask, exposure, etching and photoresist lift off, and photoresist be take positive photoresist as example.As shown in Figure 8, the method for the present embodiment comprises:
Step 11, on underlay substrate, deposit grid metallic film, by composition technique, form the figure that comprises grid line, gate electrode and public electrode wire, in the both sides up and down of described underlay substrate, form described the first grid line and first grid electrode;
Particularly, can adopt the method for magnetron sputtering or thermal evaporation, at underlay substrate, for example on glass substrate or quartz base plate, deposit one deck grid metallic film, grid metallic film can adopt the metals such as Mo, Al, also can adopt the laminated film (as Mo/Al/Mo laminated film) consisting of multiple layer metal film.Adopt normal masks plate to carry out composition to grid metallic film, on underlay substrate, form the figure that comprises grid line, gate electrode, public electrode wire, the first grid line and first grid electrode.
Step 12, on the underlay substrate of completing steps 11, deposit gate insulation layer, semiconductive thin film, doped semiconductor films and metallic film is leaked in source, by composition technique, form the figure that comprises active layer, data line, drain electrode, source electrode and TFT raceway groove, and above described first grid electrode, form transistorized the first active layer of the first film, the first source electrode, the first drain electrode and a TFT raceway groove, and described the first source electrode is connected with a data line of described data line centering, and described the first drain electrode is connected with another data line of described data line centering;
Particularly, complete on the substrate of said structure figure, first using plasma strengthens chemical vapor deposition (being called for short PECVD) method, deposit successively grid insulating film, semiconductive thin film and doped semiconductor films, then adopt the method for magnetron sputtering or thermal evaporation, metallic film is leaked in deposition one deck source.Grid insulating film can adopt oxide, nitride or oxynitrides, metallic film is leaked in source can adopt the metals such as Mo, Al, or adopt the low metal of Cu constant resistance rate, also can adopt the laminated film (as Mo/Al/Mo laminated film) being formed by multiple layer metal film.Adopt shadow tone or gray mask plate to form data line, source electrode, drain electrode and TFT channel region pattern by composition technique, and above first grid electrode, form transistorized the first active layer of the first film, the first source electrode, the first drain electrode and a TFT raceway groove, and transistorized the first source electrode of each the first film is connected with opposite polarity two data lines of voltage reversal respectively with the first drain electrode.
Step 13, on the underlay substrate of completing steps 12 deposit passivation layer, by composition technique, form the figure comprise passivation layer via hole, described passivation layer via hole is positioned at the top of drain electrode;
Particularly, complete on the underlay substrate of said structure figure, adopting PECVD method deposition one deck passivation layer.Passivation layer can adopt oxide, nitride or oxynitrides.Adopt normal masks plate to carry out composition to passivation layer, form passivation layer via hole, passivation layer via hole is positioned at the top of drain electrode.
Step 14, on the underlay substrate of completing steps 13 deposit transparent conductive film, by composition technique, form the figure comprise pixel electrode, pixel electrode is connected with drain electrode by passivation layer via hole.
Particularly, complete on the underlay substrate of said structure figure, adopt the method for magnetron sputtering or thermal evaporation, deposit transparent conductive film, transparent conductive film can adopt the materials such as tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide, also can adopt other metal and metal oxide.Adopt normal masks plate by composition technique, to form the figure that comprises pixel electrode, pixel electrode is formed in pixel region, by passivation layer via hole, is connected with drain electrode.
For the array base-plate structure shown in embodiment mono-, it only need to form the first grid line and corresponding first grid electrode by upside or the downside at underlay substrate in step 11.
The array base palte that method by the present embodiment forms, before data line charges to pixel electrode, can be by driving the first grid line respectively opposite polarity two data lines of voltage reversal to be communicated with, the pixel electrode that is connected respectively with opposite polarity two data lines of voltage reversal is communicated with, thus in and the electric charge of pixel electrode.Therefore,, closing the first grid line while adopting data line to charge to pixel electrode, can significantly reduce power consumption.
Fig. 9 is the process flow diagram of the driving method embodiment mono-of liquid crystal display of the present invention, and the method for the present embodiment can be for the liquid crystal display described in driving above-described embodiment, and as shown in Figure 9, the method for the present embodiment comprises:
Step 21, when driving grid line corresponding to every row pixel region, drive the first grid line so that the on-off element connecting with described the first grid line by the data line corresponding with this on-off element to being communicated with;
Step 22, close described the first grid line, keep the grid line of driven row to open, and driving data lines is charged to this row pixel region.
Particularly, take progressive scan mode as example, when grid line corresponding to the first row pixel region opened, open the first grid line, now for the first row pixel region, two data lines that are connected with same on-off element are communicated with, and the pixel electrode being also connected respectively with these two data lines is communicated with.Therefore, the electric charge on these two pixel electrodes can be realized neutralization, then close the first grid line and make insulated from each other between data line and keep the grid line of the first row pixel still to open, then driving data lines is to the pixel electrode charging of the first row pixel.So far, can complete the charging process of the first row pixel region, to the charge type of the second row pixel seemingly, repeat no more.It should be noted that, as long as the state that the is held open time of the first grid line meets between the time point that the time point opened at grid line and data line open in the present embodiment.
Further, structure for the array base palte embodiment bis-shown in Fig. 6 and Fig. 7, the method of the present embodiment can drive the first grid line that is separately positioned on the upper and lower both sides of array base palte, so that be connected with described the first grid line and two the first film transistors between every pair of adjacent data line are communicated with adjacent pair of data lines respectively.Adopt this type of drive can reduce signal delay.
The method of the present embodiment, before data line charges to pixel electrode, can be by driving the first grid line respectively opposite polarity two data lines of voltage reversal to be communicated with, the pixel electrode that is connected respectively with opposite polarity two data lines of voltage reversal is communicated with, thus in and the electric charge of pixel electrode.Therefore,, closing the first grid line while adopting data line to charge to pixel electrode, can significantly reduce power consumption.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can complete by the relevant hardware of programmed instruction, aforesaid program can be stored in a computer read/write memory medium, this program, when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (9)
1. an array base palte, comprise the grid line being formed on underlay substrate, data line and public electrode wire, in the pixel region that described grid line and described data line limit, form pixel electrode and thin film transistor (TFT), it is characterized in that, also comprise: the first grid line and with a plurality of data lines in described data line to corresponding respectively on-off element, described data line equals half of described data line number to the number by opposite polarity two data lines of voltage reversal form and described data line is right, described the first grid line is arranged at least one side in the upper and lower both sides of described underlay substrate, described on-off element and data line to and described the first grid line be connected, described on-off element is under the control of described the first grid line, by the data line corresponding with described on-off element to conducting,
A plurality of on-off elements are connected with the first grid line, and each on-off element is used for controlling a data line pair, and the quantity of on-off element equals the right quantity of data line;
When driving grid line corresponding to every row pixel region, drive described the first grid line so that the on-off element connecting with described the first grid line by the data line corresponding with this on-off element to being communicated with;
Close described the first grid line, keep the grid line of driven row to open, and driving data lines is charged to this row pixel region.
2. array base palte according to claim 1, it is characterized in that, described on-off element be arranged on the upper and lower both sides of described underlay substrate and with each data line to two corresponding the first film transistors, described the first grid line is separately positioned on the upper and lower both sides of described underlay substrate, and in described two the first film transistors, the first grid electrode of each thin film transistor (TFT) is connected with the first grid line of this first film transistor place side, transistorized the first source electrode of described two the first films is connected with a data line of described data line centering, transistorized the first drain electrode of described two the first films is connected with another data line of described data line centering.
3. array base palte according to claim 1 and 2, is characterized in that, described data line is to being two adjacent data lines.
4. a liquid crystal panel, comprises array base palte and color membrane substrates that box is arranged, between described array base palte and color membrane substrates, is filled with liquid crystal layer, it is characterized in that, described array base palte adopts the array base palte described in arbitrary claim in claim 1～3.
5. a liquid crystal display, comprises outside framework and liquid crystal panel, it is characterized in that: described liquid crystal panel adopts liquid crystal panel claimed in claim 4.
6. a manufacture method for array base palte as claimed in claim 2, is included in the step that forms conductive pattern on underlay substrate, it is characterized in that, also comprises:
While forming the grid line in described conductive pattern, in the both sides up and down of described underlay substrate, form described the first grid line and described first grid electrode;
While forming source electrode, the drain electrode of data line in described conductive pattern, thin film transistor (TFT), in the upper and lower both sides of described underlay substrate, form transistorized the first source electrode of described the first film and the first drain electrode, transistorized the first source electrode of described the first film is connected with a data line of described data line centering, and transistorized the first drain electrode of described two the first films is connected with another data line of described data line centering.
7. the manufacture method of array base palte according to claim 6, is characterized in that, described method specifically comprises:
Step 11, on underlay substrate, deposit grid metallic film, by composition technique, form the figure that comprises grid line, gate electrode and public electrode wire, in the both sides up and down of described underlay substrate, form described the first grid line and first grid electrode;
Step 12, on the underlay substrate of completing steps 11, deposit gate insulation layer, semiconductive thin film, doped semiconductor films and metallic film is leaked in source, by composition technique, form the figure that comprises active layer, data line, drain electrode, source electrode and TFT raceway groove, and above described first grid electrode, form transistorized the first active layer of the first film, the first source electrode, the first drain electrode and a TFT raceway groove, and described the first source electrode is connected with a data line of described data line centering, and described the first drain electrode is connected with another data line of described data line centering;
Step 13, on the underlay substrate of completing steps 12 deposit passivation layer, by composition technique, form the figure comprise passivation layer via hole, described passivation layer via hole is positioned at the top of drain electrode;
Step 14, on the underlay substrate of completing steps 13 deposit transparent conductive film, by composition technique, form the figure comprise pixel electrode, pixel electrode is connected with drain electrode by passivation layer via hole.
8. for driving a driving method for liquid crystal display claimed in claim 5, it is characterized in that, comprising:
When driving grid line corresponding to every row pixel region, drive described the first grid line so that the on-off element connecting with described the first grid line by the data line corresponding with this on-off element to being communicated with;
Close described the first grid line, keep the grid line of driven row to open, and driving data lines is charged to this row pixel region.
9. driving method according to claim 8, is characterized in that, described the first grid line of described driving so that the on-off element connecting with described the first grid line by the data line corresponding with this on-off element to being communicated with, comprising:
Driving is separately positioned on the first grid line of the upper and lower both sides of array base palte so that connect with described the first grid line and with each data line to two corresponding the first film transistors by this data line to being communicated with.
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| US9286844B2 (en) | 2013-07-09 | 2016-03-15 | Shenzhen China Star Optoelectronics Technology Co., Ltd | LC panel having switch unit, and LCD device having switch unit |
| CN103345094B (en) * | 2013-07-09 | 2016-06-29 | 深圳市华星光电技术有限公司 | A kind of liquid crystal panel, driving method and liquid crystal indicator |
| TWI563481B (en) * | 2014-05-06 | 2016-12-21 | Novatek Microelectronics Corp | Source driver, driving circuit and display apparatus |
| KR102237039B1 (en) * | 2014-10-06 | 2021-04-06 | 주식회사 실리콘웍스 | Source driver and display device comprising the same |
| CN105679275A (en) * | 2016-04-25 | 2016-06-15 | 厦门天马微电子有限公司 | Driving circuit of display panel, display panel and driving method of display panel |
| CN107180620B (en) * | 2017-07-27 | 2019-10-25 | 京东方科技集团股份有限公司 | Display panel control circuit, the driving method of display panel and display device |
| CN109509444B (en) * | 2018-12-19 | 2021-07-06 | 惠科股份有限公司 | Control circuit of display panel, display device and control method |
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| KR20070023099A (en) * | 2005-08-23 | 2007-02-28 | 엘지.필립스 엘시디 주식회사 | Liquid Crystal Display and Driving Method Thereof |
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| CN101135821A (en) * | 2006-08-30 | 2008-03-05 | 奇美电子股份有限公司 | Drive method and system of liquid crystal display board |
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