CN102339796A - Production method for and structure of accumulation-mode complementary metal oxide semiconductor (CMOS) device - Google Patents
Production method for and structure of accumulation-mode complementary metal oxide semiconductor (CMOS) device Download PDFInfo
- Publication number
- CN102339796A CN102339796A CN201010232797XA CN201010232797A CN102339796A CN 102339796 A CN102339796 A CN 102339796A CN 201010232797X A CN201010232797X A CN 201010232797XA CN 201010232797 A CN201010232797 A CN 201010232797A CN 102339796 A CN102339796 A CN 102339796A
- Authority
- CN
- China
- Prior art keywords
- side wall
- substrate
- silicon layer
- gate line
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a production method for an accumulation-mode complementary metal oxide semiconductor (CMOS) device. A complete dual-well field effect transistor is produced through at most five times of mask photo-etching and the process flow is greatly simplified; since an accumulation-mode CMOS does not require for ion implantation and impurity diffusion to form a source/drain region, the thermal budget of the process is reduced; and moreover, since the isolation between an nMOS active region and a pMOS active region and between source/drain contact and grid contact is realized through self alignment, the damage caused by misalignment to the size of the device is reduced.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, the manufacturing approach and the structure thereof of particularly a kind of accumulation type (accumulation-mode) cmos device.
Background technology
Shown in Figure 1 is typical two trap (nMOS and pMOS) cmos process flows in the prior art.In technological process shown in Figure 1, from forming two traps, need implement photo etched mask at least ten times to forming metal closures, the complex process cost is high.And in this process; Repeatedly use ion doping technique; As falling dopant well, source/drain region injection, lightly doped drain processing steps such as (LDD); On the one hand it has increased the heat budget of high annealing unfriendly, and the random fluctuation that also causes on the other hand mixing (random-doping fluctuation, RDF).In addition, Alignment Process is often adopted in the formation that contacts in the prior art, and along with dwindling of device size, it is also more obvious to the infringement of design size to lose aligning (mis-alignment).Therefore, with preparation technology's flow process of simplifying cmos device, to reduce cost, reduce various defectives among the preparation technology be that the new method exploitation of target becomes one of this area research focus.
Summary of the invention
The object of the invention is intended to one of solve the problems of the technologies described above at least; Especially propose a kind of preparation method of accumulation type CMOS structure, simplify technological process greatly, and avoid high-temperature thermal annealing; Reduce the heat budget of whole flow process, reduce and lose the infringement of aiming at device size.
For achieving the above object, one aspect of the present invention proposes a kind of manufacturing approach of accumulation type CMOS structure, and comprising: A. forms first substrate, said first substrate comprise semiconductor substrate with its on the silicon layer of first doping type; B. implement photoetching (Mask 1) on said first substrate, to form at least one protruding platform area and at least one recessed platform area, said protruding platform area comprises the silicon layer of said first doping type, and said recessed platform area does not comprise the silicon layer of said first doping type; C. on the interface of said protruding platform area and recessed platform area, form first side wall, as first shallow-trench isolation; D. on the substrate of said recessed platform area, form the silicon layer of second doping type; E. cover said first substrate and form second substrate, the said device that overturns makes said second substrate be positioned at the bottom; F. remove the semiconductor substrate of said first substrate be positioned at the top, with the silicon layer that exposes said first doping type and the silicon layer of second doping type; G. on said second substrate, form gate material layers, and implement photoetching (Mask 3) to form at least one gate line, said gate line is across said first side wall and run through the silicon layer of said first doping type and the silicon layer of second doping type; H. the sidewall at the said gate line and first side wall forms second side wall and the 3rd side wall respectively; I. form source/drain region metal material layer in said gate line both sides and implement photoetching (Mask 4), the said source of partial etching/drain region metal material layer contacts with the source/drain region of formation source/drain region and lifting; J. implement photoetching (Mask 5), the said gate line of partial etching is to form the grid contact that promotes.
In alternative embodiment of the present invention, after step D, also comprise: implement photoetching (Mask 2) to form second shallow-trench isolation, be used to isolate adjacent devices.
In preferred embodiment of the present invention, the grid contact that promotes described in the step J is formed on the intersection of the said gate line and first side wall.
The present invention proposes a kind of accumulation type cmos device of making according to said method on the other hand, it is characterized in that, comprising: substrate; Be formed at least one nMOS district and a pMOS district on the said substrate; And first side wall that is formed on conduct first shallow-trench isolation between said nMOS district and the pMOS district; Wherein, Said nMOS district and pMOS district comprise respectively: be formed at least one gate line on the said substrate, be formed with the grid contact of lifting on the said gate line; Be formed on second side wall of said gate line both sides, and the 3rd side wall that is formed on the said first side wall both sides; Be formed on the source/drain region that reaches said gate line both sides on the said substrate, be formed with source/drain region contact of lifting on said source/drain region.
In alternative embodiment of the present invention, said device comprises second shallow-trench isolation, to isolate adjacent devices.
In preferred embodiment of the present invention, the contact of the grid of said lifting is formed on the intersection of the said gate line and first side wall.
The manufacturing approach of the accumulation type CMOS structure that proposes through the present invention is only implemented to be no more than 5 photo etched masks and is produced complete two trap field-effect transistors (FET), has simplified technological process greatly; And, adopt accumulation type MOSFET as thin as a wafer, do not need diffusion impurity to form source/drain region, thereby reduced heat budget; In addition, the autoregistration of isolating through the realization of side wall technology between nMOS and the pMOS active area, and the autoregistration of isolating through the selective etch realization between source/drain region contact and the grid contact is lost the infringement of aiming at device size thereby reduce.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
Fig. 1 is typical two trap cmos process flow figure in the prior art;
Fig. 2 is the flow chart of manufacturing approach of the accumulation type cmos device of the embodiment of the invention;
Fig. 3-44 is the intermediate steps sketch map of manufacturing approach shown in Figure 2;
Figure 45-50 is the structural representation of the accumulation type cmos device of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
One aspect of the present invention; A kind of manufacturing approach of accumulation type cmos device is proposed; Only produce complete two trap FET devices through being no more than 5 masking process; Simplified technological process greatly, and, greatly reduced heat budget because accumulation type CMOS does not need ion to inject and diffusion of impurities forms source/drain region.
As shown in Figure 1, the flow chart for the manufacturing approach of the accumulation type cmos device of the embodiment of the invention below will combine sketch map to specifically describe each step:
Steps A forms first substrate, and said first substrate comprises the silicon layer 102 of semiconductor substrate 100 and first doping type on it, and is as shown in Figure 3.Semiconductor substrate 100 can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to the film of monocrystalline silicon, monocrystalline germanium, single-crystal silicon Germanium, GaAs, polysilicon, polycrystalline germanium, polycrystalline silicon germanium or any III/V compound semiconductor and combination thereof.Particularly, in the preferred embodiment of the invention, semiconductor substrate 100 adopts body silicon silicon chip, and forms epitaxial loayer 101, the SiGe layer of for example growing on its surface; Follow the silicon layer 102 of epitaxial growth original position first doping type, for example the n type mixes; Form oxide skin(coating) 103 then, for example silica.Wherein, preferably, the thickness of epitaxial loayer 101 is 10-100nm, and the thickness of silicon layer 102 is 2-5nm.
Step B; Implement photoetching (Mask 1) on said first substrate, to form at least one protruding platform area 200 and at least one recessed platform area 201 (accompanying drawing of the embodiment of the invention is that example is described with the structure that comprises two protruding platform area and two recessed platform area all); Said protruding platform area 200 comprises the silicon layer 102 of said first doping type, and said recessed platform area 201 does not comprise the silicon layer of said first doping type, shown in Fig. 4-6; Wherein, Fig. 4 is a stereogram, and Fig. 5 is a vertical view, and Fig. 6 is the profile along Fig. 3 section line AA '.Particularly, on said first substrate, apply photoresist, photoetching is carried out in utilization mask (Mask 1) for the first time; To form the photoresist protective layer of patterning, not protected oxide skin(coating) 103 of etching and silicon layer 102 successively then, partial etching epitaxial loayer 101; Preferably; The etch thicknesses of epitaxial loayer is 10-40nm, removes photoresist at last, forms figure platform area 200 shown in Figure 3 and recessed platform area 201.
Step C forms first side wall 104 on the interface of said protruding platform area 200 and recessed platform area 201, as the first shallow-trench isolation STI, shown in Fig. 7-8, wherein, Fig. 7 is a vertical view, and Fig. 8 is the profile along Fig. 7 section line AA '.Preferably, the degree of depth of the height of first side wall 104 and recessed platform area 201 is suitable basically.First side wall 104 can be by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low K dielectrics material and combination thereof; And/or other suitable materials formation, can form through the method that comprises the dielectric substance that atomic deposition method, plasma reinforced chemical meteorology deposition or additive method deposition are suitable.
Step D, the silicon layer 105 of formation second doping type on the substrate of said recessed platform area 201, shown in Fig. 9-12, wherein, Fig. 9 is a stereogram, and Figure 10 is a vertical view, and Figure 11 and Figure 12 are respectively along the profile of Figure 10 section line AA ' and BB '.In a preferred embodiment, before the silicon layer that forms second doping type, growth SiGe layer epitaxial loayer on the substrate of recessed platform area 201, for example SiGe makes its height concordant basically with the height of the SiGe layer epitaxial loayer 101 of protruding platform area 200.Below two SiGe layer epitaxial loayers with said recessed platform area and protruding platform area are referred to as SiGe layer epitaxial loayer 400; The then silicon layer 105 of epitaxial growth original position second doping type, for example the p type mixes, and the thickness of said silicon layer 105 is identical with silicon layer 102, for example 2-5nm preferably; Form oxide skin(coating) 106 then, said oxide skin(coating) 106 is preferred identical with oxide skin(coating) 103, as is silica.Following accumulation type FET structure will be formed on the said doped silicon layer 102 and 105 as thin as a wafer; Improve the grid leakage current thereby reach; Reduce the purpose of short-channel effect; And, adopt epitaxial growth method to form said doped silicon layer, can effectively control the fluctuating range of the thickness and then the oxide-semiconductor control transistors threshold voltage of silicon layer.In addition, the implication of the said opposite doping type of claim 5 is: if first doping type is the n type, then second doping type is the p type; If first doping type is the p type, then second doping type is the n type.The present invention is that example is described with the former only, those skilled in the art will appreciate that and takes the said situation of the latter can realize the present invention equally.So far, nMOS active area and pMOS active area form respectively, and the isolation between the two forms with self aligned mode through side wall technology, lose the infringement of aiming at device size thereby reduce.
Selectively, then implement photoetching (Mask 2), be used to isolate adjacent devices to form second shallow-trench isolation 300, shown in figure 10.Particularly, etching oxide layer 106, oxide skin(coating) 103, doped silicon layer 102 or 105 are the stop surface with epitaxial loayer 400 successively.
Preferably, then on recessed platform area 201, form covering, make it highly equal with protruding platform area 200.Particularly, can deposition of nitride layer 107, like SiN, and carry out planarization; Like chemico-mechanical polishing (CMP), be the stop surface with oxide skin(coating) 106, shown in Figure 13-15; Wherein, Figure 13 is a vertical view, and Figure 14 and Figure 15 are respectively along the profile of Figure 13 section line AA ' and BB '.
Step e covers said first substrate and forms second substrate 500, and this device that overturns, and makes said second substrate 500 be positioned at the bottom, and shown in Figure 16-18, wherein, Figure 16 is a vertical view, and Figure 17 and Figure 18 are respectively along the profile of Figure 16 section line AA ' and BB '.Particularly; Can stick a block semiconductor substrate as second substrate 500 at said first substrate surface; Its material can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to the film of monocrystalline silicon, monocrystalline germanium, single-crystal silicon Germanium, GaAs, polysilicon, polycrystalline germanium, polycrystalline silicon germanium or any III/V compound semiconductor and combination thereof.
Step F; Removal is positioned at the semiconductor substrate 100 of first substrate at top, with the silicon layer 102 that exposes said first doping type and the silicon layer 105 of second doping type, shown in Figure 19-22; Wherein, Figure 19 is a stereogram, and Figure 20 is a vertical view, and Figure 21 and Figure 22 are respectively along the profile of Figure 20 section line AA ' and BB '.Particularly; Overturn after this device; To be positioned at bottom second substrate 500 is substrate; Be positioned at the semiconductor substrate 100 and epitaxial loayer 400 at top successively through wet method (like hydrofluoric acid) selective corrosion, make first shallow-trench isolation 104 and second shallow-trench isolation 300 protrude in second substrate surface, shown in figure 19.
Step G; On said second substrate 500, form gate material layers; And implement photoetching (Mask 3) to form at least one gate line 111 (embodiment of the invention is that example is described with three gate lines), said gate line is across said first side wall 104 and run through the silicon layer 102 of said first doping type and the silicon layer 105 of second doping type.Shown in Figure 23-26, wherein, Figure 23 is a stereogram, and Figure 24 is a vertical view, and Figure 25 and Figure 26 are respectively along the profile of Figure 24 section line AA ' and BB '.Particularly; Gate material layers comprises gate dielectric layer 108 and grid layer 109, and the formation of gate dielectric layer 108 and grid layer 109 can be adopted conventional depositing technics, for example sputter, PLD, MOCVD, ALD, PEALD or other suitable methods; Gate dielectric layer 108 can be thermal oxide layer; Comprise silica, silicon nitride and high K medium material, wherein, the high K medium material comprises like hafnium oxide (HfO
2), hafnium silicon oxide (HfSiO), nitrogen hafnium silicon oxide (HfSiON), hafnium oxide tantalum (HfTaO), hafnium oxide titanium (HfTiO), hafnium oxide zirconium hafnium sills such as (HfZrO); Grid layer 109 can comprise metal or polysilicon, and grid layer thickness is 30-100nm preferably.Because first shallow-trench isolation 104 and second shallow-trench isolation 300 protrude in the cause of second substrate surface; The gate material layers that forms is higher than other part in first shallow-trench isolation 104 and second shallow-trench isolation, 300 parts; So preferably; Can carry out planarization to second substrate surface, can take deposit monoxide cap layer 110 particularly, like SiO
2, implement CMP again, be the stop surface with grid layer 109.Implement Mask 3 and etching then to form patterned gate line 111.
Step H forms second side wall 112 and the 3rd side wall 113 respectively at the sidewall of the said gate line 111 and first side wall 104, shown in Figure 27-30; Wherein, Figure 27 is a stereogram, and Figure 28 is a vertical view, and Figure 29 and Figure 30 are respectively along the profile of Figure 28 section line AA ' and BB '.In preferred enforcement of the present invention; Second side wall 112 and the 3rd side wall 113 can form simultaneously; For example, at first deposit one deck dielectric substance, anisotropic etching again; Second side wall 112 that forms is equal highly basically with the oxide cap layer 110 on the gate line 111, and the 3rd side wall 113 is equal highly basically with first side wall 104.Because gate line is higher than first side wall, so second side wall, 112 to the three side walls, 113 height.Wherein, second side wall and the 3rd side wall can adopt and the first side wall identical materials, form through the method that comprises the dielectric substance that atomic deposition method, plasma reinforced chemical meteorology deposition or additive method deposition are suitable equally.
Step I forms source/drain region metal material layer 114 in said gate line 111 both sides, and wherein, Figure 31 is a stereogram shown in Figure 31-34, and Figure 32 is a vertical view, and Figure 33 and Figure 34 are respectively along the profile of Figure 32 section line AA ' and BB '.Preferably, at said gate line 111 both sides depositing metal silicides 115, then deposit source/drain region metal material layer 114 on metal silicide 115 carries out planarization, then like CMP.Be with noting; Because what take is the accumulation devices structure, the dopant type in source/drain region is identical with raceway groove, so need not to be mixed and DIFFUSION TREATMENT in source/drain region; Therefore reduced the heat budget of technology; In addition, the formation of metal silicide and metal material layer all is automatically in alignment with source/drain region, thereby can realize further dwindling of device size.
Then; Implement photoetching (Mask 4), the said source of partial etching/drain region metal material layer contacts 116 with the source/drain region of formation source/drain region and lifting, shown in Figure 35-39; Wherein, Figure 35 is a stereogram, and Figure 36 is a vertical view, and Figure 37-39 is respectively along the profile of Figure 35 section line AA ', BB ' and CC '.Wherein, Figure 36 shows Mask 4, i.e. source/drain region contact mask 117.Particularly; The selectivity partial etching is except that by the source the source of mask protection/drain region contact area/drain region material 114; Said partial etching i.e. the top of etching source/drain region metal material layer 114 only; The lower part that is not etched is source/drain region, and the part that is not etched fully then forms the source/drain region contact 116 of lifting.Preferably, the surface after the etching (being the surface in source/drain region) is lower than first side wall 104.
Step J implements photoetching (Mask 5), and the said gate line 111 of partial etching is to form the grid contact 118 that promotes.Shown in Figure 40-44, wherein, Figure 40 is a vertical view, and Figure 41-44 is respectively along the profile of Figure 40 section line AA ', BB ', CC ' and DD '.Particularly; At first etch away the oxide cap layer 110 on the gate line; Implement Mask 5 and selectivity partial etching grid layer 109 then forming the grid contact 118 that promotes, said partial etching, the i.e. top of etching grid layer 109 only; The lower part that is not etched still is gate line, and the part that is not etched fully then forms the grid contact 118 of lifting.Preferably, the gate line after the etching is equal basically with the height in source/drain region.Figure 40 shows Mask 5, i.e. grid contact mask 119 promotes because the gate line 111 and first side wall 104 form in intersection, and is so the grid contact preferably is formed on this intersection, shown in figure 44.But for the intersection that need not form the grid contact, the grid layer 109 that covers on it can be etched fully, is the stop surface with first side wall 104, and is shown in figure 40.To sum up, because the source/drain region contact 116 contact 118 and be and promote and realize through selective etch with grid, so the isolation between the two can realize through autoregistration, thereby reduction mistake aligning is to the infringement of device size.
Alternatively, the present invention also is included in grid contact and source/last step that forms metal closures of drain region contact.Shown in Figure 45-50, wherein, Figure 45 is a vertical view, and Figure 46-50 is respectively along the profile of Figure 45 section line AA ', BB ', CC ', DD ' and EE '.Particularly, deposited oxide cover layer 120 on above-mentioned device is like SiO
2, and carry out planarization, and like CMP, implement damascene known in those skilled in the art (damascene) then, in grid contact 118 and source/drain region contact 116, form metal closures 121 respectively.
The present invention proposes the accumulation type cmos device that the above method of a kind of basis is made on the other hand, and its structure comprises shown in Figure 45-50: Semiconductor substrate 500; Be formed at least one a nMOS district and a pMOS district (accompanying drawing of the embodiment of the invention is that example is described with the device that comprises two nMOS districts and two pMOS districts all) on the said substrate 500; And first side wall 104 that is formed on conduct first shallow-trench isolation between said nMOS district and the pMOS district; Wherein, Said nMOS district and pMOS district comprise respectively: be formed at least one gate line 111 on the said substrate 500, be formed with the grid contact 118 of lifting on the said gate line 111; Be formed on second side wall 112 of said gate line both sides, and the 3rd side wall 113 that is formed on the said first side wall both sides; Be formed on the source/drain region that reaches said gate line 111 both sides on the said substrate 500, be formed with source/drain region contact 116 of lifting on said source/drain region.Wherein, substrate comprises n type and the in-situ doped silicon layer 102 and 105 of p type, and nMOS district and pMOS district are positioned at respectively on said n type silicon layer 102 and the p type silicon layer 105, and said n type silicon layer is equal basically with the height of p type silicon layer, and thickness is 2-5nm preferably; Said device can also preferably include second shallow-trench isolation 300, is used to isolate adjacent devices; Gate line 111 comprises gate dielectric layer 108 and grid layer 109, and preferably, the height of said source/drain region and said gate line is equal basically; Said second side wall 112 is higher than said first side wall 104, and said the 3rd side wall 113 is equal basically with the height of said first side wall 104; Said grid contact 118 is higher than said first side wall 104 and is lower than said second side wall 112; The grid contact 118 of said lifting preferably is formed on the intersection of the said gate line 111 and first side wall 104; The embodiment of the invention is that example describes with the device with three gate lines; And with grid contact design on gate line at interval; But only with this example, the grid position contacting is not limited thereto, and can design according to actual needs.Said source/drain region contact 116 contacts with grid and is formed with metal closures 121 on 118 respectively.
The accumulation type cmos device that the present invention proposes a kind of manufacturing approach of accumulation type cmos device and utilizes this method to make, this method produces complete two trap field-effect transistors through being no more than 5 photo etched masks, has simplified technological process greatly; And this method does not need ion to inject and diffusion of impurities forms source/drain region, thereby has reduced heat budget; In addition, between nFET and the pFET active area, the isolation between and source/drain region contact and the grid contact all realizes through self aligned mode, loses the infringement of aiming at device size thereby reduce.Utilize this method on doped silicon layer as thin as a wafer, to form accumulation type MOSFET, can also reach and improve the grid leakage current, reduce the purpose of short-channel effect.In addition, form said doped silicon layer, can effectively control the thickness of silicon layer through epitaxially grown mode, and then the fluctuating range of oxide-semiconductor control transistors threshold voltage.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art, will be appreciated that range of application of the present invention is not limited to the technology of the specific embodiment of describing in the specification, mechanism, manufacturing, material composition, means, method and step.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (22)
1. the manufacturing approach of an accumulation type cmos device is characterized in that, may further comprise the steps:
A. form first substrate, said first substrate comprises the silicon layer of semiconductor substrate and first doping type on it;
B. implement photoetching (Mask 1) on said first substrate, to form at least one protruding platform area and at least one recessed platform area, said protruding platform area comprises the silicon layer of said first doping type, and said recessed platform area does not comprise the silicon layer of said first doping type;
C. on the interface of said protruding platform area and recessed platform area, form first side wall, as first shallow-trench isolation;
D. on the substrate of said recessed platform area, form the silicon layer of second doping type;
E. cover said first substrate and form second substrate, the said device that overturns makes said second substrate be positioned at the bottom;
F. remove the semiconductor substrate of said first substrate be positioned at the top, with the silicon layer that exposes said first doping type and the silicon layer of second doping type;
G. on said second substrate, form gate material layers, and implement photoetching (Mask 3) to form at least one gate line, said gate line is across said first side wall and run through the silicon layer of said first doping type and the silicon layer of second doping type;
H. the sidewall at the said gate line and first side wall forms second side wall and the 3rd side wall respectively;
I. form source/drain region metal material layer in said gate line both sides and implement photoetching (Mask 4), the said source of partial etching/drain region metal material layer contacts with the source/drain region of formation source/drain region and lifting;
J. implement photoetching (Mask 5), the said gate line of partial etching is to form the grid contact that promotes.
2. the method for claim 1 is characterized in that, forms first substrate in the steps A and also comprises: before forming said silicon layer, form epitaxial loayer.
3. the method for claim 1 is characterized in that, the silicon layer that forms second doping type in the steps A among the silicon layer of formation first doping type and the step D comprises: the silicon that epitaxial growth is in-situ doped.
4. according to claim 1 or claim 2 method is characterized in that step B forms recessed platform area and comprises: the silicon layer and the said epitaxial loayer of partial etching of etching first doping type fully.
5. the method for claim 1 is characterized in that, the doping that said first doping type and said second doping type are opposite types.
6. the method for claim 1 is characterized in that, the silicon layer height of first doping type that forms in the silicon layer of second doping type that forms among the step D and the steps A is equal basically.
7. the method for claim 1 is characterized in that, after step D, also comprises: implement photoetching (Mask 2) to form second shallow-trench isolation, be used to isolate adjacent devices.
8. according to claim 1 or claim 2 method is characterized in that, removes after the semiconductor substrate of said first substrate in the step F, also comprises and removes said epitaxial loayer, so that said first side wall protrudes in said second substrate surface.
9. the method for claim 1 is characterized in that, step G also is included in and forms the oxide cap layer on the said gate line.
10. like claim 1 or 9 described methods; It is characterized in that; Second side wall that forms among the step H is equal basically with the oxide cap layer height on the said gate line, and said second side wall is higher than said first side wall, and said the 3rd side wall is equal basically with said first height of side wall.
11. the method for claim 1 is characterized in that, the source that forms among the step I/drain region metal material layer is higher than said first side wall and is lower than said second side wall.
12. like claim 1 or 9 described methods, it is characterized in that, after step I, also comprise: remove said oxide cap layer.
13. the method for claim 1 is characterized in that, the grid contact that promotes among the step J is formed on the intersection of the said gate line and first side wall.
14. the method for claim 1 is characterized in that, the gate line height behind the source/drain region that forms described in the step I and the partial etching described in the step J is equal basically.
15. an accumulation type cmos device of making according to the method for claim 1 is characterized in that, comprising:
Substrate;
Be formed at least one nMOS district and a pMOS district on the said substrate; And first side wall that is formed on conduct first shallow-trench isolation between said nMOS district and the pMOS district; Wherein, Said nMOS district and pMOS district comprise respectively: be formed at least one gate line on the said substrate, be formed with the grid contact of lifting on the said gate line; Be formed on second side wall of said gate line both sides, and the 3rd side wall that is formed on the said first side wall both sides; Be formed on the source/drain region that reaches said gate line both sides on the said substrate, be formed with source/drain region contact of lifting on said source/drain region.
16. accumulation type cmos device as claimed in claim 15 is characterized in that, said substrate comprises n type and the in-situ doped silicon layer of p type, and said nMOS district and pMOS district are positioned at respectively on the in-situ doped silicon layer of said n type and p type.
17. accumulation type cmos device as claimed in claim 16 is characterized in that, said n type silicon layer is equal basically with the height of p type silicon layer.
18. accumulation type cmos device as claimed in claim 15 is characterized in that said device comprises second shallow-trench isolation, to isolate adjacent devices.
19. accumulation type cmos device as claimed in claim 15 is characterized in that, said second side wall is higher than said first side wall, and said the 3rd side wall is equal basically with said first height of side wall.
20. accumulation type cmos device as claimed in claim 15 is characterized in that, said grid contact is higher than said first side wall and is lower than said second side wall.
21. accumulation type cmos device as claimed in claim 15 is characterized in that, the grid contact of said lifting is formed on the intersection of the said gate line and first side wall.
22. accumulation type cmos device as claimed in claim 15 is characterized in that, said source/drain region is equal basically with said gate line height.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010232797 CN102339796B (en) | 2010-07-15 | 2010-07-15 | Production method for and structure of accumulation-mode complementary metal oxide semiconductor (CMOS) device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010232797 CN102339796B (en) | 2010-07-15 | 2010-07-15 | Production method for and structure of accumulation-mode complementary metal oxide semiconductor (CMOS) device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102339796A true CN102339796A (en) | 2012-02-01 |
| CN102339796B CN102339796B (en) | 2013-09-18 |
Family
ID=45515441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010232797 Active CN102339796B (en) | 2010-07-15 | 2010-07-15 | Production method for and structure of accumulation-mode complementary metal oxide semiconductor (CMOS) device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102339796B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107128A (en) * | 1998-06-02 | 2000-08-22 | Seiko Instruments Inc. | Semiconductor device and method of manufacturing the same |
| US6982460B1 (en) * | 2000-07-07 | 2006-01-03 | International Business Machines Corporation | Self-aligned gate MOSFET with separate gates |
| CN101359626A (en) * | 2008-09-12 | 2009-02-04 | 西安电子科技大学 | Method for preparing nano CMOS integrated circuit by micro process |
-
2010
- 2010-07-15 CN CN 201010232797 patent/CN102339796B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107128A (en) * | 1998-06-02 | 2000-08-22 | Seiko Instruments Inc. | Semiconductor device and method of manufacturing the same |
| US6982460B1 (en) * | 2000-07-07 | 2006-01-03 | International Business Machines Corporation | Self-aligned gate MOSFET with separate gates |
| CN101359626A (en) * | 2008-09-12 | 2009-02-04 | 西安电子科技大学 | Method for preparing nano CMOS integrated circuit by micro process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102339796B (en) | 2013-09-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230275093A1 (en) | Structure And Method For Mosfet Device | |
| US10002794B2 (en) | Multiple gate length vertical field-effect-transistors | |
| TWI584478B (en) | Semiconductor device and method for fabricating the same | |
| US8216906B2 (en) | Method of manufacturing integrated circuit device with well controlled surface proximity | |
| US9349831B2 (en) | Integrated circuit device with well controlled surface proximity and method of manufacturing same | |
| CN102074461B (en) | Semiconductor device and method of fabricating same | |
| US11923253B2 (en) | Integrated circuit structure | |
| US20090174002A1 (en) | Mosfet having a high stress in the channel region | |
| US20130187207A1 (en) | Replacement source/drain finfet fabrication | |
| US20170170287A1 (en) | Vertical field-effect-transistors having multiple threshold voltages | |
| CN104681613A (en) | Fin structure of semiconductor device | |
| US9640660B2 (en) | Asymmetrical FinFET structure and method of manufacturing same | |
| US9653602B1 (en) | Tensile and compressive fins for vertical field effect transistors | |
| CN102339752A (en) | Method for manufacturing semiconductor device based on gate replacement technique | |
| CN102237277B (en) | Semiconductor device and method for forming same | |
| CN102110609B (en) | High-performance semiconductor device and forming method thereof | |
| US10741667B2 (en) | Method of manufacturing a protective stack on a semiconductor fin | |
| CN102254824B (en) | Semiconductor device and forming method thereof | |
| US20180277536A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN103545207A (en) | Semiconductor device manufacturing method | |
| US20160190318A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN103377931B (en) | Semiconductor structure and manufacture method thereof | |
| CN102339796B (en) | Production method for and structure of accumulation-mode complementary metal oxide semiconductor (CMOS) device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |