CN102339330A - Method for dividing physical layout of symmetric circuit - Google Patents
Method for dividing physical layout of symmetric circuit Download PDFInfo
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- CN102339330A CN102339330A CN2010102301645A CN201010230164A CN102339330A CN 102339330 A CN102339330 A CN 102339330A CN 2010102301645 A CN2010102301645 A CN 2010102301645A CN 201010230164 A CN201010230164 A CN 201010230164A CN 102339330 A CN102339330 A CN 102339330A
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Abstract
The invention is suitable for the field of integrated circuit design, and provides a method for dividing a physical layout of a symmetric circuit, which comprises the following steps: reading in a circuit network table and a physical layout; performing circuit analysis according to the circuit netlist to determine a symmetrical sub-circuit; determining the physical layout of the symmetrical sub-circuit by using a circuit and layout consistency checking technology; determining a symmetrical physical layout and an asymmetrical physical layout of the symmetrical sub-circuit; dividing half of the symmetrical physical layout; copying and dividing the other half of the symmetrical physical layout; carrying out secondary forming and dividing on the asymmetric physical layout; and outputting the physical layout after the secondary forming and dividing. According to the embodiment of the invention, after the circuit grid and the physical layout are read in, the symmetrical sub-circuit and the physical layout are determined, the symmetrical physical layout is determined, and is divided, copied and divided, and the asymmetrical physical layout is subjected to secondary forming and division, so that the problem that the actual pattern appearance of the symmetrical physical layout on a chip is asymmetrical and the actual electrical performance of the symmetrical circuit is mismatched due to the existing division technology is solved.
Description
Technical field
The invention belongs to the IC design field, relate in particular to the method that a kind of symmetric circuit physical layout is cut apart.
Background technology
The integrated circuit manufacturing begins from 45nm technology; Particularly at 32nm and 22nm and more under the small-feature-size technology; In order to strengthen characteristic density; Need to use the secondary forming photoetching process, be about to original mask graph and be divided on two masks, in ic manufacturing process, carry out the whole same layer pattern of photoetching making at twice with layer.Physical layout cutting procedure towards secondary light photoetching form technology can make symmetrical originally physical layout be assigned on the different masks; But because system's positioning error of IC etching board; The secondary forming photoetching technique can make the actual graphical pattern of physical layout on chip of symmetry also asymmetric; Increased the mismatch of the actual electric property of symmetric circuit, therefore needed a kind of symmetric circuit physical layout dividing method to guarantee that the figure on the different mask of being divided into of symmetrical physical layout also is symmetrical towards the secondary light photoetching form.
Summary of the invention
The method that the object of the present invention is to provide a kind of symmetric circuit physical layout to cut apart; Be intended to solve prior art and when cutting apart physical layout, can make the actual graphical pattern of physical layout on chip of symmetry asymmetric, increased the problem of the mismatch of the actual electric property of symmetric circuit.
The present invention is achieved in that the method that a kind of symmetric circuit physical layout is cut apart, and this method may further comprise the steps:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to circuit meshwork list, confirm symmetrical electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit;
Half of symmetrical physical layout cut apart;
Second half copy of symmetrical physical layout is cut apart;
Asymmetric physical layout is carried out secondary forming to be cut apart;
Physical layout after the output secondary forming is cut apart.
Another purpose of the embodiment of the invention is to provide a kind of dividing method of stratification multiaxis symmetric circuit physical layout, and this method may further comprise the steps:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said road network table, confirm stratification multiaxis symmetry electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit;
Half of the bottom of said symmetrical physical layout symmetry physical layout cut apart;
The bottom of said symmetrical physical layout and second half copy of upper strata symmetry physical layout are cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
The present invention is after reading in circuit meshwork list and physical layout; Confirm symmetrical electronic circuit and symmetrical physical layout and asymmetric physical layout through circuit analysis; With half of symmetrical physical layout cut apart, second half copy cuts apart; Asymmetric physical layout secondary forming is cut apart, solved prior art and when cutting apart physical layout, can make the problem that the symmetrical actual graphical pattern of physical layout on chip is asymmetric and increased the mismatch of the actual electric property of symmetric circuit.
Description of drawings
Fig. 1 is the realization flow figure of the method cut apart of symmetric circuit physical layout that the embodiment of the invention provides;
Fig. 2 be the embodiment of the invention provide carry out the process flow diagram that the method for symmetrical electronic circuit is confirmed in circuit analysis according to circuit meshwork list;
Fig. 3 is the process flow diagram of method of symmetrical physical layout and the asymmetric physical layout of definite symmetrical electronic circuit of providing of the embodiment of the invention;
Fig. 4 is the realization flow figure of the method cut apart of stratification multiaxis symmetric circuit physical layout that the embodiment of the invention provides;
Fig. 5 be the embodiment of the invention provide pass through the process flow diagram that the method for stratification multiaxis symmetry electronic circuit is confirmed in circuit analysis;
Fig. 6 is the process flow diagram of method of symmetrical physical layout and the asymmetric physical layout of the definite stratification multiaxis symmetry electronic circuit that provides of the embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention is after reading in circuit meshwork list and physical layout; Confirm symmetrical electronic circuit and symmetrical physical layout and asymmetric physical layout through circuit analysis; Half is cut apart with symmetrical physical layout, second half copy cuts apart; Asymmetric physical layout is carried out secondary forming cut apart, and export the physical layout after secondary forming is cut apart.
The embodiment of the invention is achieved in that the method that a kind of symmetric circuit physical layout is cut apart, and said method comprising the steps of:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said circuit meshwork list, confirm symmetrical electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of said symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit;
Half of said symmetrical physical layout cut apart;
Second half copy of said symmetrical physical layout is cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
Another purpose of the embodiment of the invention is to provide a kind of dividing method of stratification multiaxis symmetric circuit physical layout, said method comprising the steps of:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said road network table, confirm stratification multiaxis symmetry electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit;
Half of the bottom of said symmetrical physical layout symmetry physical layout cut apart;
The bottom of said symmetrical physical layout and second half copy of last layer symmetry physical layout are cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
Below in conjunction with accompanying drawing and embodiment, the present invention done specifically details are as follows:
Embodiment:
The realization flow of the method that the symmetric circuit physical layout that Fig. 1 shows the embodiment of the invention to be provided is cut apart, details are as follows:
In step S101, read in circuit meshwork list and physical layout;
In step S102, carry out circuit analysis according to the circuit meshwork list that reads in and confirm symmetrical electronic circuit;
In step S103, utilize circuit and domain consistency check technology to confirm the physical layout of said symmetrical electronic circuit;
In step S104, search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit;
In step S105, half of symmetrical physical layout cut apart;
In step S106, second half copy of symmetrical physical layout is cut apart;
In step S107, asymmetric physical layout is carried out secondary forming cut apart;
In step S108, the physical layout after the output secondary forming is cut apart.
Read in circuit meshwork list and physical layout;
The embodiment of the invention is through after confirming symmetric circuit to circuit analysis; Utilize circuit and domain consistency check technology to confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit; Half of symmetrical physical layout cut apart; Second half copy is cut apart; And asymmetric physical layout is carried out secondary forming cut apart the physical layout of output secondary forming in back after cutting apart, thereby realized when cutting apart physical layout, can making the actual graphical pattern of physical layout on chip of symmetry symmetrical.
The circuit meshwork list of the embodiment of the invention is that automatic Synthesis goes out the circuit meshwork list that physical layout or hand-designed go out physical layout.
The physical layout of the embodiment of the invention is the physical layout that has all passed through through layout, wiring and follow-up DRC, PE, LVS and post-simulation.
Fig. 2 be the embodiment of the invention provide pass through the method flow that symmetrical electronic circuit is confirmed in circuit analysis, details are as follows:
In step S201, set up digraph according to the circuit meshwork list that reads in;
In step S202, utilize the subgraph isomorphism algorithm in digraph, to seek the coupling subgraph;
In step S203, the external interface that the coupling subgraph is corresponding is confirmed as symmetrical subgraph apart from equidistant two coupling subgraphs of father's circuit input end mouth or output port;
In step S204, it is symmetrical electronic circuit that two corresponding sub-circuit of symmetrical subgraph are set.
The embodiment of the invention utilizes circuit and domain consistency check technology to confirm the physical layout of symmetric circuit, and its concrete realization may further comprise the steps:
Utilize the physical layout extracting tool, from the geometric position that physical layout extracts circuit meshwork list and acquisition device and elementary cell, and the geometric position of the corresponding line of gauze;
The isomorphism algorithm of utilization figure is found out original circuit meshwork list and from the corresponding relation between the circuit meshwork list of physical layout extraction, promptly the corresponding relation of corresponding relation between the device and gauze is confirmed isomorphism electronic circuit device position and physical connection position separately.
As shown in Figure 3, in the embodiment of the invention, search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit, specifically may further comprise the steps:
In step S301, calculate axis of symmetry or symcenter between the symmetrical device between symmetrical electronic circuit two parts;
In step S302, calculate axis of symmetry or symcenter between the symmetrical gauze between symmetrical electronic circuit two parts;
In step S303, seek symmetrical electronic circuit physical layout axis of symmetry or symcenter according to axis of symmetry or the symcenter calculated;
In step S304, setting with symmetrical electronic circuit physical layout axis of symmetry or symcenter is that the device (gauze) of symmetry be the symmetrical device (gauze) of physical geometry, and other device/gauzes are the symmetrical device (gauze) of non-physical geometry.
In the embodiment of the invention, with symmetrical physical layout wherein half is cut apart, adopt existing secondary forming to optimize partitioning algorithm.
Asymmetric physical layout is carried out secondary forming cut apart the existing secondary forming optimization of same employing partitioning algorithm.
In the embodiment of the invention; It is the axis of symmetry/symcenter around symmetrical electronic circuit physical layout that second half copy of symmetric circuit physical layout is cut apart; After half of the bottom of symmetrical physical layout symmetry physical layout being cut apart the figure mirror image of virtual level Layer-XXX-1 that the back forms and Layer-XXX-2, on the same virtual level of correspondence, produce the symmetrical figure in physical geometry position.
In the embodiment of the invention; Be divided into two different virtual level Layer-XXX-1 and Layer-XXX-2 after originally cutting apart with the figure of layer Layer-XXX; The physical layout of system level chip after output is cut apart; Application programming interfaces through the physical layout data storehouse deposit the graphical information on these two virtual levels in the physical layout data storehouse, so that follow-up plate-making the time utilizes virtual level Layer-XXX-1 to carry out the secondary forming photoetching with two different masks of graphical information making on the Layer-XXX-2.
The realization flow of the method that the stratification multiaxis symmetric circuit physical layout that Fig. 4 embodiment of the invention provides is cut apart, details are as follows:
In step S401, read in circuit meshwork list and physical layout;
In step S402, carry out circuit analysis according to the circuit meshwork list that reads in and confirm stratification multiaxis symmetry electronic circuit;
In step S403, utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
In step S404, search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit;
In step S405, half of the bottom physical layout of symmetrical physical layout cut apart;
In step S406, the bottom of symmetrical physical layout and second half copy of last layer symmetry physical layout are cut apart;
In step S407, asymmetric physical layout is carried out secondary forming cut apart;
In step S408, the physical layout after the output secondary forming is cut apart.
The circuit meshwork list of the embodiment of the invention is that automatic Synthesis goes out the circuit meshwork list that physical layout or hand-designed go out physical layout, and physical layout is the physical layout that has all passed through through layout, wiring and follow-up DRC, PE, LVS and post-simulation.
In embodiments of the present invention, confirm stratification multiaxis symmetry electronic circuit through circuit analysis, its concrete performing step is following, as shown in Figure 5:
In step S501, set up digraph according to the circuit meshwork list that reads in;
In step S502, utilize the subgraph isomorphism algorithm in digraph, to seek the coupling subgraph;
In step S503, the external interface that the coupling subgraph is corresponding is confirmed as symmetrical subgraph apart from equidistant two coupling subgraphs of father's circuit input end mouth or output port;
In step S504, it is stratification multiaxis symmetry electronic circuit that two corresponding sub-circuit of symmetrical subgraph are set.
In embodiments of the present invention, as shown in Figure 6, the axis of symmetry or the symcenter of searching symmetrical electronic circuit physical layout are confirmed the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit, and its concrete performing step is following:
In step S601, calculate axis of symmetry or symcenter between the symmetrical device between stratification multiaxis symmetry electronic circuit two parts;
In step S602, calculate axis of symmetry or symcenter between the symmetrical gauze between stratification multiaxis symmetry electronic circuit two parts;
In step S603, according to the axis of symmetry or the symcenter of axis of symmetry that calculates or symcenter searching stratification multiaxis symmetry electronic circuit physical layout;
In step S604, setting with said axis of symmetry or symcenter is that the device/gauze of symmetry is the device/gauze of physical geometry symmetry, and other device/gauzes are the symmetrical device/gauze of non-physical geometry.。
To the bottom of stratification multiaxis symmetric circuit physical layout symmetry physical layout wherein half is cut apart, or asymmetric physical layout is carried out secondary forming cut apart and adopt existing secondary forming to optimize partitioning algorithm.
For the bottom of stratification multiaxis symmetry electronic circuit symmetry physical layout is cut apart through the axis of symmetry/symcenter around the symmetrical electronic circuit physical layout of stratification multiaxis with second half copy of last layer symmetry physical layout; After half of the bottom of symmetrical physical layout symmetry physical layout being cut apart the figure mirror image of virtual level Layer-XXX-1 that the back forms and Layer-XXX-2; On the same virtual level of correspondence, produce the figure of physical geometry position symmetry; And from bottom to top; For second half copy of the symmetrical physical layout of each layer is cut apart, until the symmetric case of handling whole levels.
Behind the physical layout of the embodiment of the invention after the output secondary forming is cut apart; Application programming interfaces through the physical layout data storehouse deposit the graphical information on these two virtual levels in the physical layout data storehouse, so that follow-up plate-making the time utilizes virtual level Layer-XXX-1 to carry out the secondary forming photoetching with two different masks of graphical information making on the Layer-XXX-2.
The present invention is after reading in circuit meshwork list and physical layout; Confirm symmetrical electronic circuit and symmetrical physical layout and asymmetric physical layout through circuit analysis; With half of symmetrical physical layout cut apart, second half copy cuts apart; Asymmetric physical layout secondary forming is cut apart, solved prior art and when cutting apart physical layout, can make the problem that the symmetrical actual graphical pattern of physical layout on chip is asymmetric and increased the mismatch of the actual electric property of symmetric circuit.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (17)
1. the method that the symmetric circuit physical layout is cut apart is characterized in that, said method comprising the steps of:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said circuit meshwork list, confirm symmetrical electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of said symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit;
Half of said symmetrical physical layout cut apart;
Second half copy of said symmetrical physical layout is cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
2. the method for claim 1 is characterized in that, said circuit meshwork list is that automatic Synthesis goes out the circuit meshwork list that physical layout or hand-designed go out physical layout.
3. the method for claim 1 is characterized in that, said physical layout is the physical layout that passes through through layout, wiring and follow-up DRC, PE, LVS and post-simulation.
4. the method for claim 1 is characterized in that, saidly carries out circuit analysis according to said circuit meshwork list, confirms that the step of symmetrical electronic circuit specifically comprises:
Circuit meshwork list according to reading in is set up digraph;
Utilize the subgraph isomorphism algorithm in said digraph, to seek the coupling subgraph;
The external interface that the coupling subgraph is corresponding is confirmed as symmetrical subgraph apart from equidistant two coupling subgraphs of father's circuit input end mouth or output port;
It is symmetrical electronic circuit that two corresponding sub-circuit of said symmetrical subgraph are set.
5. the method for claim 1 is characterized in that, said circuit and the domain consistency check technology utilized confirms that the step of the physical layout of symmetrical electronic circuit specifically comprises:
Utilize the physical layout extracting tool, from the geometric position that physical layout extracts circuit meshwork list and acquisition device and elementary cell, and the geometric position of the corresponding line of gauze;
Utilize the isomorphism algorithm of figure, find out original circuit meshwork list and said, confirm said symmetrical electronic circuit two parts device position and physical connection position separately from the corresponding relation between the circuit meshwork list of physical layout extraction.
6. the method for claim 1 is characterized in that, said axis of symmetry or symcenter of searching said symmetrical electronic circuit physical layout confirms that the step of the symmetrical physical layout of symmetrical electronic circuit specifically comprises:
Calculate axis of symmetry or symcenter between the symmetrical device between symmetrical electronic circuit two parts;
Calculate axis of symmetry or symcenter between the symmetrical gauze between symmetrical electronic circuit two parts;
Axis of symmetry or the symcenter of seeking said symmetrical electronic circuit physical layout according to the axis of symmetry or the symcenter of said calculating;
Setting is that the device/gauze of symmetry is the device/gauze of physical geometry symmetry with said axis of symmetry or symcenter, and other device/gauzes are the device/gauze of non-physical geometry symmetry.
7. the method for claim 1 is characterized in that, said half with said symmetrical physical layout cut apart, or non-ly physical layout is carried out secondary forming cuts apart and all adopt existing secondary forming to optimize partitioning algorithm said.
8. the method for claim 1; It is characterized in that; Said second half copy with said symmetrical physical layout cut apart be the figure mirror image of virtual level Layer-XXX-1 and Layer-XXX-2 after will cutting apart half of said symmetrical physical layout with the axis of symmetry/symcenter of said symmetrical electronic circuit physical layout after, on the same virtual level of correspondence, produce the figure of physical geometry position symmetry.
9. the method for claim 1 is characterized in that, the physical layout after the said secondary forming of said output is cut apart deposits graphical information in the physical layout data storehouse through application programming interfaces.
10. the dividing method of a stratification multiaxis symmetric circuit physical layout is characterized in that, said method comprising the steps of:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said circuit meshwork list, confirm stratification multiaxis symmetry electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit;
Half of the bottom of said symmetrical physical layout symmetry physical layout cut apart;
The bottom of said symmetrical physical layout and second half copy of last layer symmetry physical layout are cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
11. method as claimed in claim 10 is characterized in that, said circuit meshwork list is that automatic Synthesis goes out the circuit meshwork list that physical layout or hand-designed go out physical layout.
12. method as claimed in claim 10 is characterized in that, said physical layout is the physical layout that passes through through layout, wiring and follow-up DRC, PE, LVS and post-simulation.
13. method as claimed in claim 10 is characterized in that, saidly carries out circuit analysis according to said circuit meshwork list, confirms that the step of stratification multiaxis symmetry electronic circuit specifically comprises:
Circuit meshwork list according to reading in is set up digraph;
Utilize the subgraph isomorphism algorithm in said digraph, to seek the coupling subgraph;
The external interface that the coupling subgraph is corresponding is confirmed as symmetrical subgraph apart from equidistant two coupling subgraphs of father's circuit input end mouth or output port;
It is stratification multiaxis symmetry electronic circuit that two corresponding sub-circuit of said symmetrical subgraph are set.
14. method as claimed in claim 10 is characterized in that, said axis of symmetry or symcenter of searching said symmetrical electronic circuit physical layout confirms that the symmetrical physical layout of stratification multiaxis symmetry electronic circuit and the step of asymmetric physical layout specifically comprise:
Calculate axis of symmetry or symcenter between the symmetrical device between stratification multiaxis symmetry electronic circuit two parts;
Calculate axis of symmetry or symcenter between the symmetrical gauze between stratification multiaxis symmetry electronic circuit two parts;
Seek the axis of symmetry or the symcenter of stratification multiaxis symmetry electronic circuit physical layout according to the axis of symmetry of said calculating or symcenter;
Setting is that the device/gauze of symmetry is the device/gauze of physical geometry symmetry with said axis of symmetry or symcenter, and other device/gauzes are the device/gauze of non-physical geometry symmetry.
15. method as claimed in claim 10; It is characterized in that; Half of said bottom symmetry physical layout to said symmetrical physical layout cut apart, or said asymmetric physical layout is carried out secondary forming cuts apart and all adopt existing secondary forming to optimize partitioning algorithm.
16. method as claimed in claim 10; It is characterized in that; It is the axis of symmetry/symcenter around said symmetrical electronic circuit physical layout that second half copy of the said bottom and upper strata symmetry physical layout to said symmetrical physical layout is cut apart; After will cutting apart the figure mirror image of virtual level Layer-XXX-1 that the back forms and Layer-XXX-2 to half of the bottom of said symmetrical physical layout symmetry physical layout, generation physical geometry position symmetric figure on the same virtual level of correspondence.
17. method as claimed in claim 10 is characterized in that, the physical layout after the said secondary forming of said output is cut apart is to deposit graphical information in the physical layout data storehouse through application programming interfaces.
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| CN102542114A (en) * | 2012-01-06 | 2012-07-04 | 深圳市汉普电子技术开发有限公司 | PCB module mirroring method and device based on origin symmetry |
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