CN102339330A - Method for dividing physical layout of symmetric circuit - Google Patents

Method for dividing physical layout of symmetric circuit Download PDF

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Publication number
CN102339330A
CN102339330A CN2010102301645A CN201010230164A CN102339330A CN 102339330 A CN102339330 A CN 102339330A CN 2010102301645 A CN2010102301645 A CN 2010102301645A CN 201010230164 A CN201010230164 A CN 201010230164A CN 102339330 A CN102339330 A CN 102339330A
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physical layout
circuit
symmetrical
symmetry
symmetric
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CN102339330B (en
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吴玉平
陈岚
叶甜春
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The invention is suitable for the field of integrated circuit design, and provides a method for dividing a physical layout of a symmetric circuit, which comprises the following steps: reading in a circuit network table and a physical layout; performing circuit analysis according to the circuit netlist to determine a symmetrical sub-circuit; determining the physical layout of the symmetrical sub-circuit by using a circuit and layout consistency checking technology; determining a symmetrical physical layout and an asymmetrical physical layout of the symmetrical sub-circuit; dividing half of the symmetrical physical layout; copying and dividing the other half of the symmetrical physical layout; carrying out secondary forming and dividing on the asymmetric physical layout; and outputting the physical layout after the secondary forming and dividing. According to the embodiment of the invention, after the circuit grid and the physical layout are read in, the symmetrical sub-circuit and the physical layout are determined, the symmetrical physical layout is determined, and is divided, copied and divided, and the asymmetrical physical layout is subjected to secondary forming and division, so that the problem that the actual pattern appearance of the symmetrical physical layout on a chip is asymmetrical and the actual electrical performance of the symmetrical circuit is mismatched due to the existing division technology is solved.

Description

The method that a kind of symmetric circuit physical layout is cut apart
Technical field
The invention belongs to the IC design field, relate in particular to the method that a kind of symmetric circuit physical layout is cut apart.
Background technology
The integrated circuit manufacturing begins from 45nm technology; Particularly at 32nm and 22nm and more under the small-feature-size technology; In order to strengthen characteristic density; Need to use the secondary forming photoetching process, be about to original mask graph and be divided on two masks, in ic manufacturing process, carry out the whole same layer pattern of photoetching making at twice with layer.Physical layout cutting procedure towards secondary light photoetching form technology can make symmetrical originally physical layout be assigned on the different masks; But because system's positioning error of IC etching board; The secondary forming photoetching technique can make the actual graphical pattern of physical layout on chip of symmetry also asymmetric; Increased the mismatch of the actual electric property of symmetric circuit, therefore needed a kind of symmetric circuit physical layout dividing method to guarantee that the figure on the different mask of being divided into of symmetrical physical layout also is symmetrical towards the secondary light photoetching form.
Summary of the invention
The method that the object of the present invention is to provide a kind of symmetric circuit physical layout to cut apart; Be intended to solve prior art and when cutting apart physical layout, can make the actual graphical pattern of physical layout on chip of symmetry asymmetric, increased the problem of the mismatch of the actual electric property of symmetric circuit.
The present invention is achieved in that the method that a kind of symmetric circuit physical layout is cut apart, and this method may further comprise the steps:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to circuit meshwork list, confirm symmetrical electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit;
Half of symmetrical physical layout cut apart;
Second half copy of symmetrical physical layout is cut apart;
Asymmetric physical layout is carried out secondary forming to be cut apart;
Physical layout after the output secondary forming is cut apart.
Another purpose of the embodiment of the invention is to provide a kind of dividing method of stratification multiaxis symmetric circuit physical layout, and this method may further comprise the steps:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said road network table, confirm stratification multiaxis symmetry electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit;
Half of the bottom of said symmetrical physical layout symmetry physical layout cut apart;
The bottom of said symmetrical physical layout and second half copy of upper strata symmetry physical layout are cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
The present invention is after reading in circuit meshwork list and physical layout; Confirm symmetrical electronic circuit and symmetrical physical layout and asymmetric physical layout through circuit analysis; With half of symmetrical physical layout cut apart, second half copy cuts apart; Asymmetric physical layout secondary forming is cut apart, solved prior art and when cutting apart physical layout, can make the problem that the symmetrical actual graphical pattern of physical layout on chip is asymmetric and increased the mismatch of the actual electric property of symmetric circuit.
Description of drawings
Fig. 1 is the realization flow figure of the method cut apart of symmetric circuit physical layout that the embodiment of the invention provides;
Fig. 2 be the embodiment of the invention provide carry out the process flow diagram that the method for symmetrical electronic circuit is confirmed in circuit analysis according to circuit meshwork list;
Fig. 3 is the process flow diagram of method of symmetrical physical layout and the asymmetric physical layout of definite symmetrical electronic circuit of providing of the embodiment of the invention;
Fig. 4 is the realization flow figure of the method cut apart of stratification multiaxis symmetric circuit physical layout that the embodiment of the invention provides;
Fig. 5 be the embodiment of the invention provide pass through the process flow diagram that the method for stratification multiaxis symmetry electronic circuit is confirmed in circuit analysis;
Fig. 6 is the process flow diagram of method of symmetrical physical layout and the asymmetric physical layout of the definite stratification multiaxis symmetry electronic circuit that provides of the embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention is after reading in circuit meshwork list and physical layout; Confirm symmetrical electronic circuit and symmetrical physical layout and asymmetric physical layout through circuit analysis; Half is cut apart with symmetrical physical layout, second half copy cuts apart; Asymmetric physical layout is carried out secondary forming cut apart, and export the physical layout after secondary forming is cut apart.
The embodiment of the invention is achieved in that the method that a kind of symmetric circuit physical layout is cut apart, and said method comprising the steps of:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said circuit meshwork list, confirm symmetrical electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of said symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit;
Half of said symmetrical physical layout cut apart;
Second half copy of said symmetrical physical layout is cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
Another purpose of the embodiment of the invention is to provide a kind of dividing method of stratification multiaxis symmetric circuit physical layout, said method comprising the steps of:
Read in circuit meshwork list and physical layout;
Carry out circuit analysis according to said road network table, confirm stratification multiaxis symmetry electronic circuit;
Utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
Search the axis of symmetry or the symcenter of said symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit;
Half of the bottom of said symmetrical physical layout symmetry physical layout cut apart;
The bottom of said symmetrical physical layout and second half copy of last layer symmetry physical layout are cut apart;
Said asymmetric physical layout is carried out secondary forming to be cut apart;
Export said secondary forming and cut apart physical layout afterwards.
Below in conjunction with accompanying drawing and embodiment, the present invention done specifically details are as follows:
Embodiment:
The realization flow of the method that the symmetric circuit physical layout that Fig. 1 shows the embodiment of the invention to be provided is cut apart, details are as follows:
In step S101, read in circuit meshwork list and physical layout;
In step S102, carry out circuit analysis according to the circuit meshwork list that reads in and confirm symmetrical electronic circuit;
In step S103, utilize circuit and domain consistency check technology to confirm the physical layout of said symmetrical electronic circuit;
In step S104, search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit;
In step S105, half of symmetrical physical layout cut apart;
In step S106, second half copy of symmetrical physical layout is cut apart;
In step S107, asymmetric physical layout is carried out secondary forming cut apart;
In step S108, the physical layout after the output secondary forming is cut apart.
Read in circuit meshwork list and physical layout;
The embodiment of the invention is through after confirming symmetric circuit to circuit analysis; Utilize circuit and domain consistency check technology to confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit; Half of symmetrical physical layout cut apart; Second half copy is cut apart; And asymmetric physical layout is carried out secondary forming cut apart the physical layout of output secondary forming in back after cutting apart, thereby realized when cutting apart physical layout, can making the actual graphical pattern of physical layout on chip of symmetry symmetrical.
The circuit meshwork list of the embodiment of the invention is that automatic Synthesis goes out the circuit meshwork list that physical layout or hand-designed go out physical layout.
The physical layout of the embodiment of the invention is the physical layout that has all passed through through layout, wiring and follow-up DRC, PE, LVS and post-simulation.
Fig. 2 be the embodiment of the invention provide pass through the method flow that symmetrical electronic circuit is confirmed in circuit analysis, details are as follows:
In step S201, set up digraph according to the circuit meshwork list that reads in;
In step S202, utilize the subgraph isomorphism algorithm in digraph, to seek the coupling subgraph;
In step S203, the external interface that the coupling subgraph is corresponding is confirmed as symmetrical subgraph apart from equidistant two coupling subgraphs of father's circuit input end mouth or output port;
In step S204, it is symmetrical electronic circuit that two corresponding sub-circuit of symmetrical subgraph are set.
The embodiment of the invention utilizes circuit and domain consistency check technology to confirm the physical layout of symmetric circuit, and its concrete realization may further comprise the steps:
Utilize the physical layout extracting tool, from the geometric position that physical layout extracts circuit meshwork list and acquisition device and elementary cell, and the geometric position of the corresponding line of gauze;
The isomorphism algorithm of utilization figure is found out original circuit meshwork list and from the corresponding relation between the circuit meshwork list of physical layout extraction, promptly the corresponding relation of corresponding relation between the device and gauze is confirmed isomorphism electronic circuit device position and physical connection position separately.
As shown in Figure 3, in the embodiment of the invention, search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of symmetrical electronic circuit, specifically may further comprise the steps:
In step S301, calculate axis of symmetry or symcenter between the symmetrical device between symmetrical electronic circuit two parts;
In step S302, calculate axis of symmetry or symcenter between the symmetrical gauze between symmetrical electronic circuit two parts;
In step S303, seek symmetrical electronic circuit physical layout axis of symmetry or symcenter according to axis of symmetry or the symcenter calculated;
In step S304, setting with symmetrical electronic circuit physical layout axis of symmetry or symcenter is that the device (gauze) of symmetry be the symmetrical device (gauze) of physical geometry, and other device/gauzes are the symmetrical device (gauze) of non-physical geometry.
In the embodiment of the invention, with symmetrical physical layout wherein half is cut apart, adopt existing secondary forming to optimize partitioning algorithm.
Asymmetric physical layout is carried out secondary forming cut apart the existing secondary forming optimization of same employing partitioning algorithm.
In the embodiment of the invention; It is the axis of symmetry/symcenter around symmetrical electronic circuit physical layout that second half copy of symmetric circuit physical layout is cut apart; After half of the bottom of symmetrical physical layout symmetry physical layout being cut apart the figure mirror image of virtual level Layer-XXX-1 that the back forms and Layer-XXX-2, on the same virtual level of correspondence, produce the symmetrical figure in physical geometry position.
In the embodiment of the invention; Be divided into two different virtual level Layer-XXX-1 and Layer-XXX-2 after originally cutting apart with the figure of layer Layer-XXX; The physical layout of system level chip after output is cut apart; Application programming interfaces through the physical layout data storehouse deposit the graphical information on these two virtual levels in the physical layout data storehouse, so that follow-up plate-making the time utilizes virtual level Layer-XXX-1 to carry out the secondary forming photoetching with two different masks of graphical information making on the Layer-XXX-2.
The realization flow of the method that the stratification multiaxis symmetric circuit physical layout that Fig. 4 embodiment of the invention provides is cut apart, details are as follows:
In step S401, read in circuit meshwork list and physical layout;
In step S402, carry out circuit analysis according to the circuit meshwork list that reads in and confirm stratification multiaxis symmetry electronic circuit;
In step S403, utilize circuit and domain consistency check technology to confirm the physical layout of symmetrical electronic circuit;
In step S404, search the axis of symmetry or the symcenter of symmetrical electronic circuit physical layout, confirm the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit;
In step S405, half of the bottom physical layout of symmetrical physical layout cut apart;
In step S406, the bottom of symmetrical physical layout and second half copy of last layer symmetry physical layout are cut apart;
In step S407, asymmetric physical layout is carried out secondary forming cut apart;
In step S408, the physical layout after the output secondary forming is cut apart.
The circuit meshwork list of the embodiment of the invention is that automatic Synthesis goes out the circuit meshwork list that physical layout or hand-designed go out physical layout, and physical layout is the physical layout that has all passed through through layout, wiring and follow-up DRC, PE, LVS and post-simulation.
In embodiments of the present invention, confirm stratification multiaxis symmetry electronic circuit through circuit analysis, its concrete performing step is following, as shown in Figure 5:
In step S501, set up digraph according to the circuit meshwork list that reads in;
In step S502, utilize the subgraph isomorphism algorithm in digraph, to seek the coupling subgraph;
In step S503, the external interface that the coupling subgraph is corresponding is confirmed as symmetrical subgraph apart from equidistant two coupling subgraphs of father's circuit input end mouth or output port;
In step S504, it is stratification multiaxis symmetry electronic circuit that two corresponding sub-circuit of symmetrical subgraph are set.
In embodiments of the present invention, as shown in Figure 6, the axis of symmetry or the symcenter of searching symmetrical electronic circuit physical layout are confirmed the symmetrical physical layout and the asymmetric physical layout of stratification multiaxis symmetry electronic circuit, and its concrete performing step is following:
In step S601, calculate axis of symmetry or symcenter between the symmetrical device between stratification multiaxis symmetry electronic circuit two parts;
In step S602, calculate axis of symmetry or symcenter between the symmetrical gauze between stratification multiaxis symmetry electronic circuit two parts;
In step S603, according to the axis of symmetry or the symcenter of axis of symmetry that calculates or symcenter searching stratification multiaxis symmetry electronic circuit physical layout;
In step S604, setting with said axis of symmetry or symcenter is that the device/gauze of symmetry is the device/gauze of physical geometry symmetry, and other device/gauzes are the symmetrical device/gauze of non-physical geometry.。
To the bottom of stratification multiaxis symmetric circuit physical layout symmetry physical layout wherein half is cut apart, or asymmetric physical layout is carried out secondary forming cut apart and adopt existing secondary forming to optimize partitioning algorithm.
For the bottom of stratification multiaxis symmetry electronic circuit symmetry physical layout is cut apart through the axis of symmetry/symcenter around the symmetrical electronic circuit physical layout of stratification multiaxis with second half copy of last layer symmetry physical layout; After half of the bottom of symmetrical physical layout symmetry physical layout being cut apart the figure mirror image of virtual level Layer-XXX-1 that the back forms and Layer-XXX-2; On the same virtual level of correspondence, produce the figure of physical geometry position symmetry; And from bottom to top; For second half copy of the symmetrical physical layout of each layer is cut apart, until the symmetric case of handling whole levels.
Behind the physical layout of the embodiment of the invention after the output secondary forming is cut apart; Application programming interfaces through the physical layout data storehouse deposit the graphical information on these two virtual levels in the physical layout data storehouse, so that follow-up plate-making the time utilizes virtual level Layer-XXX-1 to carry out the secondary forming photoetching with two different masks of graphical information making on the Layer-XXX-2.
The present invention is after reading in circuit meshwork list and physical layout; Confirm symmetrical electronic circuit and symmetrical physical layout and asymmetric physical layout through circuit analysis; With half of symmetrical physical layout cut apart, second half copy cuts apart; Asymmetric physical layout secondary forming is cut apart, solved prior art and when cutting apart physical layout, can make the problem that the symmetrical actual graphical pattern of physical layout on chip is asymmetric and increased the mismatch of the actual electric property of symmetric circuit.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (17)

1.一种对称电路物理版图分割的方法，其特征在于，所述方法包括以下步骤：1. A method for symmetrical circuit physical layout division, is characterized in that, described method comprises the following steps: 读入电路网表和物理版图；Read in the circuit netlist and physical layout; 根据所述电路网表进行电路分析，确定对称子电路；Carrying out circuit analysis according to the circuit netlist to determine a symmetrical sub-circuit; 利用电路和版图一致性检查技术确定所述对称子电路的物理版图；determining the physical layout of the symmetrical sub-circuit using circuit and layout consistency checking techniques; 查找所述对称子电路物理版图的对称轴或对称中心，确定对称子电路的对称物理版图和非对称物理版图；Finding the axis of symmetry or the center of symmetry of the physical layout of the symmetric sub-circuit, and determining the symmetric physical layout and the asymmetric physical layout of the symmetric sub-circuit; 将所述对称物理版图的一半进行分割；dividing half of the symmetrical physical layout; 将所述对称物理版图的另一半拷贝分割；splitting the other half copy of the symmetric physical layout; 对所述非对称物理版图进行二次成形分割；Performing secondary forming segmentation on the asymmetric physical layout; 输出所述二次成形分割之后的物理版图。and outputting the physical layout after the secondary forming division. 2.如权利要求1所述的方法，其特征在于，所述电路网表是自动综合出物理版图或手工设计出物理版图的电路网表。2 . The method according to claim 1 , wherein the circuit netlist is a circuit netlist for automatically synthesizing a physical layout or manually designing a physical layout. 3 . 3.如权利要求1所述的方法，其特征在于，所述物理版图是经布局、布线和后续DRC、PE、LVS以及后仿真通过的物理版图。3. The method according to claim 1, wherein the physical layout is a physical layout that has been placed, routed, followed by DRC, PE, LVS and post-simulation. 4.如权利要求1所述的方法，其特征在于，所述根据所述电路网表进行电路分析，确定对称子电路的步骤具体包括：4. The method according to claim 1, wherein the step of determining a symmetrical sub-circuit by performing circuit analysis according to the circuit netlist specifically includes: 根据读入的电路网表建立有向图；Create a directed graph based on the read-in circuit netlist; 利用子图同构算法在所述有向图中寻找匹配子图；Using a subgraph isomorphism algorithm to find a matching subgraph in the directed graph; 将匹配子图对应的对外联接点距离父电路输入端口或输出端口的距离相等的两个匹配子图确定为对称子图；Determining two matching subgraphs whose corresponding external connection points are at the same distance from the input port or output port of the parent circuit as symmetric subgraphs; 设置所述对称子图对应的两个子电路为对称子电路。The two sub-circuits corresponding to the symmetrical sub-graph are set as symmetrical sub-circuits. 5.如权利要求1所述的方法，其特征在于，所述利用电路和版图一致性检查技术确定对称子电路的物理版图的步骤具体包括：5. The method according to claim 1, wherein the step of determining the physical layout of the symmetrical sub-circuit using the circuit and layout consistency check technology specifically comprises: 利用物理版图提取工具，从物理版图提取电路网表并获取器件和基本单元的几何位置，以及线网对应连线的几何位置；Use the physical layout extraction tool to extract the circuit netlist from the physical layout and obtain the geometric positions of devices and basic units, as well as the geometric positions of the corresponding connections of the net; 利用图的同构算法，找出原来电路网表和所述从物理版图提取的电路网表之间的对应关系，确定所述对称子电路两部分各自的器件位置和物理连线位置。Using the graph isomorphism algorithm, find out the corresponding relationship between the original circuit netlist and the circuit netlist extracted from the physical layout, and determine the respective device positions and physical connection positions of the two parts of the symmetrical sub-circuit. 6.如权利要求1所述的方法，其特征在于，所述查找所述对称子电路物理版图的对称轴或对称中心，确定对称子电路的对称物理版图的步骤具体包括：6. The method according to claim 1, wherein the step of searching for the symmetry axis or symmetry center of the symmetric sub-circuit physical layout, and determining the symmetric physical layout of the symmetric sub-circuit specifically comprises: 计算对称子电路两部分之间对称器件之间的对称轴或对称中心；Calculate the axis of symmetry or the center of symmetry between symmetrical devices between two parts of a symmetrical subcircuit; 计算对称子电路两部分之间对称线网之间的对称轴或对称中心；Calculate the axis of symmetry or the center of symmetry between the symmetric nets between the two parts of the symmetric subcircuit; 根据所述计算的对称轴或对称中心寻找所述对称子电路物理版图的对称轴或对称中心；Finding the symmetry axis or symmetry center of the symmetric subcircuit physical layout according to the calculated symmetry axis or symmetry center; 设定以所述对称轴或对称中心为对称的器件/线网为物理几何对称的器件/线网，其他器件/线网为非物理几何对称的器件/线网。The devices/networks that are symmetrical about the axis of symmetry or the center of symmetry are set as devices/networks that are physically geometrically symmetric, and other devices/networks are devices/networks that are not physically geometrically symmetric. 7.如权利要求1所述的方法，其特征在于，所述将所述对称物理版图的一半进行分割，或对所述非对物理版图进行二次成形分割均采用现有二次成形优化分割算法。7. The method according to claim 1, wherein said dividing half of said symmetrical physical layout, or performing secondary forming segmentation on said non-pair physical layout adopts existing secondary forming optimized segmentation algorithm. 8.如权利要求1所述的方法，其特征在于，所述将所述对称物理版图的另一半拷贝分割是以所述对称子电路物理版图的对称轴/对称中心将对所述对称物理版图的一半分割后的虚拟层Layer-XXX-1和Layer-XXX-2的图形镜像后，在对应的同一虚拟层上产生物理几何位置对称的图形。8. The method according to claim 1, wherein said dividing the other half copy of the symmetrical physical layout is to divide the symmetrical physical layout by the symmetrical axis/symmetry center of the symmetrical sub-circuit physical layout After half of the divided graphics of the virtual layers Layer-XXX-1 and Layer-XXX-2 are mirrored, graphics with symmetrical physical geometric positions are generated on the corresponding same virtual layer. 9.如权利要求1所述的方法，其特征在于，所述输出所述二次成形分割之后的物理版图通过应用程序接口将图形信息存入物理版图数据库。9 . The method according to claim 1 , wherein the outputting the physical layout after the secondary forming is to store graphic information into a physical layout database through an application program interface. 10.一种层次化多轴对称电路物理版图的分割方法，其特征在于，所述方法包括以下步骤：10. A segmentation method of a hierarchical multi-axis symmetrical circuit physical layout, characterized in that the method comprises the following steps: 读入电路网表和物理版图；Read in the circuit netlist and physical layout; 根据所述电路网表进行电路分析，确定层次化多轴对称子电路；Carrying out circuit analysis according to the circuit netlist, and determining a hierarchical multi-axis symmetrical sub-circuit; 利用电路和版图一致性检查技术确定对称子电路的物理版图；Use circuit and layout consistency checking techniques to determine the physical layout of symmetrical subcircuits; 查找所述对称子电路物理版图的对称轴或对称中心，确定层次化多轴对称子电路的对称物理版图和非对称物理版图；Finding the axis of symmetry or the center of symmetry of the physical layout of the symmetric sub-circuit, and determining the symmetric physical layout and the asymmetric physical layout of the hierarchical multi-axis symmetric sub-circuit; 对所述对称物理版图的最底层对称物理版图的一半进行分割；dividing half of the bottommost symmetrical physical layout of the symmetrical physical layout; 对所述对称物理版图的最底层和上一层对称物理版图的另一半拷贝分割；Segmenting the bottom layer of the symmetrical physical layout and the other half copy of the upper symmetrical physical layout; 对所述非对称物理版图进行二次成形分割；Performing secondary forming segmentation on the asymmetric physical layout; 输出所述二次成形分割之后的物理版图。and outputting the physical layout after the secondary forming division. 11.如权利要求10所述的方法，其特征在于，所述电路网表是自动综合出物理版图或手工设计出物理版图的电路网表。11 . The method according to claim 10 , wherein the circuit netlist is a circuit netlist from which a physical layout is automatically synthesized or a physical layout is manually designed. 12.如权利要求10所述的方法，其特征在于，所述物理版图是经布局、布线和后续DRC、PE、LVS以及后仿真通过的物理版图。12. The method according to claim 10, wherein the physical layout is a physical layout that has been placed, routed, followed by DRC, PE, LVS and post-simulation. 13.如权利要求10所述的方法，其特征在于，所述根据所述电路网表进行电路分析，确定层次化多轴对称子电路的步骤具体包括：13. The method according to claim 10, wherein the step of performing circuit analysis according to the circuit netlist to determine a hierarchical multi-axis symmetric sub-circuit specifically comprises: 根据读入的电路网表建立有向图；Create a directed graph based on the read-in circuit netlist; 利用子图同构算法在所述有向图中寻找匹配子图；Using a subgraph isomorphism algorithm to find a matching subgraph in the directed graph; 将匹配子图对应的对外联接点距离父电路输入端口或输出端口的距离相等的两个匹配子图确定为对称子图；Determining two matching subgraphs whose corresponding external connection points are at the same distance from the input port or output port of the parent circuit as symmetric subgraphs; 设置所述对称子图对应的两个子电路为层次化多轴对称子电路。The two sub-circuits corresponding to the symmetrical sub-graph are set as hierarchical multi-axis symmetrical sub-circuits. 14.如权利要求10所述的方法，其特征在于，所述查找所述对称子电路物理版图的对称轴或对称中心，确定层次化多轴对称子电路的对称物理版图和非对称物理版图的步骤具体包括：14. The method according to claim 10, wherein the searching for the axis of symmetry or the center of symmetry of the physical layout of the symmetric sub-circuit determines the symmetric physical layout and the asymmetric physical layout of the hierarchical multi-axis symmetric sub-circuit. The steps specifically include: 计算层次化多轴对称子电路两部分之间的对称器件之间的对称轴或对称中心；Calculate the axis of symmetry or the center of symmetry between the symmetric devices between the two parts of the hierarchical multi-axis symmetric subcircuit; 计算层次化多轴对称子电路两部分之间的对称线网之间的对称轴或对称中心；Calculate the axis of symmetry or the center of symmetry between the symmetric nets between two parts of the hierarchical multi-axis symmetric subcircuit; 根据所述计算的对称轴或对称中心寻找层次化多轴对称子电路物理版图的对称轴或对称中心；Finding the symmetry axis or symmetry center of the hierarchical multi-axis symmetric subcircuit physical layout according to the calculated symmetry axis or symmetry center; 设定以所述对称轴或对称中心为对称的器件/线网为物理几何对称的器件/线网，其他器件/线网为非物理几何对称的器件/线网。The devices/networks that are symmetrical about the axis of symmetry or the center of symmetry are set as devices/networks that are physically geometrically symmetric, and other devices/networks are devices/networks that are not physically geometrically symmetric. 15.如权利要求10所述的方法，其特征在于，所述对所述对称物理版图的最底层对称物理版图的一半进行分割，或对所述非对称物理版图进行二次成形分割均采用现有二次成形优化分割算法。15. The method according to claim 10, wherein said splitting half of the bottommost symmetrical physical layout of said symmetrical physical layout, or performing secondary shaping and segmentation of said asymmetrical physical layout both adopt current There are quadratic shaping optimization segmentation algorithms. 16.如权利要求10所述的方法，其特征在于，所述对所述对称物理版图的最底层和上层对称物理版图的另一半拷贝分割是围绕所述对称子电路物理版图的对称轴/对称中心，将对所述对称物理版图的最底层对称物理版图的一半进行分割后形成的虚拟层Layer-XXX-1和Layer-XXX-2的图形镜像后，在对应的同一虚拟层上产生物理几何位置对称图形。16. The method according to claim 10, wherein the other half copy division of the bottommost and upper symmetrical physical layout of the symmetrical physical layout is around the symmetrical axis/symmetry of the symmetrical sub-circuit physical layout In the center, after dividing the half of the bottom symmetric physical layout of the symmetrical physical layout, the graphics of the virtual layers Layer-XXX-1 and Layer-XXX-2 are mirrored, and the physical geometry is generated on the corresponding virtual layer Positional symmetry graphics. 17.如权利要求10所述的方法，其特征在于，所述输出所述二次成形分割之后的物理版图是通过应用程序接口将图形信息存入物理版图数据库。17 . The method according to claim 10 , wherein the outputting the physical layout after the secondary forming is to store graphic information into a physical layout database through an application program interface.
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