CN102339255A - Nand writing balance processing method - Google Patents

Nand writing balance processing method Download PDF

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CN102339255A
CN102339255A CN2010102299363A CN201010229936A CN102339255A CN 102339255 A CN102339255 A CN 102339255A CN 2010102299363 A CN2010102299363 A CN 2010102299363A CN 201010229936 A CN201010229936 A CN 201010229936A CN 102339255 A CN102339255 A CN 102339255A
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physical
leaf
mapping
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李晓辉
胡胜发
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Guangzhou Ankai Microelectronics Co.,Ltd.
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Anyka Guangzhou Microelectronics Technology Co Ltd
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Abstract

The invention discloses a Nand writing balance processing method which comprises the following operating processes: (1) a certain logic block is in a buffer state, the logic block corresponds to two physical blocks, wherein the first physical block is used as an old data block to be read in firstly; a page mapping relationship between the logic block and the first physical block is one-to-one mapping; the second physical block is used as a buffer block to be read in later, and a page mapping relationship between the logic block and the second physical block is random mapping; (2) according to a write buffer algorithm, the page mapping relationship is established; (3) in the write operation process of the physical blocks, if the buffer block which corresponds to the physical block is overwritten, the housekeeping operation process is triggered; the write operation on the physical operation is finished; meanwhile, the corresponding relationship between the logic block and the buffer block is released. According to the Nand writing balance processing method, the two algorithms of page mapping and block mapping are combined so that the high efficiency of read-write performance is ensured while the occupied memory is substantially reduced.

Description

A kind of Nand writes the Balance Treatment method
Technical field
The present invention relates to a kind of Nand and write the Balance Treatment method.
Background technology
A Nand Flash chip is made up of many (Block), and a piece is made up of a lot of pages or leaves (Page) again, and each piece or page or leaf all have certain erasable number of times, and therefore, prolongation Nand Flash serviceable life, the simplest way was write balance exactly.Write balance, english is Wear-leveling, promptly manages to make each piece to have identical erasing times, every page and all has the identical indegree of writing.Therefore, the sector of file system will be mapped in the different Physical Page in a certain way.Writing balanced algorithm is a kind of basic research topic, and wherein important contents is mapping relations.Follow according to mapping relations, can the present popular balanced algorithm of writing be divided into two types: page or leaf mapping and piece mapping.
Page or leaf mapping algorithm:, set up the relation of penetrating of page or leaf and sector through an array in the internal memory.When searching certain sector, find corresponding page or leaf through this array.Mapping is at random also named in this mapping by the array conversion.Write fashionablely once more when certain sector, need to change the content of mapping array, simultaneously, page or leaf originally should reclaim as invalid page or leaf.The shortcoming of such algorithm is that EMS memory occupation is big, needs idle arrangement simultaneously, when writing continuously, because not free arrangement can cause writing slower and slower.
The piece mapping algorithm: the physical block among the Nand Flash and the logical block of file system are set up mapping relations.Because be the piece mapping, the array length in the internal memory reduces greatly, EMS memory occupation reduces.But the page or leaf in the piece must be corresponding one by one, and this do not have the relation of array conversion to cry mapping one by one yet.Therefore, when certain sector was upgraded, its corresponding whole physical block will be upgraded simultaneously, and readwrite performance relatively also reduces greatly.
Summary of the invention
The object of the present invention is to provide a kind of Nand to write the Balance Treatment method, this method is got up page or leaf mapping and two kinds of algorithm combination of piece mapping simultaneously, can when reducing EMS memory occupation energetically, guarantee the efficient of readwrite performance again.
The object of the invention can be realized through following technical measures:
A kind of Nand writes the Balance Treatment method, comprises the write operation process:
(1) a certain logical block is in writes buffer status: corresponding two physical blocks of said logical block, first physical block is written into earlier as old data block, and the page or leaf mapping relations of this logical block and first physical block are to shine upon one by one; Second physical block writes after as buffer stopper, and the page or leaf mapping relations of this logical block and second physical block are mapping at random;
(2), set up the page or leaf mapping relations according to writing buffer algorithm;
(3) in write operation process to physical block, full if the pairing buffer stopper of this physical block has been write, then trigger the housekeeping operation process, and finish write operation this physical block, discharge the corresponding relation of this logical block simultaneously to said buffer stopper.
The buffer algorithm of writing in the said step (2) adopts the conventional buffer algorithm of writing.
The process of setting up the page or leaf mapping relations in the said step (2) is: the data in the sector that will write sequentially write certain page or leaf of buffer stopper, and according to the numbering of sector and the numbering refresh page mapping array of page or leaf.
Also comprise initialization procedure before in said step (1): allocation block mapping array and the required internal memory of page or leaf mapping array; All physical blocks of scan N and chip upgrade piece mapping array.
The housekeeping operation process of said step (3) is: to being in the logical block of writing buffer status, the data of data block and buffer stopper are merged in the new physical block; The page or leaf mapping relations of said logical block are converted into mapping one by one by shining upon at random.
Said Nand writes the Balance Treatment method and also comprises the read operation process: in the time of need reading certain sector in system, calculate the logical block number (LBN) that need read; According to the mapping of the piece after initialization array, find the pairing physical block of the logical block that will read; If this logical block is being write buffer status, then, find corresponding page or leaf, otherwise directly calculate the corresponding physical page or leaf, and read this Physical Page according to its page or leaf mapping array.
The computing method of said logical block number (LBN) are: the number of pages of logical block number (LBN)=sector number/every.
The said formula that calculates the corresponding physical page or leaf is: the skew of number of pages+sector number in piece that Physical Page=corresponding physical piece * is every.
Nand of the present invention writes the Balance Treatment method, and mapping algorithm is ingenious combines with piece mapping and page or leaf, promptly when read operation, adopts the piece mapping algorithm, when local write operation, and page mapping algorithm of employing, so the advantage of the inventive method is:
1, EMS memory occupation amount aspect: with the piece mapping class seemingly, the mapping array length is the number of blocks of Nand Flash, rather than number of pages amount, and therefore, this method internal memory more shared than the page or leaf mapping algorithm is little, has the EMS memory occupation amount of a small amount of that the piece mapping algorithm had;
2, read aspect of performance: piece shines upon chain type sometimes searches the corresponding page or leaf in certain sector, and this method is similar with the page or leaf mapping algorithm, directly searches through array, thus than piece mapping algorithm read the performance height, have the high-performance of page mapping algorithm;
3, when writing big file: because the sector writes continuously; Arrangement can be optimised: one is in the logical block of writing buffer status; Although the page or leaf mapping is at random; But big file writes and often makes it to satisfy mapping condition one by one, at this moment only need delete old data block, and buffer stopper directly changes new data block into;
4, when writing small documents:, when carrying out write operation, write and once arrived buffer stopper for certain sector that will write; When carrying out housekeeping operation, write again and once arrived new data block.Only that is to say write once more, thus the peak performance loss can to estimate be 1 times; Simple piece mapping algorithm or page or leaf mapping algorithm then possibly write N time more, and the peak performance loss is N-1 times;
5, this method triggers arrangement in real time by write operation, puts in order while promptly write, and does not write continuously and the difference of intermittently writing.But preceding two kinds of algorithms need idle housekeeping operation to come the covert performance that promotes, while it is lower to write the actual efficiency of putting in order.Idle arrangement needs the multithreading support, has increased size of code and memory cost simultaneously.
Description of drawings
Fig. 1 is the process flow diagram that Nand of the present invention writes the write operation process of Balance Treatment method;
Fig. 2 is general mapping transformational relation synoptic diagram;
Fig. 3 is the mapping relations of the piece that writing;
Fig. 4 is the transformational relation synoptic diagram of the arrangement process of the inventive method.
Embodiment
Virtual machine and simulator technology have improved efficiency of software greatly, simultaneously can a large amount of hardware of emulation in addition reality in non-existent hardware.This method simulates the device technology through use, the Nand Flash chip of emulation different size, the integrality of verification algorithm; Then this method is transplanted in the WinCE operating system, in real hardware environment operation, test and validation the practical value of algorithm.To introduce above-mentioned two kinds of embodiments below.The purpose of introducing the simulator embodiment is more clearly to explain the principle of algorithm, and introduces practicality and the beneficial effect of real hardware embodiment in order to proof this method.
Embodiment one: simulator embodiment
Simulated environment is: the total block data of Nand Flash is 8, every 4 pages, and every page of 2K byte; Write buffer stopper 2 physical blocks are arranged; Piece is to number 0 beginning, and the homepage numbering also is 0 in the piece.
The initialization operation process is following:
1) distributes 1 piece mapping array and 2 used internal memories of page or leaf mapping array.
2) all physical blocks of scan N and chip upgrade piece mapping array, reproduction blocks mapping relations, possible mapping relations such as Fig. 2.
3) for buffer stopper, scan each page or leaf, refresh page mapping array is reappeared the page or leaf mapping relations, possible mapping relations such as Fig. 3.
During read operation, adopt mapping conversion as shown in Figure 2.Suppose and to read 17 sectors; Calculate the corresponding logical block in this sector: the number of pages that logical block number=sector number/Nand chip is every under this environment is: 17 sectors/4 page every, because 17 be 1 divided by 4 remainders; Be the 4th logical block after rounding, the piece bias internal is 1.In the piece mapping array of when initialization, setting up, the physical block that can find the mapping of the 4th logical block is 6.Then, calculating the corresponding page or leaf in the 17th sector is: every+piece of physical block 6*4 page or leaf bias internal 1, promptly the 25th page.
During read operation, the logical block that runs into the sector correspondence that will read is in writes buffer status.Shown in accompanying drawing 3, grey blocks is represented to write in the piece mapping array, and points to a page map table; When reading the 17th sector, though piece mapping array still points to 6, this logical block is in writes buffer status; So find the page or leaf mapping array of the 4th logical block,, therefore search array indexing and be 1 element value because the piece bias internal of the 17th sector is 1; So learn the mapping page array of the 17th sector be 29,29 divided by 4 round 7, then it belongs to the 7th physical block.
The housekeeping operation process is as shown in Figure 4: for logical block 4, write buffer status because it is handled, so it has a page or leaf mapping array.Through page or leaf mapping array, the arrangement process has been incorporated into old data block and buffer stopper in certain blank block, and this blank block becomes new data block.Old data block and buffering are recovered as blank block simultaneously.Anatomize page or leaf mapping array and can find that page or leaf mapping array has been pointed to two physical blocks: physical block 6 and physical block 7; Physical block 6 is old data blocks, and it shines upon one by one; Physical block 7 is buffer stoppers, and it shines upon at random.Be which blank block as for new data block, unimportant.This method is used the sequential search method to searching of blank block in order to reach erasable balance, and in fact this method is the most simply and the most effective.
Embodiment two: real hardware embodiment
In WinCE operating system, realized this method.As the instance of product quality level, this method is made as 16 or higher with buffer stopper quantity, has added power down process and dynamic bad block management, and has done a large amount of optimizations.The various operating process of this instance are following:
1) initialization operation:
A) allocation block mapping array and N the used internal memory of page or leaf mapping array.
B) all physical blocks of scan N and chip upgrade piece mapping array, the reproduction blocks mapping relations.
C) to buffer stopper, scan each page or leaf, refresh page mapping array is reappeared the page or leaf mapping relations.
2) read sector operation:
A) calculate logical block.
B) according to piece mapping array, find the corresponding physical piece.
C), then, find corresponding page or leaf, otherwise directly calculate corresponding page or leaf (seeing specific embodiment 1, accompanying drawing 2) according to its page or leaf mapping array if this logical block is being write buffer status.
D) read this page or leaf then.
3) write sector operation: idiographic flow is seen accompanying drawing 1, and concise and to the point function is as follows:
A) write operation is handled certain logical block and is write buffer status, i.e. corresponding two physical blocks of this logical block, and a physical block is written into earlier, i.e. old data block, the page or leaf mapping relations are for shine upon one by one; And write behind another physical block, i.e. buffer stopper, the page or leaf mapping relations are for shine upon at random.The corresponding page or leaf mapping of this logical block array;
B) through writing buffer algorithm, set up the page or leaf mapping relations, like accompanying drawing 1, the sector that will write writes the buffer stopper page or leaf in proper order, and this moment is according to this sector number and write page number change page or leaf mapping array;
C) in case of necessity, under the condition as shown in Figure 1, trigger the housekeeping operation process, therefore the buffer status of writing of certain logical block finishes.
4) housekeeping operation: to being in the logical block of writing buffer status, its two physical blocks are integrated into new physical block, and promptly old data block and buffer stopper are integrated into new data block.Referring to accompanying drawing 4, at this moment, the page or leaf mapping relations of this logical block are converted into mapping one by one by shining upon at random.
The process that merges is exactly the arrangement process of data: for same logical page (LPAGE); Have one or more Physical Page; As a Physical Page is arranged, and one or more Physical Page are arranged in the new physical block in old physical block, have only the Physical Page that writes at last to be only effectively in these Physical Page.The Physical Page that the arrangement process will write at last copies in the new blank block, owing to deleted invalid page or leaf, therefore two physical blocks can merge to a new physical block, in the merging process, guarantees to be mapped as mapping one by one.
FAL algorithm (the FlashAbstract Level of WinCE itself; Chinese meaning: the Flash level of abstraction) be based on the page or leaf mapping; The Nand Flash (containing 4K piece, 512K page or leaf) of 1G is compared test with this algorithm; Wherein FAL does not support the high capacity Nand of MLC and so on originally, and the FAL here is an improved.The data comparative analysis table of the FAL algorithm of WinCE and the inventive method is following:
Figure BSA00000195188800061
Embodiment of the present invention is not limited thereto; Under the above-mentioned basic fundamental thought of the present invention prerequisite;, all drop within the rights protection scope of the present invention modification, replacement or the change of other various ways that content of the present invention is made according to the ordinary skill knowledge of this area and customary means.

Claims (8)

1. a Nand writes the Balance Treatment method, comprises the write operation process, it is characterized in that:
(1) a certain logical block is in writes buffer status: corresponding two physical blocks of said logical block, first physical block is written into earlier as old data block, and the page or leaf mapping relations of this logical block and first physical block are to shine upon one by one; Second physical block writes after as buffer stopper, and the page or leaf mapping relations of this logical block and second physical block are mapping at random;
(2), set up the page or leaf mapping relations according to writing buffer algorithm;
(3) in write operation process to physical block, full if the pairing buffer stopper of this physical block has been write, then trigger the housekeeping operation process, and finish write operation this physical block, discharge the corresponding relation of said logical block and said buffer stopper simultaneously.
2. Nand according to claim 1 writes the Balance Treatment method, it is characterized in that: the buffer algorithm of writing in the said step (2) adopts the conventional buffer algorithm of writing.
3. Nand according to claim 1 writes the Balance Treatment method; It is characterized in that: the process of setting up the page or leaf mapping relations in the said step (2) is: the data in the sector that will write sequentially write certain page or leaf of buffer stopper, and according to the numbering of sector and the numbering refresh page mapping array of page or leaf.
4. Nand according to claim 1 writes the Balance Treatment method, it is characterized in that: also comprise initialization procedure before in said step (1): allocation block mapping array and the required internal memory of page or leaf mapping array; All physical blocks of scan N and chip upgrade piece mapping array.
5. Nand according to claim 1 writes the Balance Treatment method, it is characterized in that: the housekeeping operation process of said step (3) is: to being in the logical block of writing buffer status, the data of data block and buffer stopper are merged in the new physical block; The page or leaf mapping relations of said logical block are converted into mapping one by one by shining upon at random.
6. Nand according to claim 4 writes the Balance Treatment method, it is characterized in that: said Nand writes the Balance Treatment method and also comprises the read operation process: in the time of need reading certain sector in system, calculate the logical block number (LBN) that need read; According to the mapping of the piece after initialization array, find the pairing physical block of the logical block that will read; If this logical block is being write buffer status, then, find corresponding page or leaf, otherwise directly calculate the corresponding physical page or leaf, and read this Physical Page according to its page or leaf mapping array.
7. Nand according to claim 6 writes the Balance Treatment method, it is characterized in that: the computing method of said logical block number (LBN) are: the number of pages of logical block number (LBN)=sector number/every.
8. Nand according to claim 6 writes the Balance Treatment method, it is characterized in that: the said formula that calculates the corresponding physical page or leaf is: the skew of number of pages+sector number in piece that Physical Page=corresponding physical piece * is every.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103970483A (en) * 2013-01-30 2014-08-06 安凯(广州)微电子技术有限公司 Method and system for writing physical blocks
CN103995783A (en) * 2013-02-20 2014-08-20 安凯(广州)微电子技术有限公司 Method and system for establishing mapping relation between logic block and physical block
CN103970674B (en) * 2013-01-30 2017-04-05 安凯(广州)微电子技术有限公司 A kind of physical block wiring method and system
CN107092563A (en) * 2017-04-20 2017-08-25 紫光华山信息技术有限公司 A kind of rubbish recovering method and device
CN107632941A (en) * 2017-08-16 2018-01-26 南京扬贺扬微电子科技有限公司 A kind of method for improving flash memory write performance

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030163631A1 (en) * 2002-02-27 2003-08-28 Aasheim Jered Donald System and method for tracking data stored in a flash memory device
CN1828555A (en) * 2005-02-07 2006-09-06 三星电子株式会社 Flash memory control devices that support multiple memory mapping schemes and methods of operating same
CN101075211A (en) * 2007-06-08 2007-11-21 马彩艳 Flash memory management based on sector access
CN101241472A (en) * 2008-03-07 2008-08-13 威盛电子股份有限公司 Mapping management process and system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030163631A1 (en) * 2002-02-27 2003-08-28 Aasheim Jered Donald System and method for tracking data stored in a flash memory device
CN1828555A (en) * 2005-02-07 2006-09-06 三星电子株式会社 Flash memory control devices that support multiple memory mapping schemes and methods of operating same
CN101075211A (en) * 2007-06-08 2007-11-21 马彩艳 Flash memory management based on sector access
CN101241472A (en) * 2008-03-07 2008-08-13 威盛电子股份有限公司 Mapping management process and system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103970483A (en) * 2013-01-30 2014-08-06 安凯(广州)微电子技术有限公司 Method and system for writing physical blocks
CN103970674B (en) * 2013-01-30 2017-04-05 安凯(广州)微电子技术有限公司 A kind of physical block wiring method and system
CN103970483B (en) * 2013-01-30 2017-05-31 安凯(广州)微电子技术有限公司 A kind of physical block wiring method and system
CN103995783A (en) * 2013-02-20 2014-08-20 安凯(广州)微电子技术有限公司 Method and system for establishing mapping relation between logic block and physical block
CN107092563A (en) * 2017-04-20 2017-08-25 紫光华山信息技术有限公司 A kind of rubbish recovering method and device
CN107632941A (en) * 2017-08-16 2018-01-26 南京扬贺扬微电子科技有限公司 A kind of method for improving flash memory write performance

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