CN102324176B - Security system - Google Patents
Security system Download PDFInfo
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- CN102324176B CN102324176B CN201110273229.9A CN201110273229A CN102324176B CN 102324176 B CN102324176 B CN 102324176B CN 201110273229 A CN201110273229 A CN 201110273229A CN 102324176 B CN102324176 B CN 102324176B
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- host module
- security system
- state
- resistance value
- perceptron
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Abstract
The invention discloses a security system. The security system comprises a sensor, a terminal resistor and a host module. The sensor has a first state and a second state. The terminal resistor connects with the sensor. The host module connects with the sensor and sets a loop failure time, wherein, when a micro-control module carries out counting according to a frequency generation module, and a counting time is larger than or equals to the loop failure time and the sensor is not switched to the second state, the host module generates a loop failure signal. According to the security system, a problem that the security system can not work normally caused by destroy of a security system circuit is solved, the host module of the security system sets the loop failure time, and when the loop failure time is exceeded and no alarm is emitted, a security company is notified to send people to check the security system.
Description
Dividing an application of the application for a patent for invention that the application's application number that to be applicant submit on April 30th, 2009 is 200910139176.4, is attached to the application by its full content by reference.
Technical field
The present invention is about a kind of security system, especially in regard to a kind of, has a security system that partial failure detects.
Background technology
At present, the circuit in security system, refers to Fig. 1 a and Fig. 1 b.Fig. 1 a is under general normal condition, node switch unit 114 in perceptron 110 remains on the first state, to connect first node 111 and Section Point 112, and when having invader to invade security system, refer to Fig. 1 b, 114 of node switch units in perceptron 110 transfer the second state of open circuit to, and now host module 101 becomes open circuit infinity because detecting terminal resistance 102, and the signal that gives the alarm.But current security system circuit exists some problems, for example effractor can utilize short circuit mode to destroy circuit along dotted line 103, makes host module 101 cannot detect the terminal resistance 102 that the variation because of node switch unit 114 states changes.
In addition, current security system also has a problem to be, no alarms and no surprises signal as long-time in security system, this situation may be not have invader to invade, also likely for perceptron 110 is long neglected and in disrepair, break down, make node switch unit 114 normally by the first state, transfer the second state to, or the circuit of security system suffers artificial destruction, make host module 101 effractor cannot have been detected and invade.But current security system there is no effective solution, and this reports the method for full doubt.
Summary of the invention
In view of this, be necessary to provide a kind of security system, destroyed to solve security system circuit, and the problem that security system cannot be worked, and the host module of security system is also set the partial failure time, make to surpass partial failure during the time all acomia responding give the correct time, can notify and save company from damage and dispatch officers to check security system.
, it comprises a perceptron, a terminal resistance, a host module.Perceptron has the first state and the second state.Terminal resistance connects perceptron.Host module connects perceptron, and sets the partial failure time, wherein, when microcontroller module is counted according to frequency generation module, gate time is more than or equal to the partial failure time, and perceptron is not while all transferring the second state to, and host module produces partial failure signal.
Preferably, described main frame module is further set a preset resistance value, and exports a voltage signal of corresponding described preset resistance value, makes described terminal resistance produce a termination resistance value according to described voltage signal.
Preferably, when described perceptron is described the second state, the reset loop out-of-service time, and when described host module judgement terminal resistance is the state of alert, described host module produces an alarm signal, and described the second state is short-circuit condition.
Preferably, described host module is further set preset resistance value, described gate time is less than the described partial failure time, and a described host module termination resistance value of detecting described terminal resistance is while being not equal to described preset resistance value, and described host module produces an alarm signal.
Preferably, when described host module, detecting described terminal resistance is open-circuit condition or short-circuit condition, when described terminal electricity group is described open-circuit condition, described host module sends loop and destroys signal, when described host module, detecting described terminal resistance is described short-circuit condition, and described host module is reset the described partial failure time.
Compared with prior art, above-mentioned security system has one or more following advantage:
(1) prevent that security system circuit from, by short circuit, giving the alarm and security system cannot be worked.
(2) when surpassing the partial failure time all during no alarms and no surprises, can notifying, save company from damage and dispatch officers to check security system.
(3) capable of dynamic is adjusted terminal resistance, prevents from being obtained termination resistance value by effractor, and carries out security system circuit damage.
Accompanying drawing explanation
Fig. 1 a is the schematic diagram of existing security system when the first state;
Fig. 1 b is the schematic diagram of existing security system when the second state;
Fig. 2 a is node switch unit schematic diagram when the first state of security system the first embodiment of the present invention;
Fig. 2 b is node switch unit schematic diagram when the second state of security system the first embodiment of the present invention;
Fig. 2 c is the embodiment schematic diagram of three perceptron connected modes of the present invention;
Fig. 3 is security system the second embodiment schematic diagram of the present invention;
Fig. 4 is security system inspection method flow chart of steps of the present invention; And
Fig. 5 is security system inspection method process flow diagram of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Refer to Fig. 2 a and Fig. 2 b, it is security system the first embodiment schematic diagram of the present invention.In figure, security system 1 comprises a perceptron 210, a terminal resistance 202 and a host module 201.Perceptron 210 comprises a first node 211, a Section Point 212, one the 3rd node 213, a node switch unit 214.Node switch unit 214 can have the first state and the second state, refers to Fig. 2 a, and when node switch unit 214 is the first state, node switch unit 214 can connect first node 211 and Section Point 212.Refer to Fig. 2 b, when node switch unit 214 is the second state, node switch unit 214 can connect first node 211 and the 3rd node 213.
In general normal condition, the detection signal that host module 201 sends can sequentially be passed through first node 211, Section Point 212, terminal resistance 202 and the 3rd node 213, and in the abnormality of being invaded, the detection signal that host module 201 sends can sequentially be passed through first node 211 and the 3rd node 213.Therefore host module 201 can the voltage drop of detection signal with input according to output, and learns that detection signal has or not through terminal resistance 202, security system can be judged as normal or abnormality accordingly.
In addition, invader may see through destruction circuit and invade, for example at primary importance dotted line 2031 or second place dotted line 2032 places, utilize the mode of short circuit to destroy circuit, these two kinds of failure modes are owing to making detection signal cannot pass through terminal resistance 202, therefore host module 201 can give the alarm as usual.The failure mode of San position dotted line 2033 places short circuit is owing to not affecting the start of node switch unit 214, therefore when security system is invaded, node switch unit 214 can transfer the second state in the same old way, and the signal that gives the alarm.
Security system also can comprise a plurality of perceptrons, refers to Fig. 2 c, and it take 3 perceptrons is example.Each perceptron can be arranged in the possible intrusion route of invader.The first node 2111 of first perceptron 2101 can be connected host module 201 with the 3rd node 2131, the first node 2112 of second perceptron 2102 and the 3rd node 2132 can be connected Section Point 2121 and the 3rd node 2131 of first perceptron 2101, the Section Point 2122 of second perceptron 2102 can be connected the first node 2113 of the 3rd perceptron 2103 and the Section Point 2123 of 2133, the three perceptrons 2103 of the 3rd node and the 3rd node 2133 connectable terminal resistance 202 with the 3rd node 2132.
Security system of the present invention is not limited to one or three perceptrons, can utilize same Anknupfungskeregriff to extend to a plurality of perceptrons.N perceptron for example, N is greater than 1 integer.The first node of first perceptron is connected host module with the 3rd node, the Section Point of N perceptron is connected terminal resistance with the 3rd node, wherein the first node of M perceptron is connected Section Point and the 3rd node of M-1 perceptron with the 3rd node, and the Section Point of M perceptron is connected first node and the 3rd node of M+1 perceptron with the 3rd node, M be between 1 and N between integer.
Refer to Fig. 3, it is security system the second embodiment schematic diagram of the present invention.At the host module 301 of Fig. 3, more comprise a frequency generation module 3013, preset resistance value selection module 3011 and a microcontroller module 3012 with the difference of Fig. 2 a-Fig. 2 c.Host module 301 can be set the partial failure time, and counted according to frequency generation module 3013 by microcontroller module 3012, when gate time is more than or equal to the partial failure time, node switch unit 314 all remains on the first state, do not transfer the second state to, now security system is likely fault or is destroyed, and now host module 301 can produce a partial failure signal, to notify, saves company from damage and dispatches officers to check that security system has no problem.
Preset resistance value selects module 3011 that the preset resistance value of host module 301 dynamic setting one normal conditions can be provided, host module 301 can be according to this preset resistance value afterwards, select the voltage signal 3014 of corresponding preset resistance value, and export this voltage signal 3014 to terminal resistance 302, make terminal resistance 302 produce termination resistance value according to voltage signal 3014.This capable of dynamic is adjusted the method for terminal resistance 302, can prevent invader at primary importance dotted line 3031 places, to connect identical terminal resistance 302 because learning termination resistance value, and destroys the first circuit point 304 and second circuit point 305 is invaded.
When gate time is less than the described partial failure time, and the termination resistance value of host module 301 detecting terminal resistances 302 is not equal to preset resistance value, and host module 301 can produce alarm signal.
When host module 301 detects terminal resistance 302, be an open-circuit condition, host module 301 sends a loop and destroys signal.
And be a short-circuit condition when host module 301 detects terminal resistance 302, node switch unit 314 in expression perceptron 310 may be triggered and transfer the second state to by the first state, show that security system function is normal, host module 301 can the reset loop out-of-service time.
Refer to Fig. 4, it is security system inspection method flow chart of steps of the present invention.In figure, first, step S401 sets a preset resistance value and a partial failure time by a host module.Step S402 is used host module to detect the termination resistance value that a terminal resistance produces.The termination resistance value that step S403 detects when host module equals preset resistance value, and is more than or equal to the partial failure time, and perceptron is not all changed state, and host module produces a partial failure signal.
The termination resistance value wherein detecting at host module is not equal under the prerequisite of preset resistance value, when host module is a state of alert, host module can send an alarm signal, and when host module is a non-state of alert, as host module detects termination resistance value, be now an open-circuit condition, host module sends a loop and destroys signal, and detect termination resistance value as host module, is a short-circuit condition, the host module reset loop out-of-service time.Refer to Fig. 5, it is security system inspection method flow chart of steps of the present invention.In figure, when security system is started working, can first set the preset resistance value 502 of normal range, how long do not move and send the partial failure time 503 of losing efficacy and warning with setting perceptron, the termination resistance value 504 of security system main frame detecting afterwards, take and judge that termination resistance value is as setting value, open circuit, non-setting value or short circuit 505.When main frame judgement termination resistance value equals setting value (being that termination resistance value is preset resistance value), then judge whether to arrive the partial failure time 506.When reaching partial failure during the time, send partial failure warning 507, and save company from damage and dispatch officers to process 511, if not, continue detecting termination resistance value 504.When main frame judgement terminal resistance is open-circuit condition, sends loop and destroy warning 512, and save company from damage and dispatch officers to process 511.When main frame judgement termination resistance value is not setting value or short circuit, reset loop out-of-service time 508, then determine whether the state of alert 509, if be now the state of alert, send safety alarm 510, and save company from damage and dispatch officers to process 511, if not, host module continues detecting termination resistance value 504.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (5)
1. a security system, is characterized in that, it comprises:
One perceptron, it has the first state and the second state;
One terminal resistance, connects described perceptron; And
One host module, connects described perceptron, and sets the partial failure time;
When microcontroller module is counted according to frequency generation module, gate time is more than or equal to the described partial failure time, and described perceptron is not while all transferring described the second state to, and described host module produces partial failure signal.
2. security system as claimed in claim 1, is characterized in that, described main frame module is further set a preset resistance value, and exports a voltage signal of corresponding described preset resistance value, makes described terminal resistance produce a termination resistance value according to described voltage signal.
3. security system as claimed in claim 1, is characterized in that, when described perceptron is described the second state, the reset loop out-of-service time, and when described host module judgement terminal resistance is the state of alert, described host module produces an alarm signal, and described the second state is short-circuit condition.
4. security system as claimed in claim 1, it is characterized in that, described host module is further set preset resistance value, described gate time is less than the described partial failure time, and when the termination resistance value that described host module is detected described terminal resistance is not equal to described preset resistance value, described host module produces an alarm signal.
5. security system as claimed in claim 1, it is characterized in that, when described host module, detecting described terminal resistance is open-circuit condition or short-circuit condition, when described terminal electricity group is described open-circuit condition, described host module sends loop and destroys signal, when described host module, detecting described terminal resistance is described short-circuit condition, and described host module is reset the described partial failure time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110273229.9A CN102324176B (en) | 2009-04-30 | 2009-04-30 | Security system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110273229.9A CN102324176B (en) | 2009-04-30 | 2009-04-30 | Security system |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101391764A Division CN101877162B (en) | 2009-04-30 | 2009-04-30 | Security system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102324176A CN102324176A (en) | 2012-01-18 |
| CN102324176B true CN102324176B (en) | 2014-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110273229.9A Expired - Fee Related CN102324176B (en) | 2009-04-30 | 2009-04-30 | Security system |
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| Country | Link |
|---|---|
| CN (1) | CN102324176B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4351014A (en) * | 1980-07-18 | 1982-09-21 | Xenex Corporation | Solid state self-checking relay |
| US4361833A (en) * | 1980-03-25 | 1982-11-30 | Monitran International, Inc. | Multi-sensor alarm system and method of protecting a premises |
| CN2092125U (en) * | 1991-04-23 | 1992-01-01 | 河南省冶金研究所 | Anti-theft alarming system for electric power installation |
| CN2105779U (en) * | 1991-07-08 | 1992-05-27 | 唐山市路南日月电子电器厂 | Infrared monitor for electricity fraudulent use proof |
| GB2429317A (en) * | 2005-08-16 | 2007-02-21 | Bosch Gmbh Robert | Security system using an AC primary line |
-
2009
- 2009-04-30 CN CN201110273229.9A patent/CN102324176B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4361833A (en) * | 1980-03-25 | 1982-11-30 | Monitran International, Inc. | Multi-sensor alarm system and method of protecting a premises |
| US4351014A (en) * | 1980-07-18 | 1982-09-21 | Xenex Corporation | Solid state self-checking relay |
| CN2092125U (en) * | 1991-04-23 | 1992-01-01 | 河南省冶金研究所 | Anti-theft alarming system for electric power installation |
| CN2105779U (en) * | 1991-07-08 | 1992-05-27 | 唐山市路南日月电子电器厂 | Infrared monitor for electricity fraudulent use proof |
| GB2429317A (en) * | 2005-08-16 | 2007-02-21 | Bosch Gmbh Robert | Security system using an AC primary line |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102324176A (en) | 2012-01-18 |
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| C06 | Publication | ||
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140115 Termination date: 20210430 |