CN102316574B - A kind of multimode terminal system clock timing method and device - Google Patents

A kind of multimode terminal system clock timing method and device Download PDF

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Publication number
CN102316574B
CN102316574B CN201010213597.XA CN201010213597A CN102316574B CN 102316574 B CN102316574 B CN 102316574B CN 201010213597 A CN201010213597 A CN 201010213597A CN 102316574 B CN102316574 B CN 102316574B
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lte
ref
offset
sysclk
counter
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CN102316574A (en
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王茜
杨小勇
唐平
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Spreadtrum Communications Shanghai Co Ltd
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Chongqing Cyit Communication Technologies Co Ltd
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Abstract

The present invention relates to moving communicating field, a kind of multimode terminal system clock timing method and device are provided especially, first described method determines TD system, LTE system timing accuracy, the timing offset of the enumerator determined under system reference timer clock and reference count length, design reference timer clock, then the acquisition each system of multimode system, finally carries out TD system, LTE system synchronization control；Described device includes reference clock enumerator, timing offset acquiring unit and synchronization control unit；The present invention two systems in multimode terminal utilize same reference clock and an enumerator, rather than each system is used separate counters counting, reduce an enumerator, save hardware spending, and the timing relationship between TD and LTE system can carry out calculating without using extra hardware circuit in real time, saves system resource overhead.

Description

A kind of multimode terminal system clock timing method and device
Technical field
The present invention relates to moving communicating field, particularly relate to TD SDMA TD-SCDMA (being called for short TD)/time-division Long Term Evolution TDD-LTE (being called for short LTE) multimode terminal system clock timing method and device.
Background technology
Current 3-G (Generation Three mobile communication system) reaches its maturity, and has had a number of user, and after development, the mobile communication technology such as three generations, forth generation has become development trend.Standing in the angle of user, in order to ensure mobile communication subscriber to the most excessive requirement of system, many modellings of terminal and miniaturization have become objective demand；And the most not there is the Miniature Terminal of TD/LTE multi-mode function,
In TD system, one a length of 10ms of radio frames, one sub-frame length is 5ms, the most each radio frames is made up of 2 subframes, each subframe is made up of 7 main time slots and 3 special time slots of a length of 675us, totally 6400 chips (being called for short chip), the time of day of TD system is chip (1chip=0.78125us i.e. needs the multiple clock of 1.28MHZ to be timed as system clock).
In LTE system; one a length of 10ms of radio frames; one field is 5ms; one subframe lengths is 1ms; the most each radio frames is made up of 2 fields; each field is made up of 8 regular time slots and three special time slots (descending pilot frequency time slot DwPTS, protection interval GP, uplink pilot time slot UpPTS), and each subframe comprises 30720 Ts, is made up of 2 time slots.The time of day of LTE system is Ts (1Ts=1/30720s i.e. needs the multiple clock of 30.72MHZ to be timed as system clock).The time relationship of the subframe lengths of TD and LTE is 5: 1.
The matter of utmost importance of the terminal that development has TD/LTE multi-mode function is how to solve the timing between TD and LTE and stationary problem, and in TD/GSM (or EDGE) multimode system of prior art, use 2 independent enumerators, select different system clocks that different patterns (TD pattern or GSM mode) is carried out independent timing, cause occupying more hardware resource, and the synchronized relation between multimode system is complicated.
Summary of the invention
Present invention solves the problem in that and a kind of multimode terminal system clock timing method solving the independent timing of each mould and device are provided.
For solving problem above, the present invention proposes a kind of multimode terminal system clock timing method, including:
Step A: determine TD system, LTE system timing accuracy；
Step B: determine system reference timer clock sysclk and reference count length ref_framl；
Choose the common multiple clock reference timer clock sysclk as system of the timer clock TD_SYSCLK of TD system and the timer clock LTE_SYSCLK of LTE system；
It is chosen at the counting step of 5ms multiple time under system reference timer clock, as reference count length ref_framl；
Step C: designing one and count under with reference to timer clock sysclk, counting step is the enumerator ref_counter of ref_framl, with ref_framl for the counting cycle, overflows when arriving ref_framl, restarts counting
Step D: obtain the timing offset of each system of multimode system；
Step E: carry out TD system, LTE system synchronization control；
The described system synchronization that carries out is adjusted to adjustment TD system, the timing offset of LTE system respectively: i.e. detected by terminal, obtains frame header position and the relation with reference to timer clock frame header position of network side, adjusts the most forward or adjust backward,
Described adjustment backward refers to when the frame header position that terminal detects is in advance when with reference to timer clock frame header position, and frame interrupt signal postpones to produce；
Described adjustment forward refers to that when the frame header position detected when terminal lags behind with reference to timer clock frame header position, frame interrupt signal produces in advance；
Described backward adjust or adjust forward for TD system, refer to when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint, wherein, td_offset ' represent produce interrupt moment；
When adjusting backward, td_offset '=td_offset '+td_offset × sysclk/TD_SYSCLK
When adjusting forward, td_offset '=td_offset '-td_offset × sysclk/TD_SYSCLK
Described backward adjust or adjust forward for LTE system, refer to when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint, wherein, lte_offset ' represent produce interrupt moment；
When adjusting backward, lte_offset '=lte_offset '+lte_offset × sysclk/TD_SYSCLK
When adjusting forward, lte_offset '=lte_offset '-lte_offset × sysclk/TD_SYSCLK
Preferably, the described system synchronization that carries out is adjusted to adjustment TD system, the timing offset of LTE system simultaneously, i.e. under the duty of TD pattern or LTE pattern, detected by terminal, obtain the frame header position of network side and with reference to reference length deviant ref_offset between timer clock frame header position, then carry out TD timing and the synchronization control of LTE system timing；
Described synchronization control for ref_counter count down to reference clock frame interrupt signal produce the moment in moment ref_framl ' overflows, for TD system, described when ref_counter count down to td_offset ', generation TD frame interrupt signal td_fint；For LTE system, described when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint
When adjusting backward, ref_framl '=ref_framl '+ref_offset
When adjusting forward, ref_framl '=ref_framl '-ref_offset
Further, also include
Step F: determine the timing relationship between TD system and LTE system,
Timing relationship between the described TD of determination system and LTE system is, TD system, LTE system respectively with respective Network Synchronization in the case of, by the inquiry value of td_offset ' and the value of lte_offset ', it is thus achieved that frame head deviation Fr between TD and LTE system
Frame head deviation Fr=td_offset between system '-lte_offset '
Preferably, the timing relationship between the described TD of determination system and LTE system is, calculates frame head deviation Fr between TD and LTE system by reference clock enumerator, specially includes:
Step 1): design two enumerator td_ref_counter and lte_ref_counter, enumerator td_ref_counter with td_offset ' as overflow value, when arriving td_offset ', restart counting；Enumerator lte_ref_counter as overflow value, when arriving this value, restarts counting with lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), and wherein, z is an integer in 0,1,2,3,4；
Step 2): calculate minimum timing precision count value td_min in the frame in TD system a certain moment, calculate minimum timing precision count value lte_min in the frame in LTE system a certain moment
In the frame in described calculating TD system a certain moment, minimum timing precision count value td_min is:
Td_min=[td_ref_counter/ (sysclk/TD_SYSCLK)]
Wherein, td_ref_counter is a certain moment count value of counting under sysclk clock, and [] expression rounds downwards
Td_ref_counter is when counting down to TD frame interrupt signal moment td_offset ', and td_ref_counter starts again to count from sysclk/TD_SYSCLK；
In the frame in described calculating LTE system a certain moment, minimum timing precision count value lte_min is
Lte_min=[lte_ref_counter/ (sysclk/LTE_SYSCLK)]
Wherein, lte_ref_counter is the count value in enumerator a certain moment；[] expression rounds downwards
Lte_ref_counter, when counting down to lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), starts again to count from sysclk/LTE_SYSCLK, and wherein, z is an integer in 0,1,2,3,4；
Step 3) frame head deviation Fr between calculating system
Fr=td_min × (sysclk/TD_SYSCLK)-lte_min × (sysclk/LTE_SYSCLK).
For solving problem above, the present invention also proposes a kind of multimode terminal system clock timing means, as shown in Figure 2 and Figure 3, and including:
Reference clock enumerator, sets with reference to timer clock syscl, counts under with reference to timer clock sysclk, and counting step is the enumerator ref_counter of ref_framl, with ref_framl for the counting cycle, overflows, restart counting when arriving ref_framl；
Timing offset acquiring unit: complete to synchronize acquisition process by initial cell search, the difference receiving signal frame head and intervalometer TD interrupt signal generation moment obtaining TD pattern is timing offset td_offset；And complete to synchronize acquisition process by initial cell search, the difference receiving signal frame head and intervalometer LTE interrupt signal generation moment obtaining LTE pattern is timing offset lte_offset；Timing offset is passed to synchronization control unit；
Synchronization control unit: receive the timing offset ref_offset that timing offset acquiring unit sends, calculates frame interrupt signal and produces the moment, and ref_counter arrives when frame interrupt signal produces the moment and produces interrupt signal, comprising:
TD synchronization control unit: calculate TD frame interrupt signal by timing offset ref_offset and produce moment td_offset ', when ref_counter arrives td_offset ', produces TD frame interrupt signal, makes frame interrupt signal that ref_offset is retarded or advanced and produces；
LTE synchronization control unit: calculate LTE frame interrupt signal by timing offset ref_offset and produce moment lte_offset ', when ref_counter arrives lte_offset ', produce LTE frame interrupt signal, make frame interrupt signal that ref_offset is retarded or advanced and produce；
Preferably, described synchronization control unit includes reference clock adjustment unit, count down to system-frame interrupt signal at ref_counter and produces moment ref_framl ' spilling, for TD system, when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint；For LTE system, when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint
When adjusting backward, ref_framl '=ref_framl '+ref_offset
When adjusting forward, ref_framl '=ref_framl '-ref_offset.
Further, including timing relationship acquiring unit between TD and LTE system: TD system, LTE system respectively with respective Network Synchronization in the case of, by value and the value of lte_offset ' of inquiry td_offset ', obtain frame head deviation Fr between TD and LTE system, in order to carry out the mission planning between multimode system；
Frame head deviation Fr=td_offset between system '-lte_offset '；
Preferably, described timing relationship acquiring unit between TD and LTE system, calculate frame head deviation Fr between TD and LTE system by reference clock enumerator, specifically include:
Step 1): design two enumerator td_ref_counter and lte_ref_counter, enumerator td_ref_counter with td_offset ' as overflow value, when arriving td_offset ', restart counting；Enumerator lte_ref_counter as overflow value, when arriving this value, restarts counting with lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), and wherein, z is an integer in 0,1,2,3,4；
Step 2): calculate minimum timing precision count value td_min in the frame in TD system a certain moment, calculate minimum timing precision count value lte_min in the frame in LTE system a certain moment
In the frame in described calculating TD system a certain moment, minimum timing precision count value td_min is:
Td_min=[td_ref_counter/ (sysclk/TD_SYSCLK)]
Wherein, td_ref_counter is a certain moment count value of counting under sysclk clock, and [] expression rounds downwards
Td_ref_counter is when counting down to TD frame interrupt signal moment td_offset ', and td_ref_counter starts again to count from sysclk/TD_SYSCLK；
In the frame in described calculating LTE system a certain moment, minimum timing precision count value lte_min is
Lte_min=[lte_ref_counter/ (sysclk/LTE_SYSCLK)]
Wherein, lte_ref_counter is the count value in enumerator a certain moment；[] expression rounds downwards
Lte_ref_counter, when counting down to lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), starts again to count from sysclk/LTE_SYSCLK, and wherein, z is an integer in 0,1,2,3,4；
Step 3) frame head deviation Fr between calculating system
Fr=td_min × (sysclk/TD_SYSCLK)-lte_min × (sysclk/LTE_SYSCLK).
The present invention utilizes TD and the particular kind of relationship of LTE system frame structure, provide the same clock of a kind of employing and carry out clock-timed method and device, compared with prior art, the present invention two systems in multimode terminal utilize same reference clock and an enumerator, rather than each system is used separate counters counting, reduce an enumerator, save hardware spending, and the timing relationship between TD and LTE system can carry out calculating without using extra hardware circuit in real time, saves system resource overhead further.
Accompanying drawing explanation
Fig. 1 is multimode terminal system clock timing method preferred embodiment flow chart of the present invention
Fig. 2 is multimode terminal system clock timing means preferred embodiment structure chart of the present invention
Fig. 3 is another preferred embodiment structure chart of multimode terminal system clock timing means of the present invention
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, one multimode terminal system clock timing method of the present invention and device are described in further details, known in some, implementation no longer describes in detail, to avoid there is unnecessary obscuring with present disclosure.
A kind of multimode terminal system clock timing method of the present invention, as it is shown in figure 1, include:
Step A: determine TD system, LTE system timing accuracy
The time of day of TD system is chip (1chip=0.78125us i.e. needs the multiple clock of 1.28MHZ to be timed as system clock), when system designs, can choose higher timing accuracy, it may be assumed that 1/nchip, and wherein n is 2x, wherein x=0,1,2 ...；The preferred x=5 of the present embodiment illustrates, and i.e. selecting timing accuracy is 1/32chip；
The time of day of LTE system is Ts (1Ts=1/30720s i.e. needs the multiple clock of 30.72MHZ to be timed as system clock), when system designs, can choose higher timing accuracy, it may be assumed that 1/mTs, and wherein m is 2y, wherein y=0,1,2 ...；The preferred y=0 of the present embodiment illustrates, and i.e. selecting timing accuracy is Ts；
Step B: determine System Clock Reference sysclk and reference count length ref_framl
B1: determine System Clock Reference sysclk
The timing accuracy selecting TD system in step is that (wherein n is 2 to 1/nchipx, wherein x=0,1,2 ...), then need the multiple timer clock TD_SYSCLK as TD system of 1.28MHz clock.Such as: when being timing accuracy selecting 1/32chip, preferably 40.96MHz is as timer clock.
The timing accuracy selecting LTE system in step is that (wherein m is 2 to 1/mTsy, wherein y=0,1,2 ...), then need the multiple timer clock LTE_SYSCLK as LTE system of 30.72MHz clock.Such as: when being Ts selecting timing accuracy, preferably 30.72MHz is as timer clock；
For meeting the timing accuracy requirement of TD system and LTE system simultaneously, choose the common multiple clock reference timer clock sysclk as system of the timer clock TD_SYSCLK of TD system and the timer clock LTE_SYSCLK of LTE system.Such as: elect 40.96MHz as at TD_SYSYCLK, when LTE_SYSCLK elects 30.72MHz as, preferably reference timer clock sysclk is 122.88MHz.
B2: selecting system is with reference to reference count length ref_framl under timer clock
Owing to a subframe lengths of TD system is 5ms, a subframe lengths of LTE system is 1ms, for meeting the timing requirements of 2 systems simultaneously, is chosen at the counting step of 5ms multiple time under system reference timer clock, as reference count length ref_framl.Such as: under with reference to timer clock 122.88MHz clock, preferably with reference to timer counter length ref_framl5ms, its hexadecimal is 0x96000.
Step C: design reference clock counter
Designing one to count under with reference to timer clock sysclk, counting step is the enumerator ref_counter of ref_framl, with ref_framl for the counting cycle, overflows, restart counting when arriving ref_framl.Such as: when a length of 0x96000 of reference count selected above, ref_counter overflows after counting down to 0x96000, counting 5ms is represented.
Step D: obtain the timing offset of each system of multimode system
Completing to synchronize acquisition process by initial cell search, the difference receiving signal frame head and system reference timer clock TD interrupt signal generation moment obtaining TD pattern is timing offset td_offset.Initial cell search under TD mode of operation is known in the art general knowledge, is not described in detail in this.
Completing to synchronize acquisition process by initial cell search, the difference receiving signal frame head and system reference timer clock LTE interrupt signal generation moment obtaining LTE pattern is timing offset lte_offset.Initial cell search under LTE mode of operation is known in the art general knowledge, is not described in detail in this.
Step E: carry out system synchronization adjustment
The described system synchronization that carries out is adjusted to step E1: adjust TD system, the timing offset of LTE system respectively, detected by terminal, obtain the frame header position (position that every frame starts of network side, the position that i.e. frame interrupts) and the relation of system reference timer clock frame header position, it is divided into and adjusts forward and adjust backward, when the frame header position that terminal detects is in advance when with reference to timer clock frame header position, need to do the frame header position of terminal to adjust backward；When the frame header position that terminal detects lags behind with reference to timer clock frame header position, need to do the frame header position of terminal to adjust forward, to reach and to align with reference to timer clock frame header position,
Subsystem is described as follows below:
The adjustment of step E11:TD timing
E111: adjust backward
The frame interrupt signal i.e. arranging TD postpones to produce, timer clock TD_SYSCLK according to TD system and the relation with reference to timer clock sysclk, calculate td_offset '=td_offset '+td_offset × sysclk/TD_SYSCLK, when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint.Td_offset ' represents the moment producing interruption, i.e. count down to during this moment produce interrupt, and its initial value is 0.
Such as: choose sysclk be 122.88MHz, TD_SYSCLK be 40.96MHz time, calculate td_offset '=td_offset '+3 × td_offset.When ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint；
E112: adjust forward
The frame interrupt signal i.e. arranging TD produces in advance, timer clock TD_SYSCLK according to TD system and the relation with reference to timer clock sysclk, calculate td_offset '=td_offset '-td_offset × sysclk/TD_SYSCLK, when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint；
Such as: choose sysclk be 122.88MHz, TD_SYSCLK be 40.96MHz time, calculate td_offset '=td_offset '-3 × td_offset, when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint；
The adjustment of E12:LTE timing
E121: adjust backward
The frame interrupt signal i.e. arranging LTE postpones to produce, timer clock LTE_SYSCLK according to LTE system and the relation with reference to timer clock sysclk, calculate lte_offset '=lte_offset '+lte_offset × sysclk/LTE_SYSCLK, when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint；Lte_offset ' represents the moment producing interruption, i.e. count down to during this moment produce interrupt, and its initial value is 0.
Such as: choose sysclk be 122.88MHz, LTE_SYSCLK be 30.72MHz time, calculate lte_offset '=lte_offset '+4 × lte_offset, when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint；
E122: adjust forward
The frame i.e. arranging LTE interrupts producing in advance, timer clock LTE_SYSCLK according to LTE system and the relation with reference to timer clock sysclk, calculate lte_offset '=lte_offset '-lte_offset × sysclk/LTE_SYSCLK, when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint；
Such as: choose sysclk be 122.88MHz, LTE_SYSCLK be 30.72MHz time, calculate lte_offset '=lte_offset '-4 × lte_offset, when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint；
Preferably, system synchronization is adjusted to step E2: adjust TD system, the timing offset of LTE system simultaneously, under TD mode of operation or under LTE mode of operation or under other mode of operations, detected by terminal, obtain the frame header position of network side and with reference to reference length deviant ref_offset between timer clock frame header position, then carry out TD timing and the synchronization control of LTE system timing, complete the synchronization timing of TD system and LTE system.
E21: adjust backward
Ref_framl '=ref_framl '+ref_offset is i.e. set, the overflow value making ref_counter is delayed ref_offset system clock and is arrived, that is: the frame interrupt signal of TD and the frame interrupt signal of LTE are all delayed ref_offset system clock and are produced, to realize synchronization control, wherein, ref_framl ' represents the moment producing interruption, i.e. count down to during this moment produce frame interrupt signal, and its initial value is 0；
E22: adjust forward
Adjust forward, ref_framl '=ref_framl '-ref_offset is i.e. set, the overflow value of ref_counter shifts to an earlier date ref_offset system clock and arrives, that is: the frame interrupt signal of TD or the frame interrupt signal of LTE ref_offset system clock all in advance produces, to realize synchronization control.
Through above procedure so that the TD system generation frame interrupt signal moment aligns with the frame head of TD network side, the LTE system generation frame interrupt signal moment aligns with the frame head of LTE network side, further, in order to understand the timing relationship between TD system and LTE system, including:
Step F: determine the timing relationship between TD and LTE system
A kind of preferred implementation is, TD system, LTE system respectively with respective Network Synchronization in the case of, by value and the value of lte_offset ' of inquiry td_offset ', it is thus achieved that frame head deviation Fr between TD and LTE system, in order to carry out the mission planning between multimode system.
Frame head deviation Fr=td_offset between system '-lte_offset '
Another preferred implementation is: calculate frame head deviation Fr between TD and LTE system by reference clock enumerator
Step 1): design two enumerator td_ref_counter and lte_ref_counter, enumerator td_ref_counter with td_offset ' as overflow value, when arriving td_offset ', restart counting；Enumerator lte_ref_counter is with lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), and (z is an integer in 0,1,2,3,4) is overflow value, when arriving this value, restarts counting
Step 2): minimum timing precision count value lte_min in the frame in minimum timing precision count value td_min calculating LTE system a certain moment in the frame in calculating TD system a certain moment
In the frame in described calculating TD system a certain moment, minimum timing precision count value td_min is:
Td_min=[td_ref_counter/ (sysclk/TD_SYSCLK)]
Wherein, td_ref_counter is a certain moment count value of counting under sysclk clock, and [] expression rounds downwards
Td_ref_counter is when counting down to TD frame interrupt signal moment td_offset ', and td_ref_counter starts again to count from sysclk/TD_SYSCLK.
Such as: sysclk elect as 122.88MHz, TD timing accuracy elect 1/32chip as time, in the td_min frame frame of TD, minimum timing precision is td_ref_counter/3, has no progeny producing in TD frame every time, and td_ref_counter starts again to count from 3.
In the frame in described calculating LTE system a certain moment, minimum timing precision count value lte_min is
Lte_min=[lte_ref_counter/ (sysclk/LTE_SYSCLK)]
Wherein, lte_ref_counter is the count value in enumerator a certain moment；[] expression rounds downwards
Lte_ref_counter is (z is an integer in 0,1,2,3,4) when counting down to lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), starts again to count from sysclk/LTE_SYSCLK.
Such as: sysclk elect as 122.88MHz, LTE timing accuracy elect Ts as time, the lte_framc frame count value of LTE is lte_ref_counter/4, has no progeny producing in LTE frame every time, and lte_ref_counter starts again to count from 4.
Step 3) frame head deviation Fr between calculating system
Fr=td_min × (sysclk/TD_SYSCLK)-lte_min × (sysclk/LTE_SYSCLK)
A kind of multimode terminal system clock timing means of the present invention, as shown in Figure 2 or Figure 3, including:
Reference clock enumerator, sets with reference to timer clock syscl, counts under with reference to timer clock sysclk, and counting step is the enumerator ref_counter of ref_framl, with ref_framl for the counting cycle, overflows, restart counting when arriving ref_framl；
Timing offset acquiring unit: complete to synchronize acquisition process by initial cell search, the difference receiving signal frame head and intervalometer TD interrupt signal generation moment obtaining TD pattern is timing offset td_offset；And complete to synchronize acquisition process by initial cell search, the difference receiving signal frame head and intervalometer LTE interrupt signal generation moment obtaining LTE pattern is timing offset lte_offset；Timing offset is passed to synchronization control unit；
Synchronization control unit: receive the timing offset ref_offset that timing offset acquiring unit sends, calculates frame interrupt signal and produces the moment, and ref_counter arrives when frame interrupt signal produces the moment and produces interrupt signal, comprising:
TD synchronization control unit: calculate TD frame interrupt signal by timing offset ref_offset and produce moment td_offset ', when ref_counter arrives td_offset ', produces TD frame interrupt signal, makes frame interrupt signal that ref_offset is retarded or advanced and produces；
LTE synchronization control unit: calculate LTE frame interrupt signal by timing offset ref_offset and produce moment lte_offset ', when ref_counter arrives lte_offset ', produce LTE frame interrupt signal, make frame interrupt signal that ref_offset is retarded or advanced and produce；
Or, including reference clock adjustment unit, it count down to system-frame interrupt signal at ref_counter and produces moment ref_framl ' spilling, for TD system, when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint；For LTE system, when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint
When adjusting backward, ref_framl '=ref_framl '+ref_offset
When adjusting forward, ref_framl '=ref_framl '-ref_offset；
Further, including the timing relationship acquiring unit between TD and LTE system；
Timing relationship acquiring unit between described TD and LTE system, TD system, LTE system respectively with respective Network Synchronization in the case of, by value and the value of lte_offset ' of inquiry td_offset ', it is thus achieved that frame head deviation Fr between TD and LTE system, in order to carry out the mission planning between multimode system.
Frame head deviation Fr=td_offset '-5 × lte_offset ' between system
Preferably, the timing relationship acquiring unit between described TD and LTE system, calculate frame head deviation Fr between TD and LTE system by reference clock enumerator, specifically include:
Step 1): design two enumerator td_ref_counter and lte_ref_counter, enumerator td_ref_counter with td_offset ' as overflow value, when arriving td_offset ', restart counting；Enumerator lte_ref_counter is with lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), and (z is an integer in 0,1,2,3,4) is overflow value, when arriving this value, restarts counting
Step 2): calculate minimum timing precision count value td_min in the frame in TD system a certain moment, calculate minimum timing precision count value lte_min in the frame in LTE system a certain moment
In the frame in described calculating TD system a certain moment, minimum timing precision count value td_min is:
Td_min=[td_ref_counter/ (sysclk/TD_SYSCLK)]
Wherein, td_ref_counter is a certain moment count value of counting under sysclk clock, and [] expression rounds downwards
Td_ref_counter is when counting down to TD frame interrupt signal moment td_offset ', and td_ref_counter starts again to count from sysclk/TD_SYSCLK.
Such as: sysclk elect as 122.88MHz, TD timing accuracy elect 1/32chip as time, in the td_min frame frame of TD, minimum timing precision is td_ref_counter/3, has no progeny producing in TD frame every time, and td_ref_counter starts again to count from 3.
In the frame in described calculating LTE system a certain moment, minimum timing precision count value lte_min is
Lte_min=[lte_ref_counter/ (sysclk/LTE_SYSCLK)]
Wherein, lte_ref_counter is the count value in enumerator a certain moment；[] expression rounds downwards
Lte_ref_counter is (z is an integer in 0,1,2,3,4) when counting down to lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), starts again to count from sysclk/LTE_SYSCLK.
Such as: sysclk elect as 122.88MHz, LTE timing accuracy elect Ts as time, the lte_framc frame count value of LTE is lte_ref_counter/4, has no progeny producing in LTE frame every time, and lte_ref_counter starts again to count from 4.
Step 3) frame head deviation Fr between calculating system
Fr=td_min × (sysclk/TD_SYSCLK)-lte_min × (sysclk/LTE_SYSCLK).
The purpose of the present invention, technical scheme and beneficial effect have been described in detail by the lifted embodiment of the present invention or embodiment; should be understood that; embodiment provided above or embodiment are only the preferred embodiment of the present invention; not in order to limit the present invention; all any modification, equivalent substitution and improvement the most made for the present invention etc., should be included within the scope of the present invention.

Claims (6)

1. a multimode terminal system clock timing method, it is characterised in that including:
Step A: determine TD system, LTE system timing accuracy；
Step B: determine system reference timer clock sysclk and reference count length ref_framl；
Step C: designing one and count under with reference to timer clock sysclk, counting step is the enumerator ref_counter of ref_framl, with ref_framl for the counting cycle, overflows when arriving ref_framl, restarts counting；
Step D: obtain the timing offset of each system of multimode system；
Step E: carry out TD system, LTE system synchronization control；
The described TD of carrying out system, LTE system synchronization control are to adjust TD system, the timing offset of LTE system respectively, are i.e. detected by terminal, obtain frame header position and the relation with reference to timer clock frame header position of network side, adjust the most forward or adjust backward；
Described adjustment backward refers to when the frame header position that terminal detects is in advance when with reference to timer clock frame header position, and frame interrupt signal postpones to produce；
Described adjustment forward refers to that when the frame header position detected when terminal lags behind with reference to timer clock frame header position, frame interrupt signal produces in advance；
Step F: determine the timing relationship between TD system and LTE system: calculate frame head deviation Fr between TD and LTE system by reference clock enumerator, specifically include:
Step 1): design two enumerator td_ref_counter and lte_ref_counter, enumerator td_ref_counter with td_offset ' as overflow value, when arriving td_offset ', restart counting；Enumerator lte_ref_counter as overflow value, when arriving this value, restarts counting with lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), and wherein, z is an integer in 0,1,2,3,4；
Step 2): calculate minimum timing precision count value td_min in the frame in TD system a certain moment, calculate minimum timing precision count value lte_min in the frame in LTE system a certain moment；
In the frame in described calculating TD system a certain moment, minimum timing precision count value td_min is:
Td_min=[td_ref_counter/ (sysclk/TD_SYSCLK)]
Wherein, td_ref_counter is a certain moment count value of counting under sysclk clock, and [] expression rounds downwards；
Td_ref_counter is when counting down to TD frame interrupt signal moment td_offset ', and td_ref_counter starts again to count from sysclk/TD_SYSCLK；
In the frame in described calculating LTE system a certain moment, minimum timing precision count value lte_min is:
Lte_min=[lte_ref_counter/ (sysclk/LTE_SYSCLK)]
Wherein, lte_ref_counter is the count value in enumerator a certain moment；[] expression rounds downwards；
Lte_ref_counter, when counting down to lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), starts again to count from sysclk/LTE_SYSCLK, and wherein, z is an integer in 0,1,2,3,4；
Step 3) frame head deviation Fr between calculating system
Fr=td_min × (sysclk/TD_SYSCLK)-lte_min × (sysclk/LTE_SYSCLK)；
Above-mentioned TD_SYSCLK represents that the timer clock of TD system, above-mentioned LTE_SYSCLK represent the timer clock of LTE system.
2. multimode terminal system clock timing method as claimed in claim 1, it is characterised in that determine described in step B that system reference timer clock sysclk and reference count length ref_framl are:
Choose the common multiple clock reference timer clock sysclk as system of the timer clock TD_SYSCLK of TD system and the timer clock LTE_SYSCLK of LTE system；
It is chosen at the counting step of 5ms multiple time under system reference timer clock, as reference count length ref_framl.
3. multimode terminal system clock timing method as claimed in claim 1, it is characterised in that adjust backward described in step E or adjust forward:
For TD system, referring to when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint, wherein, td_offset ' represents the moment producing interruption；
When adjusting backward, td_offset '=td_offset '+td_offset × sysclk/TD_SYSCLK
When adjusting forward, td_offset '=td_offset ' td_offset × sysclk/TD_SYSCLK；
For LTE system, referring to when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint, wherein, lte_offset ' represents the moment producing interruption；
When adjusting backward, lte_offset '=lte_offset '+lte_offset × sysclk/TD_SYSCLK
When adjusting forward, lte_offset '=lte_offset ' lte_offset × sysclk/TD_SYSCLK.
4. multimode terminal system clock timing method as claimed in claim 1, it is characterized in that, carry out TD system described in step E, LTE system synchronization control is to adjust TD system, the timing offset of LTE system simultaneously, i.e. under the duty of TD pattern or LTE pattern, detected by terminal, obtain the frame header position of network side and with reference to reference length deviant ref_offset between timer clock frame header position, then carry out TD timing and the synchronization control of LTE system timing；Described synchronization control produces moment ref_framl ' spilling for counting down to reference clock frame interrupt signal at ref_counter；For TD system, described when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint；For LTE system, described when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint；
When adjusting backward, ref_framl '=ref_framl '+ref_offset
When adjusting forward, ref_framl '=ref_framl '-ref_offset.
5. a multimode terminal system clock timing means, it is characterised in that including:
Reference clock enumerator, sets with reference to timer clock sysclk, counts under with reference to timer clock sysclk, and counting step is the enumerator ref_counter of ref_framl, with ref_framl for the counting cycle, overflows, restart counting when arriving ref_framl；
Timing offset acquiring unit: complete to synchronize acquisition process by initial cell search, the difference receiving signal frame head and intervalometer TD interrupt signal generation moment obtaining TD pattern is timing offset td_offset；And complete to synchronize acquisition process by initial cell search, the difference receiving signal frame head and intervalometer LTE interrupt signal generation moment obtaining LTE pattern is timing offset lte_offset；Timing offset is passed to synchronization control unit；
Synchronization control unit: receive the timing offset ref_offset that timing offset acquiring unit sends, calculates frame interrupt signal and produces the moment, and ref_counter arrives when frame interrupt signal produces the moment and produces interrupt signal, comprising:
TD synchronization control unit: calculate TD frame interrupt signal by timing offset ref_offset and produce moment td_offset ', when ref_counter arrives td_offset ', produces TD frame interrupt signal, makes frame interrupt signal that ref_offset is retarded or advanced and produces；
LTE synchronization control unit: calculate LTE frame interrupt signal by timing offset ref_offset and produce moment lte_offset ', when ref_counter arrives lte_offset ', produce LTE frame interrupt signal, make frame interrupt signal that ref_offset is retarded or advanced and produce；
Timing relationship acquiring unit between TD and LTE system: calculate frame head deviation Fr between TD and LTE system by reference clock enumerator, specifically include:
Step 1): design two enumerator td_ref_counter and lte_ref_counter, enumerator td_ref_counter with td_offset ' as overflow value, when arriving td_offset ', restart counting；Enumerator lte_ref_counter as overflow value, when arriving this value, restarts counting with lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), and wherein, z is an integer in 0,1,2,3,4；
Step 2): calculate minimum timing precision count value td_min in the frame in TD system a certain moment, calculate minimum timing precision count value lte_min in the frame in LTE system a certain moment；
In the frame in described calculating TD system a certain moment, minimum timing precision count value td_min is:
Td_min=[td_ref_counter/ (sysclk/TD_SYSCLK)]
Wherein, td_ref_counter is a certain moment count value of counting under sysclk clock, and [] expression rounds downwards；
Td_ref_counter is when counting down to TD frame interrupt signal moment td_offset ', and td_ref_counter starts again to count from sysclk/TD_SYSCLK；
In the frame in described calculating LTE system a certain moment, minimum timing precision count value lte_min is:
Lte_min=[lte_ref_counter/ (sysclk/LTE_SYSCLK)]
Wherein, lte_ref_counter is the count value in enumerator a certain moment；[] expression rounds downwards；
Lte_ref_counter, when counting down to lte_offset '+z × ref_framl/ (5 × sysclk/LTE_SYSCLK), starts again to count from sysclk/LTE_SYSCLK, and wherein, z is an integer in 0,1,2,3,4；
Step 3) frame head deviation Fr between calculating system
Fr=td_min × (sysclk/TD_SYSCLK)-lte_min × (sysclk/LTE_SYSCLK).
6. plant multimode terminal system clock timing means as claimed in claim 5, it is characterized in that, described synchronization control unit includes reference clock adjustment unit, it count down to reference clock frame interrupt signal at ref_counter and produce moment ref_framl ' spilling, for TD system, when ref_counter count down to td_offset ', produce TD frame interrupt signal td_fint；For LTE system, when ref_counter count down to lte_offset ', produce LTE frame interrupt signal lte_fint
When adjusting backward, ref_framl '=ref_framl '+ref_offset
When adjusting forward, ref_framl '=ref_framl '-ref_offset.
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