CN102299710A

CN102299710A - Phase-locked loop having improved phase detection mechanism

Info

Publication number: CN102299710A
Application number: CN2010102175835A
Authority: CN
Inventors: 林鹏飞; 林铭琦; 余浡豪
Original assignee: QIYAN ELECTRONIC CO Ltd
Current assignee: Prolific Technology Inc
Priority date: 2010-06-23
Filing date: 2010-06-23
Publication date: 2011-12-28
Anticipated expiration: 2030-06-23
Also published as: CN102299710B

Abstract

The invention discloses a phase-locked loop (PLL) having an improved phase detection mechanism. The PLL comprises a phase frequency detector (PFD), a controller, a D2A module, and a VCO/ICO. The PFD has a reference signal input and an input of a VCO/ICO output signal as well as is connected with the controller; and then the controller is further connected with the D2A module that converts a control signal from the controller into an analog voltage to control a VCO/ICO frequency and a VCO/ICO phase position. It should be noticed that the PFD utilized in the invention has a novel phase detection mechanism, so that edge alignment is not required during the phase detection. Furthermore, the improved phase detection mechanism also provides an elastic reference signal input that is used as, for example, a fixed external source for a crystal.

Description

Has the phase-locked loop that improves phase-detection mechanism

Technical field

The present invention relates to a kind of phase-locked loop, relate in particular to phase-locked loop with improvement phase-detection mechanism.

Background technology

(phase-locked loop PLL) is a kind of frequency control system to phase-locked loop, generally is the circuit design that is used for wide scope, comprises clock generating, clock recovery, exhibition frequency, removes deflection, clock distribution, shake and noise reduction, frequency synthesis or the like.The operation of PLL is based on the phase difference between the feedback of input signal and voltage-controlled oscillator (VCO).PLL is widely used in the clock generator of being used as in the electronic installation, and supports the high-speed transfer agreement, such as USB 2.0, is used as the critical elements of the synchronous usefulness of transfer of data.Fig. 1 shows the schematic diagram of conventional P LL.As shown in Figure 1, conventional P LL comprise phase-frequency detector (phase frequency detector, PFD) 101, loop filter 102, VCO 103 and divider 104.As shown in Figure 1, PFD 101 receives reference signals 110 and from the feedback signal 104a of divider 104, and output control signal 101a, and control signal 101a represents whether feedback signal falls behind or this reference signal in advance.Loop filter 102 converts control signal 101a to voltage signal 102a and uses for VCO 103, and is used as bias voltage.VCO 103 according to voltage signal 102a very fast or than slow oscillation to produce output signal 103a.Output signal 103a is feed-in divider 104 also, so that became feedback signal 104a earlier before feed-in PFD 101.By this way, PLL can produce stable output signal, this also be why except other are used PLL also extensively be used as the reason of clock generator.In clock generator, output signal 103a provides the clock to remaining circuit in the electronic installation, with further control and the operation of this electronic installation synchronously.

Yet in conventional P LL, reference signal 110 is normally from fixing external source, such as the crystal that can produce clock, as shown in Figure 1.Last output signal 103a normally has the signal of external crystal resonance frequency.For example, at the PLL that is used in USB 2.0 application, the 480MHz clock rate can produce by the source of using the 12MHz crystal to be used as reference signal 110.

Generally, the phase-frequency detector that often is used in conventional P LL design need rely on the edge relative timing of feedback signal and reference signal that is phase place.At this moment, when two kinds of signals are same frequency, can produce the fixedly output that is proportional to phase difference.On the other hand, be used in that the advantage that phase detectors were provided based on logic gates is among the PLL,, but can force VCO to be synchronized with reference signal fast even reference signal is the initial output frequency that is different from VCO in essence.Fig. 2 shows the conventional phase testing mechanism according to justified margin.This justified margin can apply and be limited in some application, such as high-speed applications.

Another restriction of conventional phase frequency detector is to need fixing external source.This not only increases the cost of electronic installation, also can hinder the elasticity of design.Therefore, the improvement phase-detection mechanism that is used for flexible PLL design and reduces manufacturing cost is made in very favourable creation.

Summary of the invention

The present invention is in order to overcome the shortcoming of above-mentioned conventional P LL design.Main purpose of the present invention providing a kind of have improve phase-detection mechanism, can make phase-detection have elasticity and can be applicable to high-speed applications.

Another object of the present invention is in that a kind of PLL that improves phase-detection mechanism that has is provided, so that the reference signal source of flexible reference signal and eliminate separate to be provided, to reduce manufacturing cost and complexity.

For achieving the above object, the invention provides and have the PLL that improves phase-detection mechanism, comprise phase-frequency detector (PFD), controller, digital-to-analogue conversion (D2A) module and voltage-controlled oscillator/current control oscillator (VCO/ICO), wherein PFD has reference signal input and from the input of the output signal of VCO/ICO, and be connected to controller, then this controller further is connected to the D2A module, and the D2A module converts comes the control signal of self-controller to become frequency and the phase place of aanalogvoltage with control VCO/ICO.

Beneficial effect of the present invention is that PFD of the present invention has the phase-detection of improvement mechanism, so that phase-detection does not rely on justified margin.In addition, improve phase-detection mechanism flexible reference signal input also is provided, as originating, such as crystal with respect to fixed outer.

Above-mentioned and other purpose of the present invention, characteristic, characteristics and advantage will become better and understand by carefully studying detailed description under this and the suitable appended accompanying drawing of reference carefully.

Description of drawings

Fig. 1 shows the schematic diagram of conventional phase locked loops (PLL);

Fig. 2 shows the waveform schematic diagram of tradition according to the phase-detection of justified margin;

Fig. 3 shows the first exemplary waveform schematic diagram that improves phase-detection according to the present invention;

Fig. 4 shows the second exemplary waveform schematic diagram that improves phase-detection according to the present invention; And

Fig. 5 shows the schematic diagram with the phase-locked loop (PLL) that improves phase-detection mechanism.

Wherein, description of reference numerals is as follows:

101 phase-frequency detectors (PFD)

The 101a control signal

102 loop filters

The 102a voltage signal

103 voltage-controlled oscillators (VCO)

The 103a output signal

104 dividers

The 104a feedback signal

110 reference signals

501 phase-frequency detectors (PFD)

502 controllers

503 digital-to-analogue conversions (D2A) module

504 voltage-controlled oscillators/current control oscillator (VCO/ICO)

The 504a output signal

The input of 510 reference signals

A-signal

The Ad inhibit signal

The B1 signal

The B2 signal

Embodiment

PLL of the present invention uses the phase-detection mechanism of improving.As mentioned above, the conventional phase frequency detector often uses the fixed outer source, such as crystal, to be used as reference signal.The final output signal of PLL is the resonance of reference signal normally.For example, in USB 2.0, the 480MHz clock rate can obtain to be used as the reference clock source by fixing outside 12MHz crystal.

This improvement phase-detection mechanism does not need the external source fixed.But, according to the phase-detection mechanism of PLL of the present invention,, analyze reference signal and VCO output signal earlier producing control signal to before the controller.Last output signal is relevant for reference signal, but the resonance of the frequency of reference signal not necessarily.Below will illustrate how in phase-detection, to analyze reference signal and output signal according to the present invention.

Fig. 3 shows the first exemplary waveform schematic diagram that improves phase-detection according to the present invention.For simplicity, employed waveform is the regular periodicity waveform in this example embodiment, that is 1,0,1,0,1,0 ... the tandem that waits.As shown in Figure 3, first waveform is denoted as A, that is signal A, and second waveform is inhibit signal Ad, that is has the waveform that is same as signal A and has phase retardation.The 3rd waveform is shown as signal B1, has the frequency also higher than half frequency of signal A.For simplicity, signal A can be considered the viewed signal by observer's signal B.As shown in Figure 3, if signal A and inhibit signal Ad are the rising edge samplings at signal B1, it is right then to can be observed four groups of different numbers, that is (1,1), (1,0), (0,0) reaches (0,1), wherein first of every group of number centering is the level of signal A, and second is the level of inhibit signal Ad.In addition, can be observed (1,1)-＞(1,0), (1,0)-＞(0,0), (0,0)-＞(0,1), (0,1)-＞transformation of (1,1).That is, when half of the observed frequency of observer's frequency ratio is also high, can be observed any combination of above-mentioned four kinds of transformations, that is (1,1)-＞(1,0), (1,0)-＞(0,0), (0,0)-＞(0,1), (0,1)-＞(1,1).Similarly, the 4th Waveform display signal B2 has the frequency also lower than half frequency of signal A.If signal A and inhibit signal Ad are the rising edge samplings at the 4th waveform (that is signal B2), it is right then to can be observed four groups of different numbers, that is (1,1), (1,0), (0,0), (0,1), wherein first of every group of number centering is the level of signal A, and second is the level of inhibit signal Ad.In addition, can be observed (1,1)-＞(0,1), (0,1)-＞(0,0), (0,0)-＞(1,0), (1,0)-＞transformation of (1,1).That is, when half of the observed frequency of observer's frequency ratio is also low, can be observed any combination of above-mentioned four kinds of transformations, that is ((1,1)-＞(0,1), (0,1)-＞(0,0), (0,0)-＞(1,0), (1,0)-＞(1,1).By the observation of exemplary waveform show (1,1)-＞(1,0), (1,0)-＞(0,0), (0,0)-＞(0,1), (0,1)-＞(1,1) transformation implies, and observer's frequency such as signal B1, is also faster than half of observed frequency, such as signal A, and (1,1)-＞(0,1), (0,1)-＞(0,0), (0,0)-＞(1,0), (1,0)-＞transformation of (1,1) implies observer's frequency, such as signal B2, is also slower than half of observed frequency, such as signal A.

Fig. 4 shows the second exemplary waveform schematic diagram that improves phase-detection according to the present invention.This exemplary waveform is also to may extend to irregular or aperiodicity observer waveform through vague generalization with the observation of the transformation pattern of displayed map 3, that is signal B1 and signal B2.As shown in Figure 4, first waveform is signal A, and second waveform is inhibit signal Ad.The 3rd waveform shows that observer's signal B 1 has the frequency also higher than half frequency of signal A.If signal A and inhibit signal Ad are in the sampling of the rising edge of observer's signal B1, then can be observed (1,0), (0,0), (0,1), (1,1), (1,0), (0,0) ... tandem.Again, can observedly severally observe the transformation of four kinds of different types above-mentioned to the diverse location in the tandem, that is (1,1)-＞(1,0), (1,0)-＞(0,0), (0,0)-＞(0,1), (0,1)-＞(1,1).Similarly, the 4th waveform shows that observer's signal B2 has the frequency also lower than half frequency of signal A.If signal A and inhibit signal Ad are the rising edge samplings at the 4th waveform (that is observer's signal B2), then observe (1,1), (0,1), (0,0), (1,0), (1,1), (0,1) ....And similarly, can observedly severally observe the transformation of four kinds of different types above-mentioned to the diverse location in the tandem, that is (1,1)-＞(0,1), (0,1)-＞(0,0), (0,0)-＞(1,0), (1,0)-＞(1,1).Therefore, even when observer's signal has aperiodicity and scrambling waveform, the appearance of transformation can be in order to indicate the relative frequency between observed signal and the observer's signal.

The result who is summed up by above-mentioned two demonstration example is, the relation between observed signal and the observer's signal can be by observing the transformation found in the right tandem of observed number of signals and be detected.When observer's frequency is higher than a half of observed frequency, B1＞A in the example when above-mentioned can find the transformation of four kinds of different types in observed several right tandems, that is (1,1)-＞(1,0), (1,0)-＞(0,0), (0,0)-＞(0,1), (0,1)-＞(1,1).On the other hand, when observer's frequency is lower than a half of observed frequency, B2＜A in the example when above-mentioned, can in observed several right tandems, find the transformation of four kinds of different types, that is (1,1)-＞(0,1), (0,1)-＞(0,0), (0,0)-＞(1,0), (1,0)-＞(1,1).The transformation of every other pattern, such as (1,1)-＞(0,0), (1,0)-＞(0,1), or vice versa, all can abandoning of safety and can not have influence on testing mechanism.

Relation between the transformation pattern of the observed signal of this detection and the relative frequency of observer and observed signal has two important implications.First implication is no longer to need the edge of phase-detection with the variance signal of align earlier before relatively reference signal and VCO/ICO output signal.This is non-when important, because justified margin is that very difficult restriction is applied on the high-speed applications for phase-detection.Secondary Meaning is that it is the external source of fixing that reference signal no longer needs, such as crystal.But reference signal can be Any Digit signal tandem, and improves the necessary phase-detection operation that phase-detection mechanism can be used for PLL.Utilize to improve phase-detection mechanism, the signal that PFD can concern between the output observed frequency of expression and the observer's frequency to the transformation pattern found in the tandem and easily according to observed number of signals.

Therefore, Fig. 5 shows the schematic diagram that has the phase-locked loop (PLL) that improves phase-detection mechanism according to the present invention.As shown in Figure 5, PLL of the present invention comprises phase-frequency detector (PFD) 501, controller 502, digital-to-analogue conversion (D2A) module 503 and voltage-controlled oscillator/current control oscillator (VCO/ICO) 504.PFD 501 has reference signal input 510 and from the input of the output signal 504a of VCO/ICO 504, and is connected to controller 502.Then this controller 502 further is connected to

D2A module

503, and 503 conversions of D2A module come the control signal of self-controller 502 to become aanalogvoltage or electric current, with frequency and the phase place of control VCO/ICO 504.It should be noted that PFD 501 of the present invention has the improvement phase-detection mechanism according to the exemplary waveform of Fig. 3 and Fig. 4.Therefore, PFD 501 is than VCO output signal 504a and reference signal 510, to produce the signal whether expression VCO output signal comparatively fast or is slower than the frequency of reference signal.According to the signal that receives from PFD 501, controller 502 control D2A modules 503 output aanalogvoltage or electric currents, and then frequency and the phase place of the output signal 504a of control VCO/ICO 504.

It should be noted that, when reference signal 510 stops or disappearing, controller 502 can will be kept original signal earlier before stopping reference signal 510, that is maintenance is sent to the control signal of D2A module 503, make D2A module 503 can not change the analog voltage/current that exports VCO/ICO to, to change frequency and the phase place of output signal 504a.In other words, keep output signal 504a, that is locking, till reference signal 510 occurs once more.By this way, PFD can switch to different reference signals, is used as in order to phase-detection basis relatively.The example embodiment that realizes " locking " is to utilize counter or any equity mechanism with realization D2A module 503, and this any reciprocity mechanism can be increased and reduce, so that expression signal very fast or slow frequency can shine increase or reduce numerical value.When reference signal 510 disappeared, counter or any equity mechanism kept this numerical value, so that do not increase or reduce to operate the numerical value that is kept to change.

The main application that the present invention has a PLL that improves phase-detection mechanism is the electronic installation such as USB 2.0, can use the serial data that comes the main frame of PC (PC) freely ought act on synchronous reference signal.

And it should be noted that improving phase-detection mechanism can further extend to comprise more than one inhibit signal, accelerating ated test when very big with the difference between convenient observer's frequency and the observed frequency.For example, have the second inhibit signal A ' of phase delay a little, have more the 3rd inhibit signal A of leggy delay " or the like; all can add, so that observed sets of signals (A, A '; A " ...) be to be recorded in to improve in the phase-detection mechanism, to quicken the convergence of different frequency.

Though the present invention describes with reference to preferred embodiment, be noted that the present invention is not the details that is subject in the explanation.The different replacement and modification suggestion in the above description, and other replacements and modification will take place for those skilled in the art.Therefore, all these replacements and modification all are intended to be included in by within the defined protection range of the present invention of claims.

Claims

1. one kind has the phase-locked loop that improves phase-detection mechanism, comprising:

One phase-frequency detector, have one first the input and one second the input, and according to this first the input and this second the input relative frequency to produce a signal, represent this second the input frequency whether comparatively fast or be slower than this first the input frequency;

One controller is connected to this phase-frequency detector, in order to reception this signal from this phase-frequency detector, and produces a control signal;

One D/A converter module is connected to this controller, in order to receiving this control signal, and produces analog voltage/current output; And

One voltage-controlled oscillator is connected to this D/A converter module, in order to receive this analog voltage/current output, regulates an output signal according to this,

Wherein this of this phase-frequency detector first input is connected to a reference signal, and this second input is connected to this output signal of this voltage-controlled oscillator.

2. phase-locked loop as claimed in claim 1 is characterized in that, this voltage-controlled oscillator can be replaced by a current control oscillator.

3. phase-locked loop as claimed in claim 1, it is characterized in that, relatively this first input of this phase-frequency detector, this second input and one postpone second input, the waveform that this delay second input has is same as this second input and has phase delay, the appearance of the transformation that this second input and first group that postpones the transformation pattern of second input are had is also fast in order to this second frequency of importing of frequency ratio of representing this first input.

4. phase-locked loop as claimed in claim 1, it is characterized in that, relatively this first input of this phase-frequency detector, this second input and one postpone second input, the waveform that this delay second input has is same as this second input and has phase delay, the appearance of the transformation that this second input and second group that postpones the transformation pattern of second input are had, also slow in order to this second frequency of importing of frequency ratio of representing this first input.

5. phase-locked loop as claimed in claim 1 is characterized in that this reference signal is from an external crystal.

6. phase-locked loop as claimed in claim 1 is characterized in that, this reference signal is the numerical data from a main frame.

7. phase-locked loop as claimed in claim 3 is characterized in that, this second input and first group that postpones the transformation pattern of second input comprise (1,1)-＞(1,0), (1,0)-＞(0,0), (0,0)-＞(0,1), (0,1)-＞(1,1), each several right first is observation level of this second input, and second is the observation level that this delays second is imported.

8. phase-locked loop as claimed in claim 4 is characterized in that, this second input and second group that postpones the transformation pattern of second input comprise (1,1)-＞(0,1), (0,1)-＞(0,0), (0,0)-＞(1,0), (1,0)-＞(1,1), each several right first is observation level of this second input, and second is the observation level that this delays second is imported.

9. phase-locked loop as claimed in claim 1, it is characterized in that, this reference signal is when stopping or disappearing, this D/A converter module kept original control signal numerical value earlier before this reference signal stops, so that this D/A converter module will can not change this analog voltage/current output that is sent to this voltage-controlled oscillator/Current Control vibration and change to this output signal frequency and phase place.

10. phase-locked loop as claimed in claim 9 is characterized in that, this D/A converter module is to realize by the equity mechanism that a counter maybe can increase or reduce.

11. phase-locked loop as claimed in claim 3 is characterized in that, improves phase-detection mechanism and uses a plurality of being somebody's turn to do to postpone second input, each this delay second input has mutual same waveform as and out of phase.

12. phase-locked loop as claimed in claim 4 is characterized in that, improves phase-detection mechanism and uses a plurality of being somebody's turn to do to postpone second input, each this delay second input has mutual same waveform as and out of phase.