CN102299657A - Input-series and output-series (ISOS) inverter system and voltage-sharing input and same-phase output control method thereof - Google Patents

Abstract

The invention discloses an input-series and output-series (ISOS) inverter system and a voltage-sharing input and same-phase output control method thereof, and belongs to the field of direct current-alternating current converters. The inverter system comprises a power supply circuit and n inverter modules, wherein each inverter module has a high-frequency isolation two-stage structure, a front stage is a full-bridge direct current converter, and a rear stage is a full-bridge inverter. A control loop of the inverter system mainly comprises a shared output voltage loop and the input voltage-sharing loop and current inner loop of each inverter module; and the three loops act in a matched mode to ensure that the phases of output voltages of the modules are consistent, and output voltage sharing is realized by combining the action of input voltage sharing. The input voltage sharing and output voltage sharing of the inverter system are realized, and the input voltage-sharing loop and the output voltage loop are decoupled, so that the loop design of the system is effectively simplified.

Description

Output same-phase control method is all pressed in a kind of ISOS inverter system and input thereof

Technical field

The present invention relates to a kind of inverter system, output same-phase control method is all pressed in the inverter system and the input thereof that relate in particular to a kind of input series connection output series connection (ISOS), belongs to the direct-current-alternating-current converter field of transformation of electrical energy device.

Background technology

In recent years, along with the further investigation to power electronic technology, people are more and more higher to the requirement of transformation of electrical energy device, particularly in the application scenario of many high DC input voitage, device in the level converter thereafter chosen the comparison difficulty.For example in urban rail transit vehicles, their pantagraph current collector receives direct current energy from overhead contact line or the 3rd rail, its power supply grid has 750V direct current and two kinds of systems of 1500V direct current, and the former allows the change in voltage scope is 500～900V, and it is 1000～1800V that the latter allows the change in voltage scope.For example the China railways passenger train adopts 600V direct current supply again, its change in voltage scope is 500～660V direct current, employing 850～1250V the direct current that in the ship power supply system there is supply voltage, the DC bus-bar voltage in the high-speed electrified line is especially up to 2160～2600V.As seen, so high input voltage amplitude has proposed stern challenge to choosing of the inverter device in the above-mentioned electrical system.In addition, in some occasion, such as the three-phase input, if adopt power factor correction technology, the output voltage of power factor correcting converter may be up to 800～1000V, and back level converter is difficult to select suitable switching device.

The connection in series-parallel combined system of standardized module is as the integrated important branch of power electronic system, adopt series-parallel combination connecting mode, can obtain power conversion system flexible and changeable, any input and output performance by the standardized module of a plurality of small-powers, low pressure (input and output).Input tandem type inverter system wherein (comprising ISOP and ISOS inverter) is highly suitable for the inverter in the electrical systems such as above-mentioned boats and ships, high-speed electrified line and urban track traffic.Because such system input adopts cascaded structure, the input voltage of each module will be reduced to original 1/n (n is a number of modules), be easy to select suitable switching device, simultaneously, the ISOS inverter system also is specially adapted to the higher interchange electricity consumption occasion of output voltage.For such changer system, the key issue that needs at present to solve is the equalization problem of each module input voltage and output voltage.

Summary of the invention

The present invention is directed to the high voltage direct current input and exchange the output occasion, propose a kind of ISOS inverter system and input thereof and all press output same-phase control method, to solve the equalization problem of input, output voltage.

This ISOS inverter system comprises power circuit and n inverter module, described power circuit comprises input source and n input dividing potential drop electric capacity, after being connected in series successively, n input dividing potential drop electric capacity is parallel between the positive-negative input end of input source, a described n inverter module all is to connect full-bridge inverter by full-bridge direct current converter to constitute, the input of full-bridge direct current converter is as the input of inverter module, the output of full-bridge inverter is as the output of inverter module, the input of n inverter module is parallel to the two ends of corresponding input dividing potential drop electric capacity respectively, the positive output end of first inverter module connects the negative output terminal of n inverter module by load, make i=2,3, ..., n, the positive output end of i inverter module connects the negative output terminal of i-1 inverter module.

Output same-phase control method is all pressed in the input of above-mentioned ISOS inverter system, specifically comprises following content:

System's output voltage sampled signal is through K _VoDoubly obtain output voltage feedback, K after the decay _VoBe output voltage closed loop sampling coefficient, the output voltage feedback obtains the common current benchmark through the closed loop pi regulator after subtracting each other with reference voltage again;

The input voltage error signal of each inverter module is all earlier through K _VcdDoubly obtain the dc error signal of each inverter module after the decay again through the grading ring pi regulator, K _VcdBe the input voltage attenuation coefficient, obtain the current reference of each inverter module after the dc error signal of each inverter module all multiplies each other with the common current benchmark again with the stack of common current benchmark;

The inverse cascade capacitance current sampled signal of each inverter module is all earlier through K _CfDoubly the output capacitance electric current that obtains each inverter module again by ternary hysteresis current adjuster, K are subtracted each other with the current reference of corresponding inverter module in the decay back _CfBe current inner loop sampling coefficient, the output capacitance electric current of each inverter module all multiply by 1/sC _fObtain the output voltage of each inverter module, 1/sC _fBe the output capacitance electric current and the relation of the transfer function between the output voltage of each inverter module, the output voltage addition of each inverter module is promptly obtained system's output voltage.

Technique effect:

1, the main circuit topology of inverter system adopts the two-stage type structure of high-frequency isolation, is convenient to realize the ISOS series connection framework of each module input/output terminal.

2, all pressures are all pressed and are exported in the input that has realized the ISOS inverter system.

3, input grading ring in the control loop and output voltage ring work alone each other, realized decoupling zero, effectively simplified the loop design of system, can carry out independent design respectively to input grading ring and output voltage ring, its effect does not influence every performance of system.

Description of drawings

Fig. 1 (a) is the main circuit topology figure of ISOS inverter system of the present invention, and Fig. 1 (b) is the control principle figure of ISOS inverter system of the present invention.

Fig. 2 is the schematic diagram of ISOS inverter system of the present invention.

Fig. 3 is the simplification control principle figure of ISOS inverter system of the present invention.

Fig. 4 is the further reduced graph of Fig. 3.

Fig. 5 is an output voltage closed loop transfer function, block diagram.

Fig. 6 is the prime DC/DC converter loop control theory figure of inverter module.

Main designation in the above accompanying drawing: C _D1～C _DnBe input dividing potential drop electric capacity; V _Cd1～V _CdnBe input dividing potential drop capacitance voltage; I _In1～I _InnInput current for each inverter module; I _Cd1～I _CdnBe input dividing potential drop capacitance current; v _O1～v _OnOutput voltage for each inverter module; i _oBe system's output current; I _InBe system's input current; K _VcdBe the input voltage attenuation coefficient; G _IVSR(s) be input grading ring pi regulator; v _{Cd_EA1}～v _{Cd_EAn}Dc error signal for each inverter module; K _VoBe output voltage closed loop sampling coefficient; G _OVR(s) be output voltage ring pi regulator; i _RefBe the common current reference signal; i _EA1～i _EAnFor with i _RefSynchronous sinusoidal error signal; i _Ref1～i _RefnCurrent reference signal for each inverter module; i _Cf1～i _CfnInverse cascade output capacitance current signal for each inverter module; K _CfBe current inner loop sampling coefficient; Z _LdBe fully loaded with for system is resistive; V _DcjBe the output voltage of the prime DC/DC converter of each inverter module, j=1,2...n; K _VdcOutput voltage attenuation coefficient for the prime DC/DC converter; D _QStable state duty ratio for the prime DC/DC converter; V _PpSawtooth waveforms amplitude for the prime DC/DC converter.

Embodiment

The invention will be further described below in conjunction with accompanying drawing.

Here analyze the present invention earlier and realize the control principle that the input and output of ISOS inverter system are all pressed.

Because the power output of inverter had both comprised active power, comprised reactive power again, so above-mentioned controlled target is exactly will be when realizing that input is all pressed, the equilibrium by control active power of output and reactive power realizes that output all presses.

The schematic diagram of the ISOS inverter system that the present invention relates to supposes that the conversion efficiency of each inverter module is 100% as shown in Figure 2, and the input power of each inverter module equals its active power of output so, that is:

$\left\{\begin{array}{c}{P}_{\mathrm{in}1}={\mathrm{<figure-callout\; id="1"\; label="V\; cd"\; filenames="HDA0000087722010000022.png,HDA0000087722010000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{cd}}\&CenterDot;I_{\mathrm{in}1}=V_{o1}\&CenterDot;I_o\&CenterDot;{\cos \mathrm{\&theta;}}_1=P_{o1}\\ P_{\mathrm{in}2}=V_{\mathrm{cd}2}\&CenterDot;I_{\mathrm{in}2}=V_{o2}\&CenterDot;I_o\&CenterDot;{\cos \mathrm{\&theta;}}_2=P_{o2}\\ M\\ P_{\mathrm{inn}}=V_{\mathrm{cdn}}\&CenterDot;I_{\mathrm{inn}}=V_{\mathrm{on}}\&CenterDot;I_o\&CenterDot;{\cos \mathrm{\&theta;}}_n=P_{\mathrm{on}}\end{array}\right.---\left(1\right)$

In the formula (1): P _In1～P _InnInput power for each inverter module; P _O1～P _OnActive power of output for each inverter module; V _O1～V _OnOutput voltage effective value for each inverter module; I _oOutput current effective value for system; θ ₁～θ _nOutput power factor angle for each inverter module.

If adopt the input Pressure and Control at system input, when system reached stable state, the electric current that each inverter module is imported on the dividing potential drop electric capacity accordingly remained unchanged, and its mean value is zero, that is:

I _cd1＝I _cd2＝...＝I _cdn＝0 (2)

Further can get:

I _in1＝I _in2＝...＝I _inn＝I _in (3)

And owing to adopt the input Pressure and Control, so can get:

V _cd1＝V _cd2＝...＝V _cdn (4)

Convolution (1), (3), (4) can get:

V _o1·I _o·cosθ ₁＝V _o2·I _o·cosθ ₂＝L＝V _on·I _o·cosθ _n (5)

If on the basis of formula (5), control each inverter module output voltage amplitude simultaneously or phase place identical, even following one of them establishment of two formulas:

V _o1＝V _o2＝L＝V _on (6)

θ ₁＝θ ₂＝L＝θ _n (7)

If formula (5) and formula (6) are set up, then can get formula (7) and set up, again or make formula (5) and formula (7) establishment, then can get formula (6) sets up, both of these case finally all can obtain each inverter module output voltage amplitude and phase place and equate respectively, thus following formula (8) establishment, i.e. and output is all pressed.

v _o1＝v _o2＝...＝v _on (8)

By above analysis as can be known,, all press, then can only guarantee the equilibrium of each inverter module active power of output, and reactive power may not be balanced, also just can not guarantee to export all to press if control its input at system input for the ISOS inverter system; And if on the basis that the control system input is all pressed, it is identical to control each inverter module output voltage amplitude or phase place simultaneously, then can realize all pressures of output.

The main circuit topological structure of the ISOS inverter system that the present invention relates to comprises a power circuit and n inverter module shown in Fig. 1 (a), described power circuit comprises input source V _InWith n input dividing potential drop capacitor C _D1～C _Dn, n input dividing potential drop capacitor C _D1～C _DnBe parallel to input source V after the serial connection successively _InPositive-negative input end between, the input of n inverter module is parallel to the two ends of corresponding input dividing potential drop electric capacity respectively, the positive output end of the first inverter module 1# connects the negative output terminal of n inverter module n# by load, make i=2,3, ..., n, the positive output end of i inverter module connects the negative output terminal of i-1 inverter module.Can carry out the requirement of tandem compound for satisfying the native system input/output terminal, the two-stage type structure of the main circuit topology employing high-frequency isolation of each inverter module---straight-straight conversion stage 1 and straight-friendship inverse cascade 2, wherein isolated form DC-DC converter transforms to input voltage the input voltage of inverter requirement and realizes electrical isolation, its high frequency transformer that adopts has the little advantage such as in light weight of volume, is easy to realize modularization.Directly-and straight conversion stage employing full-bridge direct current converter, the voltage stress that each switching device bears in this converter is an input voltage, and can adopt the phase-shift soft switch technology, to reduce the voltage stress of switching tube and rectifier diode, improves the efficient of converter; Directly-hand over inverse cascade to adopt full-bridge inverter, full-bridge inverter is applicable to more powerful application scenario, and there is the output voltage between brachium pontis in it is no-voltage, it is the state of output inductor electric current nature afterflow, therefore the ternary modulation of brachium pontis output voltage can be realized, thereby better output effect can be under lower switching frequency, obtained.

The input of the ISOS inverter system that the present invention proposes all presses the control principle figure of output same-phase control method shown in Fig. 1 (b).In this controlling schemes, its control loop mainly comprises output voltage closed loop 3 and the input grading ring 4 of each module and the current inner loop 5 of each module that each inverter module is shared.The shared total output voltage stabilization work of output voltage closed loop 3 controls, in this control loop, system's output voltage sampled signal is through K _VoThe output voltage feedback v that doubly decays and obtain _OfWith reference voltage V _RefSubtract each other after pi regulator G _OVRObtain the shared current reference i of each module _RefBecause controlled device is an inverter, common current benchmark i _RefNot only comprise amplitude information, also comprise phase information, so introduced multiplier here, the semaphore that is used for the fine-adjusting current benchmark with assurance input grading ring is identical with original current reference maintenance phase place.In each input grading ring, the input voltage V that each inverter module should be assigned to _In/ n input voltage v actual with it _Cdj(j=1,2...n) poor (being the input voltage error signal) is through K _VcdDoubly send into pi regulator G after the decay _IVSRObtain dc error signal v _{Cd_EAj}(j=1,2...n), each dc error signal and common current benchmark i _RefBehind multiplier, obtain and i _RefSynchronous sinusoidal error signal i _EAj(j=1,2...n), each sinusoidal error signal is superimposed upon common current benchmark i _RefGo up finely tuning the amplitude of each blocks current benchmark, thereby obtain the required current reference signal i of each module _Refj(j=1,2...n).The current inner loop of each inverter module adopts the ternary ring control that stagnates, sampling be the inverse cascade output capacitance electric current of each module, each blocks current reference signal i _RefjWith K _CfDoubly the difference of the capacitance current after the decay is sent into ternary hysteresis current adjuster G _I, G _IThe capacitance current i of output _Cfj(j=1,2...n) with electric capacity on voltage (be each module output voltage v _Oj, j=1 2...n) exists intrinsic transfer function to concern 1/sC _f, s is the Laplace transformation factor, so with i _CfjMultiply by 1/sC _fPromptly obtain v _Oj, each module output voltage v _OjSum is the output voltage v of system _oBecause the sampling of the current inner loop of each module is the capacitance current of each module, so above-mentioned input grading ring is only finely tuned the amplitude of each module capacitance current reference, and that their phase place remains is identical, thereby each module capacitance current tracking benchmark also keeps the phase place unanimity.Further, because the direction of each module capacitance sense of current and output voltage differs pi/2,, promptly there is formula (7) to set up so above-mentioned control has also just guaranteed the phase place unanimity of each module output voltage.Input grading ring 4 is by regulating the output capacitance current i of inverse cascade _Cf(or inductive current i _Lf), and then the load current i of change prime DC/DC converter _DcReaching the purpose that realizes each module input voltage equilibrium, thereby formula (4) and formula (5) establishment are arranged.Set up and can get formula (6), and finally can get formula (8) establishment by formula (5) and formula (7).Convolution (4) and formula (8) as can be known, above-mentioned input is all pressed in conjunction with the synchronous controlling schemes of output and has been realized that simultaneously input all presses and export all and to press.

In Fig. 1 (b), the output voltage v of system _oActual input voltage v with n inverter module _Cdj, n+1 variable needs control altogether.As if the surface is seen interrelatedly between these controlled variables, if directly system is analyzed and designs with very difficult, the relation between each controlled variable of for this reason further analyzing and researching here is with the complexity of simplified system.

In the accompanying drawing 1 (b), the current inner loop of each module adopts the ternary ring control that stagnates, because inverter switching frequency is far above its output voltage frequency, so current inner loop can equivalence be a current follower, and its multiplication factor is 1/K _CfSo, can obtain the control principle figure of system after the simplification as shown in Figure 3, can get by Fig. 3:

$\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}(i_{\mathrm{ref}}-i_{\mathrm{EAj}})\&CenterDot;\frac{1}{{\mathrm{sK}}_{\mathrm{cf}}{C}_f}=({\mathrm{ni}}_{\mathrm{ref}}-\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{i}_{\mathrm{EAj}})\&CenterDot;\frac{1}{{\mathrm{sK}}_{\mathrm{cf}}{C}_f}$

$=(i_{\mathrm{ref}}-\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{i}_{\mathrm{EAj}}/n)\&CenterDot;\frac{n}{{\mathrm{sK}}_{\mathrm{cf}}{C}_f}=v_o---\left(9\right)$

The further simplification of Fig. 3 can be obtained Fig. 4 according to formula (9).I among Fig. 4 _EAj(j=1 2...n) is equivalent to the disturbance of system in the output voltage ring.Can get according to Fig. 1 (b):

$i_{\mathrm{EA}1}+i_{\mathrm{EA}2}+L+i_{\mathrm{EAn}}=\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}[(V_{\mathrm{in}}/n-v_{\mathrm{cdj}})\&CenterDot;K_{\mathrm{vcd}}\&CenterDot;G_{\mathrm{IVSR}}\left(s\right)]\&CenterDot;i_{\mathrm{ref}}$

$=(V_{\mathrm{in}}-\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{v}_{\mathrm{cdj}})\&CenterDot;K_{\mathrm{vcd}}\&CenterDot;G_{\mathrm{IVSR}}\left(s\right)\&CenterDot;i_{\mathrm{ref}}---\left(10\right)$

Can get by Fig. 1 (a):

$V_{\mathrm{in}}-\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{v}_{\mathrm{cdj}}=0---\left(11\right)$

Formula (11) substitution formula (10) is obtained:

i _EA1+i _EA2+L+i _EAn＝0 (12)

As seen, though the input regulated quantity i of each module _EAjTransient change, but total input regulated quantity instantaneous value of n module is zero.The value that total input all presses regulated quantity to be added in the Voltage loop is zero, so the influence of grading ring work is not imported in the work of Voltage loop.

The output signal i of output voltage ring _RefFor each module provides electric current loop given, work as i _RefWhen changing, the given signal i of the electric current loop of all modules _RefjAll change simultaneously, the power output of each module and input power are also changed thereupon.In order to guarantee output voltage stabilization, output voltage ring output signal i _RefIncrease, the capacitance current of each module will increase, thereby each module output voltage also will raise, but still guarantee all pressures of output, and power output also equates.According to energy conservation relation, the input current of each module and system's input current all will increase.Because each module input current equates that still input dividing potential drop capacitance current mean value is zero, then each module still keeps importing equal pressure condition, and the work of visible output voltage ring does not change the state of each module input voltage, does not influence the work of input grading ring yet.

Input grading ring and output voltage ring work alone each other, have realized the circuit decoupling zero, can independently analyze and design input grading ring and output voltage ring respectively, and its effect does not influence every performance of system.

According to formula (12), Fig. 4 further can be simplified obtaining Fig. 5, in fact it is exactly output voltage closed loop transfer function, block diagram, for improving the precision of output voltage, adopts pi regulator to implement cascade compensation, and its transfer function is the G among Fig. 5 _OVR(s).

Remark additionally in addition, about the input grading ring, shown in Fig. 1 (a) and (b), this closed-loop control is with input reference voltage V _In/ n and the actual input of prime DC/DC converter dividing potential drop v _CdjBetween error as control signal, regulate the capacitance current i of back level inverter _Cf(or inductive current i _Lf), and then the load current i of change prime DC/DC converter _DcTo reach the purpose that realizes each module input capacitance electric voltage equalization of DC/DC converter.Therefore, need set up above-mentioned association between variables, to obtain importing the transfer function that all presses off ring.In addition because the prime DC/DC converter adopts closed-loop control, control principle figure as shown in Figure 6, so setting up i _DcWith v _CdBetween contact the time need consider this point, before design all presses off ring, need earlier prime to be controlled closed loop and design.

Claims (2)

1. an ISOS inverter system comprises a power circuit and n inverter module, and described power circuit comprises input source (V _In) and n input dividing potential drop electric capacity (C _D1～C _Dn), n input dividing potential drop electric capacity (C _D1～C _Dn) be parallel to input source (V after the serial connection successively _In) positive-negative input end between, a described n inverter module all is to connect full-bridge inverter by full-bridge direct current converter to constitute, the input of full-bridge direct current converter is as the input of inverter module, and the output of full-bridge inverter is characterized in that as the output of inverter module:

The input of a described n inverter module is parallel to the two ends of corresponding input dividing potential drop electric capacity respectively, the positive output end of first inverter module (1#) connects the negative output terminal of n inverter module (n#) by load, make i=2,3, ..., n, the positive output end of i inverter module connects the negative output terminal of i-1 inverter module.

2. output same-phase control method is all pressed in the input based on the described ISOS inverter system of claim 1, it is characterized in that:

This method comprises following content:

System's output voltage sampled signal is through K _VoDoubly obtain output voltage feedback (v after the decay _Of), K _VoBe output voltage closed loop sampling coefficient, output voltage feedback (v _Of) and reference voltage (V _Ref) subtract each other after again through closed loop pi regulator (G _OVR) obtain common current benchmark (i _Ref);

The input voltage error signal of each inverter module is all earlier through K _VcdDoubly after the decay again through grading ring pi regulator (G _IVSR) obtain the dc error signal of each inverter module, K _VcdBe the input voltage attenuation coefficient, the dc error signal of each inverter module all with common current benchmark (i _Ref) multiply each other after again with common current benchmark (i _Ref) superposeing obtains the current reference of each inverter module;

The inverse cascade capacitance current sampled signal of each inverter module is all earlier through K _CfDoubly the output capacitance electric current that obtains each inverter module again by ternary hysteresis current adjuster, K are subtracted each other with the current reference of corresponding inverter module in the decay back _CfBe current inner loop sampling coefficient, the output capacitance electric current of each inverter module all multiply by 1/sC _fObtain the output voltage of each inverter module, 1/sC _fBe the output capacitance electric current and the relation of the transfer function between the output voltage of each inverter module, the output voltage addition of each inverter module is promptly obtained the output voltage (v of system _o).

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