CN102298973B - Anti-radiation fault-secure type memory device and anti-radiation fault-secure method thereof - Google Patents

Abstract

The invention discloses an anti-radiation fault-secure type memory device, and an anti-radiation fault-secure method thereof, and relates to an anti-radiation fault-secure type memory device, and a protection method thereof. In the prior art, multiple-bit upsets exist in the existing memory array; single event transient effects exist in an encoder, a decoder and other combinational circuits; EG-LDPC codes require a plurality of redundant bits to store encoded information so as to increase large area overhead and increase the chip cost. A purpose of the present invention is to solve the problems in the prior art. The anti-radiation fault-secure method comprises: 1, selecting the EG-LDPC codes and the Hamming codes; 2, dividing the EG-LDPC codes into M parts; 3, uniformly inserting the Hamming codes into the intervals of the M parts; 4, adopting a constraint algorithm to ensure the fault-secure characteristic of the mixed codes. The device has characteristics of low area and delay overhead, and can be applicable for synchronously inhibiting the multiple-bit upsets in the memory array and the single event transient effects in the encoder, the decoder and other combinational circuits.

Description

Anti-radiation fault-secure type memory device and radioresistance fault protecting method thereof

Technical field

The present invention relates to a kind of fault-resistant protection type memory storage and guard method thereof.

Background technology

Along with the continuous reduction of integrated technique size, integrated circuit is to space radiation environment and surface noise environment sensitivity all the more, and the normal operating conditions of circuit is seriously affected.Bug patch code (ECC) is a kind of common method of revising fault in storer.Yet along with the distance of facing mutually between unit in storer is constantly dwindled, one time radiation event causes the probability of multidigit upset to increase widely; Because ECC circuit need to consist of scrambler and code translator, these combinational circuits can be subject to the impact by radiation-induced single-ion transient state effect simultaneously.Therefore, need a kind of storage failure protection (Fault-Secure) reinforcement technique more effectively, both can revise the multi-bit error in storage array, can revise the mistake in ECC circuit again.

Hamming code (Hamming codes) is a kind of error correcting technique the most common in ECC, and it can be revised one, survey two bit-errors.It is simple that Hamming code has coding structure, is easy to the features such as realization, but it cannot revise the mistake more than two.Euclidean geometry low-density single-parity check code (EG-LDPC) is at present known unique ECC coding with emergency protection ability.EG-LDPC code is a kind of of grouping reflected code, and it can revise a plurality of mistakes, has the feature of high code gain and low error rate simultaneously, has been widely used in the communications field.EG-LDPC code or a kind of majority logic decodable code, the iterative decoding mode with respect to other grouping reflected code, has the fast feature of decoding speed.Concrete decoded mode is as follows: the inner product of the data vector first receiving by calculating and the parity matrix of self, obtains α parity checking summation; Then α parity checking summation is input in majority logic door and judges; If the Output rusults of large several is 1, transmit the data corresponding data bit of need to overturning that makes a mistake; If the Output rusults of large several is 0, transmit data correct, remain unchanged.

The emergency protection ability of an ECC coding is by its syndrome (syndrome) S _ithe detector circuit forming determines.Whether the information bit that syndrome detection circuit can be surveyed scrambler, code translator and the output of self circuit is correct, if decoding correctly, syndrome is 0, if there is mistake in decoding, syndrome is not 0.The EG-LDPC code that is n for a word length; it can produce n syndrome; in order to produce detectable signal and to feed back to storer; if there is the mistake that cannot revise in scrambler, code translator or detector; interrupt laying equal stress on newly sending out the data of existing mistake; thereby make storer have emergency protection ability, amendment scheme as shown in Figure 1.

But not all ECC coding all has emergency protection ability.If J is the minor increment (minimum distance) of ECC code, the maximum error correcting capability E that ECC is somebody's turn to do is (J-1)/2, and maximum probe ability D is J-1, and the weight of error pattern (weight) meets 0<e≤J-1.The mistake occurring in scrambler, code translator and correcting circuit is used respectively E _e, E _dand E _smark, the mistake in storage array is E _m.For common ECC code, need to meet E _m≤ E and E _e=E _d=0, for the ECC code with emergency protection ability, need to meet E _e+ E _m≤ E and E _e+ E _m+ E _d+ E _s≤ D.Suppose that in emergency protection ECC, error pattern weight is E _e+ E _m+ E _d=e, the weight that syndrome circuit makes a mistake in can sensing range should meet E _s≤ J-1-e.Guarantee that in syndrome circuit, each mistake only affects a syndrome position, realize wrong detection self is appearred in syndrome circuit, now the weight of syndrome at least needs for J-e.The syndrome weight that has proved at present EG-LDPC code can meet and is greater than J-e, therefore possesses the ability of emergency protection.

Because EG-LDPC code needs more redundant digit, deposit coded message, and storage unit has occupied most areas of whole storer, so the failure protection scheme of EG-LDPC code can bring huge area overhead, increase the cost of chip.In addition, the EG-LDPC of some yard of section needs multistep majority logic to realize decoding, thereby brings excessive delay expense, and is not suitable for the application of some high-speed memory.

Summary of the invention

The multidigit upset occurring in the unresolved existing storage array of the present invention can suppress again the single-ion transient state effect occurring in the combinational circuits such as scrambler, code translator, and existing EG-LDPC code deposits coded message because of the more redundant digit of needs and bring huge area overhead, increase the problem of chip cost; And a kind of Anti-radiation fault-secure type memory device and radioresistance fault protecting method thereof have been proposed.

Anti-radiation fault-secure type memory device, it comprises hybrid code encoding pack and hybrid code translation subassembly; Described hybrid code encoding pack is comprised of EG-LDPC code coding module and Hamming code coding module; The information coding data input pin of EG-LDPC code coding module is connected with external information data output end with the information coding data input pin of Hamming code coding module simultaneously; The EG-LDPC code coded data output terminal of EG-LDPC code coding module is connected with the EG-LDPC code coded data input end of storage array module; The Hamming code coded data output terminal of Hamming code coding module is connected with the Hamming code coded data input end of storage array module; Described hybrid code translation subassembly is comprised of EG-LDPC code decoding module and Hamming code decoding module; The EG-LDPC code decoding data input end of EG-LDPC code decoding module is connected with the EG-LDPC code decoding data output terminal of storage array module; The Hamming code decoding data input end of Hamming code decoding module is connected with the Hamming code decoding data output terminal of storage array module; It also comprises code error code probe assembly and decoding error code probe assembly; Described code error code probe assembly is comprised of EG-LDPC code code error code detecting module and Hamming code code error code detecting module;

The EG-LDPC code code error code detection data input end of described EG-LDPC code code error code detecting module is connected with the EG-LDPC code coded data output terminal of EG-LDPC code coding module; The Hamming code code error code detection data input end of described Hamming code code error code detecting module is connected with the Hamming code coded data output terminal of Hamming code coding module;

Described decoding error code probe assembly is comprised of EG-LDPC code decoding error code detecting module and Hamming code decoding error code detecting module;

The EG-LDPC code decoding error code detection data input end of described EG-LDPC code decoding error code detecting module is connected with the EG-LDPC code decoding data output terminal of EG-LDPC code decoding module; The Hamming code decoding error code detection data input end of described Hamming code decoding error code detecting module is connected with the Hamming code decoding data output terminal of Hamming code decoding module;

The EG-LDPC code decoding companion data input end of described EG-LDPC code decoding error code detecting module simultaneously with EG-LDPC code decoding companion data output terminal, the Hamming code decoding companion data output terminal of Hamming code decoding module and the Hamming code decoding companion data input end of Hamming code decoding error code detecting module of EG-LDPC code decoding module be connected.

The radioresistance fault protecting method that adopts above-mentioned Anti-radiation fault-secure type memory device, it is comprised of following step:

Step 1: reinforce as required the data width N of storer, the Hamming code that the EG-LDPC code that selection code word is (n1, k1) and code word are (n2, k2); Wherein n1 and k1 are respectively code length and the data width of EG-LDPC code, and n2 and k2 are respectively code length and the data width of Hamming code;

Step 2: the EG-LDPC code that the code length that step 1 is selected is n1 is divided into M part, and the value of M equates with the code length n2 of Hamming code, at least 2 of the length of the every part in a described M part;

Step 3: the Hamming code that is n2 code length is inserted in the interval of M the part that EG-LDPC code cuts apart equably, and each byte of Hamming code is separated in physical layout; If the code length of Hamming code and EG-LDPC code and information bit meet equation 1 and 2, forming a data width is N, the hybrid code that code length is n1+n2;

$\frac{n1}{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="HDA0000065954010000012.png"\; state="\{\{state\}\}">n</figure-callout>}2}\&GreaterEqual;2$ Equation 1

K1+k2=N equation 2

Step 4: the emergency protection characteristic of guaranteeing hybrid code by emergency protection bounding algorithm; If the minor increment that J is bug patch code, the weight that e is error pattern, the check matrix to system form

$H_{\mathrm{systematic}}=\left[\begin{array}{cccccccccccccccccccccc}1& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 0& 1& 0& 0& 0& 1& 0& 1& 0\\ 0& 0& 1& 0& 0& 0& 1& 1& 1& 0& 1& 1& 1& 0& 0& 1& 1& 0& 0& 0& 0& 0\\ 0& 0& 0& 1& 0& 0& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 0& 1& 0& 0& 0& 1\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 1& 1\\ 0& 0& 0& 0& 0& 1& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1\end{array}\right]$

Carry out row elementary transformation, obtain having the check matrix H of emergency protection ability _fS;

$H_{\mathrm{FS}}=\left[\begin{array}{cccccccccccccccccccccc}0& 0& 0& 1& 0& 1& 1& 0& 1& 0& 0& 1& 0& 1& 1& 1& 1& 0& 1& 1& 1& 0\\ 0& 1& 1& 1& 1& 1& 0& 1& 1& 0& 0& 1& 1& 0& 1& 1& 0& 0& 0& 0& 1& 1\\ 1& 1& 0& 0& 1& 0& 1& 0& 1& 1& 0& 1& 0& 0& 0& 1& 1& 1& 0& 0& 0& 1\\ 1& 1& 1& 0& 1& 1& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 0& 1& 1& 1& 0\\ 1& 1& 1& 0& 0& 0& 0& 1& 0& 0& 1& 0& 0& 1& 1& 1& 0& 1& 0& 1& 1& 0\\ 0& 1& 0& 1& 0& 0& 1& 1& 0& 1& 1& 1& 1& 1& 0& 1& 0& 1& 1& 0& 1& 1\end{array}\right]$

The described check matrix H with emergency protection ability _fSmeet following condition:

In a, each row, at least comprise J individual 1;

B, emergency protection check matrix H _fSin total number Z of 1 remain between " (J+1) * matrix columns>=Z>=J * matrix columns ";

C, emergency protection check matrix H _fSin in every a line 1 number all equate;

Step 5: the Hamming check matrix H of utilizing EG-LDPC code check matrix and step 4 to obtain _fS, by carrying out the parameter of scrambler that corresponding vector-matrix multiplication obtains hybrid code, the parameter of the parameter of code translator and detector with the data bit receiving and send; The scrambler of described hybrid code, code translator and detector connect and compose Anti-radiation fault-secure type memory device.

Anti-radiation fault-secure type memory device of the present invention has low area and postpones the characteristic of expense, is applicable to suppress the single-ion transient state effect in the combinational circuits such as multidigit upset in storage array and scrambler, code translator simultaneously.

Accompanying drawing explanation

Fig. 1 is the failure protecting device structural representation of ECC coding; Fig. 2 is modular structure schematic diagram of the present invention; Fig. 3 mixes the structure of code word described in embodiment two in method, wherein M represents Hamming code, and E represents EG-LDPC code, and A represents the error span, and B represents the length of every part.

Embodiment

Embodiment one: in conjunction with Fig. 2, present embodiment is described, the Anti-radiation fault-secure type memory device described in present embodiment, it comprises hybrid code encoding pack 2 and hybrid code translation subassembly 3; Described hybrid code encoding pack 2 is comprised of EG-LDPC code coding module 2-1 and Hamming code coding module 2-2; The information coding data input pin of EG-LDPC code coding module 2-1 is connected with external information data output end with the information coding data input pin of Hamming code coding module 2-2 simultaneously; The EG-LDPC code coded data output terminal of EG-LDPC code coding module 2-1 is connected with the EG-LDPC code coded data input end of storage array module 1; The Hamming code coded data output terminal of Hamming code coding module 2-2 is connected with the Hamming code coded data input end of storage array module 1; Described hybrid code translation subassembly 3 is comprised of EG-LDPC code decoding module 3-1 and Hamming code decoding module 3-2; The EG-LDPC code decoding data input end of EG-LDPC code decoding module 3-1 is connected with the EG-LDPC code decoding data output terminal of storage array module 1; The Hamming code decoding data input end of Hamming code decoding module 3-2 is connected with the Hamming code decoding data output terminal of storage array module 1; It also comprises code error code probe assembly 4 and decoding error code probe assembly 5; Described code error code probe assembly 4 is comprised of EG-LDPC code code error code detecting module 4-1 and Hamming code code error code detecting module 4-2;

The EG-LDPC code code error code detection data input end of described EG-LDPC code code error code detecting module 4-1 is connected with the EG-LDPC code coded data output terminal of EG-LDPC code coding module 2-1; The Hamming code code error code detection data input end of described Hamming code code error code detecting module 4-2 is connected with the Hamming code coded data output terminal of Hamming code coding module 2-2;

Described decoding error code probe assembly 5 is comprised of EG-LDPC code decoding error code detecting module 5-1 and Hamming code decoding error code detecting module 5-2;

The EG-LDPC code decoding error code detection data input end of described EG-LDPC code decoding error code detecting module 5-1 is connected with the EG-LDPC code decoding data output terminal of EG-LDPC code decoding module 3-1; The Hamming code decoding error code detection data input end of described Hamming code decoding error code detecting module 5-2 is connected with the Hamming code decoding data output terminal of Hamming code decoding module 3-2;

The EG-LDPC code decoding companion data input end of described EG-LDPC code decoding error code detecting module 5-1 simultaneously with the EG-LDPC code decoding companion data output terminal of EG-LDPC code decoding module 3-1, the Hamming code decoding companion data input end of the Hamming code decoding companion data output terminal of Hamming code decoding module 3-2 and Hamming code decoding error code detecting module 5-2 be connected.Described EG-LDPC code is euclidean geometry low-density single-parity check code.

Anti-radiation fault-secure type memory device principle of work is as follows: data deposit in storage array module 1 by hybrid code encoding pack 2; if radiation event affects a plurality of data bit in storage array module 1; the state of data is changed; data, in reading the process of storage array module 1, can be revised these data by hybrid code translation subassembly 3 so.If mistake appears in hybrid code encoding pack 2, hybrid code translation subassembly 3, code error code probe assembly 4 and decoding error code probe assembly 5, can detect and correct mistakes thereupon by code error code probe assembly 4 and decoding error code probe assembly 5 so.Anti-radiation fault-secure type memory device of the present invention has low area and postpones the characteristic of expense, is applicable to suppress the single-ion transient state effect in the combinational circuits such as multidigit upset in storage array and scrambler, code translator simultaneously.

Embodiment two: the radioresistance fault protecting method of the Anti-radiation fault-secure type memory device described in employing embodiment one, it is comprised of following step:

Step 1: reinforce as required the data width N of storer, the Hamming code that the EG-LDPC code that selection code word is (n1, k1) and code word are (n2, k2); Wherein n1 and k1 are respectively code length and the data width of EG-LDPC code, and n2 and k2 are respectively code length and the data width of Hamming code;

Step 2: the EG-LDPC code that the code length that step 1 is selected is n1 is divided into M part, and the value of M equates with the code length n2 of Hamming code, at least 2 of the length of the every part in a described M part;

Step 3: the Hamming code that is n2 code length is inserted in the interval of M the part that EG-LDPC code cuts apart equably, and each byte of Hamming code is separated in physical layout; If the code length of Hamming code and EG-LDPC code and information bit meet equation 1 and 2, forming a data width is N, the hybrid code that code length is n1+n2;

$\frac{n1}{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="HDA0000065954010000012.png"\; state="\{\{state\}\}">n</figure-callout>}2}\&GreaterEqual;2$ Inequality 1

K1+k2=N equation 2

Step 4: the emergency protection characteristic of guaranteeing hybrid code by emergency protection bounding algorithm; If the minor increment that J is bug patch code, the weight that e is error pattern, the check matrix to system form

$H_{\mathrm{systematic}}=\left[\begin{array}{cccccccccccccccccccccc}1& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 0& 1& 0& 0& 0& 1& 0& 1& 0\\ 0& 0& 1& 0& 0& 0& 1& 1& 1& 0& 1& 1& 1& 0& 0& 1& 1& 0& 0& 0& 0& 0\\ 0& 0& 0& 1& 0& 0& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 0& 1& 0& 0& 0& 1\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 1& 1\\ 0& 0& 0& 0& 0& 1& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1\end{array}\right]$

Carry out row elementary transformation, obtain having the check matrix H of emergency protection ability _fs;

$H_{\mathrm{FS}}=\left[\begin{array}{cccccccccccccccccccccc}0& 0& 0& 1& 0& 1& 1& 0& 1& 0& 0& 1& 0& 1& 1& 1& 1& 0& 1& 1& 1& 0\\ 0& 1& 1& 1& 1& 1& 0& 1& 1& 0& 0& 1& 1& 0& 1& 1& 0& 0& 0& 0& 1& 1\\ 1& 1& 0& 0& 1& 0& 1& 0& 1& 1& 0& 1& 0& 0& 0& 1& 1& 1& 0& 0& 0& 1\\ 1& 1& 1& 0& 1& 1& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 0& 1& 1& 1& 0\\ 1& 1& 1& 0& 0& 0& 0& 1& 0& 0& 1& 0& 0& 1& 1& 1& 0& 1& 0& 1& 1& 0\\ 0& 1& 0& 1& 0& 0& 1& 1& 0& 1& 1& 1& 1& 1& 0& 1& 0& 1& 1& 0& 1& 1\end{array}\right]$

The described check matrix H with emergency protection ability _fsmeet following condition:

In a, each row, at least comprise J individual 1;

B, emergency protection check matrix H _fsin total number Z of 1 remain between " (J+1) * matrix columns>=Z>=J * matrix columns ";

C, emergency protection check matrix H _fsin in every a line 1 number all equate;

Step 6: the Hamming check matrix H of utilizing EG-LDPC code check matrix and step 5 to obtain _fs, by carrying out with the data bit receiving and send scrambler, code translator and the detector that corresponding vector-matrix multiplication obtains hybrid code; The scrambler of described hybrid code, code translator and detector connect and compose Anti-radiation fault-secure type memory device.

Object: hybrid code scrambler is encoded to data writing, the data after coding deposit in storer.Hybrid code code translator carries out decoding to the data of readout memory, if radiation event affects a plurality of data bit in storer, the state of data is changed, and can revise these multidigits so overturn by hybrid code code translator.The single-particle inversion occurring in scrambler, code translator and detector can be surveyed and be revised thereupon to hybrid code detector.

The emergency protection reservoir system that the hybrid code obtaining by said method forms has low area and postpones the characteristic of expense, is applicable to suppress the single-ion transient state effect in the combinational circuits such as multidigit upset in storage array and scrambler, code translator simultaneously.

Embodiment three: present embodiment and embodiment two differences are a code word to be defined as the form of (n, k, t), and wherein n is code length, and k is information bit, and t represents error correcting capability.EG-LDPC code can provide stronger error correcting capability to normally used data bit in storage array module 1, but need to, by double redundancy and multistep realization of decoding, can bring excessive area and postpone expense whole storage array module 1.In addition, too high error correction ability (for example 15) is unwanted to common radiation environment.The Scheme of Strengthening of hybrid code

EG-LDPC code	(127,64,7)	(208,128,8)	(511,256,15)	(754,512,16)
					The EG-LDPC code merging	(63,48,2)	(127,99,3)	(255,231,2)	(511,448,4)
Hamming code	(21,16,1)	(35,29,1)	(30,25,1)	(71,64,1)
					Hybrid code	(84,64,2)	(162,128,3)	(285,256,2)	(582,512,4)
Redundant digit reduces	68%	58%	89%	71%
					Decoding procedure reduces	2 steps	0 step	3 steps	0 step

The Scheme of Strengthening contrast of the Scheme of Strengthening of hybrid code and EG-LDPC code as shown in Table I.The Scheme of Strengthening of the first behavior EG-LDPC code in table, second and third row is respectively low weight or less EG-LDPC code and the corresponding Hamming code of decoding progression of choosing, and the third line is hybrid code Scheme of Strengthening.From Table I, can see, the Scheme of Strengthening redundant digit of hybrid code and decoding procedure all have reduction significantly.Other composition and connected mode are identical with embodiment two.

Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For this person of an ordinary skill in the technical field, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to the definite scope of patent protection of claims that the present invention submits to.

Claims (2)

1. Anti-radiation fault-secure type memory device, is characterized in that it comprises hybrid code encoding pack (2) and hybrid code translation subassembly (3); Described hybrid code encoding pack (2) is comprised of EG-LDPC code coding module (2-1) and Hamming code coding module (2-2); The information coding data input pin of the information coding data input pin of EG-LDPC code coding module (2-1) and Hamming code coding module (2-2) is connected with external information data output end simultaneously; The EG-LDPC code coded data output terminal of EG-LDPC code coding module (2-1) is connected with the EG-LDPC code coded data input end of storage array module (1); The Hamming code coded data output terminal of Hamming code coding module (2-2) is connected with the Hamming code coded data input end of storage array module (1); Described hybrid code translation subassembly (3) is comprised of EG-LDPC code decoding module (3-1) and Hamming code decoding module (3-2); The EG-LDPC code decoding data input end of EG-LDPC code decoding module (3-1) is connected with the EG-LDPC code decoding data output terminal of storage array module (1); The Hamming code decoding data input end of Hamming code decoding module (3-2) is connected with the Hamming code decoding data output terminal of storage array module (1); Described memory storage also comprises code error code probe assembly (4) and decoding error code probe assembly (5); Described code error code probe assembly (4) is comprised of EG-LDPC code code error code detecting module (4-1) and Hamming code code error code detecting module (4-2);

The EG-LDPC code code error code detection data input end of described EG-LDPC code code error code detecting module (4-1) is connected with the EG-LDPC code coded data output terminal of EG-LDPC code coding module (2-1); The Hamming code code error code detection data input end of described Hamming code code error code detecting module (4-2) is connected with the Hamming code coded data output terminal of Hamming code coding module (2-2);

Described decoding error code probe assembly (5) is comprised of EG-LDPC code decoding error code detecting module (5-1) and Hamming code decoding error code detecting module (5-2);

The EG-LDPC code decoding error code detection data input end of described EG-LDPC code decoding error code detecting module (5-1) is connected with the EG-LDPC code decoding data output terminal of EG-LDPC code decoding module (3-1); The Hamming code decoding error code detection data input end of described Hamming code decoding error code detecting module (5-2) is connected with the Hamming code decoding data output terminal of Hamming code decoding module (3-2);

The EG-LDPC code decoding companion data input end of described EG-LDPC code decoding error code detecting module (5-1) simultaneously with EG-LDPC code decoding companion data output terminal, the Hamming code decoding companion data output terminal of Hamming code decoding module (3-2) and the Hamming code decoding companion data input end of Hamming code decoding error code detecting module (5-2) of EG-LDPC code decoding module (3-1) be connected.

2. adopt the radioresistance fault protecting method of Anti-radiation fault-secure type memory device claimed in claim 1, it is characterized in that it is comprised of following step:

Step 1: reinforce as required the data width N of storer, the Hamming code that the EG-LDPC code that selection code word is (n1, k1) and code word are (n2, k2); Wherein n1 and k1 are respectively code length and the data width of EG-LDPC code, and n2 and k2 are respectively code length and the data width of Hamming code;

Step 2: the EG-LDPC code that the code length that step 1 is selected is n1 is divided into M part, and the value of M equates with the code length n2 of Hamming code, at least 2 of the length of the every part in a described M part;

Step 3: the Hamming code that is n2 code length is inserted in the interval of M the part that EG-LDPC code cuts apart equably, and each byte of Hamming code is separated in physical layout; If the code length of Hamming code and EG-LDPC code and information bit meet equation 1 and 2, forming a data width is N, the hybrid code that code length is n1+n2;

$\frac{n1}{n2}\&GreaterEqual;2$ Inequality 1

K1+k2=N equation 2

Step 4: the emergency protection characteristic of guaranteeing hybrid code by emergency protection bounding algorithm; If the minor increment that J is bug patch code, the weight that e is error pattern, the check matrix to system form

$H_{\mathrm{systematic}}=\left[\begin{array}{cccccccccccccccccccccc}1& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 0& 1& 0& 0& 0& 1& 0& 1& 0\\ 0& 0& 1& 0& 0& 0& 1& 1& 1& 0& 1& 1& 1& 0& 0& 1& 1& 0& 0& 0& 0& 0\\ 0& 0& 0& 1& 0& 0& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 0& 1& 0& 0& 0& 1\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 1& 1\\ 0& 0& 0& 0& 0& 1& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1\end{array}\right]$

Carry out row elementary transformation, obtain having the check matrix H of emergency protection ability _fS;

$H_{\mathrm{FS}}=\left[\begin{array}{cccccccccccccccccccccc}0& 0& 0& 1& 0& 1& 1& 0& 1& 0& 0& 1& 0& 1& 1& 1& 1& 0& 1& 1& 1& 0\\ 0& 1& 1& 1& 1& 1& 0& 1& 1& 0& 0& 1& 1& 0& 1& 1& 0& 0& 0& 0& 1& 1\\ 1& 1& 0& 0& 1& 0& 1& 0& 1& 1& 0& 1& 0& 0& 0& 1& 1& 1& 0& 0& 0& 1\\ 1& 1& 1& 0& 1& 1& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 0& 1& 1& 1& 0\\ 1& 1& 1& 0& 0& 0& 0& 1& 0& 0& 1& 0& 0& 1& 1& 1& 0& 1& 0& 1& 1& 0\\ 0& 1& 0& 1& 0& 0& 1& 1& 0& 1& 1& 1& 1& 1& 0& 1& 0& 1& 1& 0& 1& 1\end{array}\right]$

The described check matrix H with emergency protection ability _fSmeet following condition:

In a, each row, at least comprise J individual 1;

B, emergency protection check matrix H _fSin total number Z of 1 remain between " (J+1) * matrix columns>=Z>=J * matrix columns ";

C, emergency protection check matrix H _fSin in every a line 1 number all equate;

Step 5: the Hamming check matrix H of utilizing EG-LDPC code check matrix and step 4 to obtain _fS, by carrying out with the data bit receiving and send scrambler, code translator and the detector that corresponding vector-matrix multiplication obtains hybrid code; The scrambler of described hybrid code, code translator and detector connect and compose Anti-radiation fault-secure type memory device.

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