CN102298914B

CN102298914B - Liquid crystal indicator, its driving method and electronic equipment

Info

Publication number: CN102298914B
Application number: CN201110164468.0A
Authority: CN
Inventors: 寺西康幸
Original assignee: Japan Display Central Inc
Current assignee: Japan Display Central Inc
Priority date: 2010-06-24
Filing date: 2011-06-17
Publication date: 2016-12-14
Anticipated expiration: 2031-06-17

Abstract

The invention discloses liquid crystal indicator, its driving method and electronic equipment.A kind of liquid crystal indicator, including: for each pixel, the first switch element, the multiple sub-pixels for one pixel of composition are arranged jointly, and the first switch element makes its one end be connected to holding wire；For each pixel, multiple second switch elements, one second switch element is set for each sub-pixel, between each pixel electrode being connected to one of multiple sub-pixel and the other end of the first switch element in multiple second switch elements；And drive division, be suitable to sequentially switch on and off in section in the turn-on time of the first switch element multiple second switch element, and first disconnect the last second switch element connected in order, be then turned off the first switch element.

Description

Liquid crystal indicator, its driving method and electronic equipment

Technical field

The present invention relates to liquid crystal indicator, its driving method and electronic equipment, and more particularly, to using institute The liquid crystal indicator of selector driving method, its driving method and there is the electronics of this liquid crystal indicator in the pixel of meaning Equipment.

Background technology

Some liquid crystal indicators use selector driving method in so-called pixel.This driving method is arranged by use Selector portion within the pixel and the signal potential of reflection gray level is sequentially write the many height picture constituting pixel (main pixel) Element.This signal potential is provided via the holding wire arranged for each pixel.Hereinafter may be used in the selector portion within the pixel that arranges To be referred to as " selector portion in pixel ".

In employing pixel, the liquid crystal indicator of selector driving method includes the first switch element for each pixel With second switch element.For multiple sub-pixels, the first switch element is set jointly.One is arranged for each in multiple sub-pixels Second switch element (for example, with reference to Japanese Patent Publication the 2009-98234th).First switch element makes its one end be connected to Holding wire.Each second switch element is both connected to the pixel electricity of in multiple sub-pixel (more specifically, liquid crystal capacitance) Between the other end of pole and the first switch element.

In pixel, selector portion includes the first switch element and multiple second switch element.In pixel in selector portion, Multiple second switch elements sequentially switched on and off within the first switching elements ON time period, thus allowed via holding wire Signal potential that provide, reflection gray level sequentially writes multiple sub-pixel.

Here, in order to ensure signal potential is reliably written multiple sub-pixel by selector portion in pixel, it is proposed that protect Stay the period for signal potential being write multiple sub-pixel that (setting) is long as far as possible.In order to accomplish this point, unavoidably Make section turn-on time of the first switch element maximum.

In order to section turn-on time making the first switch element is maximum, while the first switch element disconnects, all second The second switch element finally switched on and off in switch element disconnects.This is section quilt turn-on time due to the first switch element Equalization is divided into section turn-on time of multiple second switch element.

Summary of the invention

Incidentally, between control electrode and the distribution of switch element, it is usually present parasitic capacitance.So, when multiple When two switch elements disconnect after signal potential being write capacity cell, the signal potential in capacity cell is owing to posting Give birth to Capacitance Coupled (Capacitance Coupled) and slightly change.

Now, if as it has been described above, last second switch element and the first switch element are changed into from connection simultaneously Disconnect, then the coupled level caused due to the parasitic capacitance of two switch elements is in the sub-pixel being ultimately written signal potential It is about twice big.I.e., finally it is written into the coupled level of the sub-pixel of signal potential and the sub-pixel of previous write signal current potential Different.In other words, the condition affecting sub-pixel caused due to parasitic capacitance coupling is different between multiple sub-pixels.

Here, it is contemplated that multiple sub-pixel is red (R), green (R) and the situation of blue (B) pixel.In this situation Under, if owing to parasitic capacitance and the coupling condition (coupled level) of switch element that causes is different between multiple sub-pixels, The color of the sub-pixel being then ultimately written signal potential changes than other color sub-pixels relative to the signal potential originally wanted More, thus cause the imbalance between color.

In accordance with the above, it is desirable to provide a kind of liquid crystal indicator, wherein, due to by the control electrode of switch element The coupling of parasitic capacitance at place and the condition affecting multiple sub-pixels that causes is identical for sub-pixel, and expect to carry Supply the driving method of this liquid crystal indicator and there is the electronic equipment of this liquid crystal indicator.

According to the embodiment of the present invention, it is provided that a kind of liquid crystal indicator.This liquid crystal indicator includes, for each Pixel, the first switch element and multiple second switch element.First switch element is multiple sub-pixels of one pixel of composition Common setting.First switch element makes its one end be connected to holding wire.For each sub-pixel, one second switch element is set.Many Each pixel electrode being connected to one of multiple sub-pixel in individual second switch element and the other end of the first switch element it Between.

Multiple second switch element is sequentially switched on and off in section in the turn-on time of the first switch element.Additionally, first Disconnect the last second switch element connected in order, hereafter disconnect the first switch element.

As mentioned above and in the liquid crystal indicator constructed, when multiple second switch element connecing at the first switch element When sequentially switching on and off in the logical time period, first last last second switch element connected disconnects, hereafter in order First switch element disconnects.Here, " first last second switch element disconnects, and hereafter breaks at the first switch element in expression Open " to refer to the first switch element and last second switch element separated when different.Therefore, following feelings are also included Condition, i.e. after last second switch element disconnects, the first switch element disconnected within the given time period.

Therefore, the first switch element disconnects after last second switch element disconnects.As a result, the first switch element With last second switch element when different separated.That is, multiple second switch element connecing at the first switch element Sequentially switch on and off in the logical time period.As a result, in turn-off time of any one second switch element in section, by switch unit The condition of the coupling of the parasitic capacitance at the control electrode of part is identical for multiple sub-pixels.

Present invention ensures that when using selector driving method in pixel due at by the control electrode of switch element The coupling of parasitic capacitance and the condition affecting multiple sub-pixels that causes is identical for sub-pixel.

Accompanying drawing explanation

Fig. 1 shows the system structural map of the outline of the structure of the active matrix liquid crystal display apparatus of the application present invention；

Fig. 2 shows the sectional view of the example of the cross section structure of display panels (liquid crystal indicator)；

Fig. 3 shows and uses the circuit diagram of the essential structure example of the image element circuit of selector driving method in pixel；

Fig. 4 A to Fig. 4 H shows the sequential of the maximum sequential relationship of section turn-on time for making the first switch element Oscillogram；

Fig. 5 shows the structure example of the pixel of the active matrix liquid crystal display apparatus according to embodiment of the present invention Circuit diagram；

Fig. 6 A to Fig. 6 H be for describe according to the operation of the image element circuit in the liquid crystal indicator of embodiment time Sequence oscillogram；

Fig. 7 shows the circuit diagram of the image element circuit according to example 1；

Fig. 8 A to Fig. 8 F is the sequential ripple for describing the operation under analog information pattern of the image element circuit according to example 1 Shape figure；

Fig. 9 A to Fig. 9 H is the refreshing performed under memory display mode by the image element circuit according to example 1 for description The timing waveform of operation；

Figure 10 A to Figure 10 D is for describing according to the scan line in the image element circuit of example 1 under memory display mode The timing waveform of operation；

Figure 11 shows the circuit diagram of the image element circuit according to example 2；

Figure 12 A to Figure 12 G is the sequential for describing the operation under analog information pattern of the image element circuit according to example 2 Oscillogram；

Figure 13 A to Figure 13 I is for describing the refresh operation under memory display mode of the image element circuit according to example 2 Timing waveform；

Figure 14 A to Figure 14 E is that the scan line for describing the image element circuit according to example 2 is under memory display mode The timing waveform of operation；

Figure 15 shows the perspective view of the outward appearance of the television set of the application present invention；

Figure 16 A and Figure 16 B shows the perspective view of the outward appearance of the digital camera of the application present invention, and Figure 16 A is From the perspective view above watched, Figure 16 B is the perspective view watched from behind；

Figure 17 shows the perspective view of the outward appearance of the laptop PC of the application present invention；

Figure 18 shows the perspective view of the outward appearance of the video camera of the application present invention；And

Figure 19 A to Figure 19 G is the outside drawing of mobile phone of the application present invention, and Figure 19 A is facing in the on-state Figure, Figure 19 B is its side view, and Figure 19 C is front view in closed state, and Figure 19 D is left view, and Figure 19 E is right view, figure 19F is top view, and Figure 19 G is look up figure.

Detailed description of the invention

The pattern (hereinafter, referred to embodiment) implementing the present invention is described below with reference to the accompanying drawings.It should be noted that, will be by Following order is described.

1. apply the liquid crystal indicator of the present invention

1-1. system constructs

The cross section structure of 1-2 panel

Selector driving method in 1-3. pixel

2. according to the description of the liquid crystal indicator of embodiment

2-1. example 1 (using the example of inverter circuit)

2-2. example 2 (using the example of latch cicuit)

3. variation

4. application examples (electronic equipment)

1. apply the liquid crystal indicator of the present invention

1-1. system constructs

Fig. 1 shows the system structural map of the outline of the structure of the active matrix liquid crystal display apparatus of the application present invention. Liquid crystal indicator has two pieces of substrate (not shown), and wherein, at least one piece is transparent.Two pieces of substrates are configured to phase each other Right, there is predetermined interval therebetween.By sealing liquid crystal between two pieces of substrates.

Liquid crystal indicator 10 according to this application examples includes multiple pixel 20, pixel array unit 30 and drive division.Multiple Pixel 20 each has liquid crystal capacitance.Pixel array unit 30 includes the pixel 20 arranged with two-dimensional matrix.Drive division quilt It is arranged on pixel array unit 30 around, and such as includes that holding wire drive division 40, control line drive division 50 and driver' s timing generate Portion 60.Drive division is such as integrated in pixel array unit 30 identical substrate (display panels 10_AOn), to drive pel array The pixel 20 in portion 30.

Here, if liquid crystal indicator 10 can carry out colored display, the most each pixel all include therein each Multiple sub-pixels corresponding to pixel 20.More specifically, each pixel in liquid crystal indicator all includes three sub-pixels, or Person is suitable to launch the sub-pixel of red (R) light, be suitable to launch another sub-pixel of green (G) light and be suitable to launch the another of blue (B) light One sub-pixel.

It should be noted, however, that the combination of sub-pixel is not limited to be suitable to launch three kinds of primary colours (that is, red, green and blue) The combination of sub-pixel of light.On the contrary, each pixel is in addition to including the sub-pixel being suitable to launch the light of three kinds of primary colours, it is also possible to Including being suitable to launch the one or more other sub-pixel of different colours.More specifically, for example, it is possible to add and be suitable to launch in vain The sub-pixel of light, to improve brightness.It is alternatively possible to interpolation complementary color, to expand color gamut.

In FIG, in pixel array unit 30, on the column direction of the pixel arranged with m row n row, for each column pixel, It is provided with holding wire 31₁To 31_n(holding wire 31 can be expressed simply as).Additionally, for often row pixel, be provided with control line 32₁To 32_m(control line 32 can be expressed simply as).Here, term " column direction " refers to the pixel being provided with in pixel column Direction (that is, vertical direction), and term " line direction " refers to (that is, the level side, direction of the pixel being provided with in pixel column To).

Holding wire 31₁To 31_nIn every make its one end be connected to be associated with the holding wire discussed holding wire drive One outfan in portion 40.Holding wire drive division 40 will reflect the signal potential V of any gray level_sigOutput is to the letter being associated Number line 31.

Although as shown in the single line in Fig. 1, but control line 32₁To 32_mIt is not limited to single line.It practice, control line 32₁To 32_m In every all include a plurality of distribution.Control line 32₁To 32_mIn every control line phase making its one end be connected to and be discussed One outfan of the control line drive division 50 of association.Control line drive division 50 controls to export to signal from holding wire drive division 40 Line 31₁To 31_nThe signal potential V of reflection gray level_sig, write to pixel 20.

Various driving pulses (clock signal) are supplied to holding wire and drive by driver' s timing generating unit (TG: timing generator) 60 Dynamic portion 40 and control line drive division 50, to drive these drive divisions 40 and 50.

The cross section structure of 1-2. panel

Fig. 2 shows the sectional view of the example of the cross section structure of display panels (liquid crystal indicator).Such as Fig. 2 institute Show, display panels 10_AIncluding two pieces of glass substrates 11 and 12 and liquid crystal layer 13.Glass substrate 11 and 12 is set to that This is relative, has predetermined interval therebetween.Liquid crystal layer 13 is sealed between glass substrate 11 and 12.

Polarizer 14 is arranged on the outer surface of one piece of glass substrate (or substrate 11), and alignment film 15 sets within it side On surface.Similarly, polarizer 16 is arranged on the outer surface of another glass substrate (or substrate 12), and alignment film 17 is arranged on On its inner surface.The liquid crystal molecule group being configured such that in liquid crystal display layer 13 by alignment film 15 and 17 is the most right Together.

On another glass substrate 12, pixel electrode 18 and counter electrode 19 is formed with nesa coating.At this structure example In, pixel electrode 18 such as has five electrode branches 18 of comb shape_A, wherein electrode branch 18_ATwo ends all pass through connecting portion (not shown) and link together.On the other hand, counter electrode 19 is to cover the form in the whole region of pixel array unit 30, shape Become at electrode branch 18_ALower section (glass substrate 12 side).

Due to the electrode structure formed with the pixel electrode 18 of comb shape and counter electrode 19, at electrode branch 18_AWith right Radial electric field is created between electrode 19.This also allows for electric field also having an impact the upside of pixel electrode 18.As a result, may be used So that the liquid crystal molecule group in liquid crystal layer 13 aligns in the desired orientation in the whole region of pixel array unit 30.

Selector driving method in 1-3. pixel

Construct as mentioned above according to the liquid crystal indicator 10 of use-case have employed selector driving side in pixel Method.As described earlier, the signal potential of reflection gray level is write by identical method by selector portion in use pixel Enter to form multiple sub-pixels of pixel (main pixel).Signal potential is provided via the holding wire arranged for each pixel.

Fig. 1 shows a kind of fundamental system structure, where it is assumed that each pixel 20 is sub-pixel, sets for each sub-pixel Put holding wire 31.On the contrary, if using selector driving method in pixel, then include being suitable to launch three kinds of bases when each main pixel The sub-pixel 20 of the light of color (that is, redness (R), green (G) and blue (B))_R、20_GWith 20_BTime, set for each pixel (main pixel) Put holding wire 31.

Fig. 3 shows and uses the circuit diagram of the essential structure example of the image element circuit of selector driving method in pixel. In figure 3, identical with the parts shown in Fig. 1 parts are represented by identical reference marks.In figure 3, pixel 20 (pixel electricity Road) such as include red sub-pixel 20_R, green sub-pixels 20_GWith blue subpixels 20_B。

Red sub-pixel 20_RIncluding liquid crystal capacitance 21_RWith capacity cell 22_R.Liquid crystal capacitance 21_RRefer at pixel electricity Pole (pixel electrode 18 corresponding in Fig. 2) with for each pixel to be formed as the counter electrode relative with pixel electrode (right Should be in the counter electrode 19 in Fig. 2) between produce electric capacity.For all pixels, by common electric potential V_COMApply to liquid crystal capacitance 21_RCounter electrode.Liquid crystal capacitance 21_RPixel electrode be electrically connected to capacity cell 22_RAn electrode.

Capacity cell 22_RKeep the letter from the reflection gray level of holding wire 31 write by write operation as described below Number current potential V_sig.Capacity cell 22_RHereinafter will be indicated as holding capacitor 22_R.It is used as (by holding capacitor 22_RKeep) signal The current potential Vcs (hereinafter, being expressed as CS current potential) of the benchmark of current potential applies to holding capacitor 22_RAnother electrode.CS current potential V_CS Substantially with common electric potential V_COMCurrent potential identical.

Similarly, green sub-pixel 20_GIncluding liquid crystal capacitance 21_GWith capacity cell 22_G.Blue sub-pixel 20_BIncluding Liquid crystal capacitance 21_BWith capacity cell 22_B.Liquid crystal capacitance 21_GWith holding capacitor 22_G, and liquid crystal capacitance 21_BWith holding capacitor 22_B With substantially with sub-pixel 20_RIn the identical mode of corresponding component connect.

Including sub-pixel 20_R、20_GWith 20_BPixel 20 in, selector portion (selector portion in pixel) 23 is set, with will The signal potential V of reflection gray level_sigSequentially write sub-pixel 20_R、20_GWith 20_B.Signal potential V is provided via holding wire 31_sig。

Selector portion 23 includes the first switch element 231 and three second switch elements 232_R、232_GWith 232_B.For sub-picture Element 20_R、20_GWith 20_BFirst switch element 231 is set jointly.It is respectively sub-pixel 20_R、20_GWith 20_BSecond switch element is set 232_R、232_GWith 232_B。

First switch element 231 makes its one end be connected to holding wire 31, and as the signal potential V of reflection gray level_sigWrite Enter holding capacitor 22_R、22_GWith 22_BTime connect (become Guan Bi).Signal potential V is provided via holding wire 31_sig.That is, the first switch Element 231 is connected, with by signal potential V_sigWrite (loading) pixel 20.By control signal GATE₁Control the first switch element 231 switch on and off.

Second switch element 232_R、232_GWith 232_BIn the other end being each connected to the first switch element 231 and phase Sub-pixel (that is, the sub-pixel 20 of association_R、20_GWith 20_BIn one) pixel electrode (more specifically, liquid crystal capacitance 21R, 21G And 21B) between.That is, second switch element 232_R、232_GWith 232_BIn its one end that each makes be commonly connected to the first switch The other end of element 231, and make its other end be connected to associated pixel (that is, sub-pixel 20_R、20_GWith 20_BOne) picture Element electrode.

Signal potential V when reflection gray level_sigHolding capacitor (that is, the holding capacitor 22 that write is associated_R、22_GWith 22_B In one) time, second switch element 232_R、232_GWith 232_BIn each connection.That is, second switch element 232_R、232_G With 232_BIn each connection, with the signal potential V that will be loaded by the first switch element 231_sigThe holding electricity that write is associated Hold (that is, holding capacitor 22_R、22_GWith 22_BIn one).By control signal GATE_2R、GATE_2GAnd GATE_2BControl second to open Close element 232_R、232_GWith 232_BSwitch on and off.

As it has been described above, be arranged in the pixel of the selector 23 in pixel 20 in selector driving method using, it is only necessary to Single signal line 31 is set for each pixel 20, i.e. for sub-pixel 20_R、20_GWith 20_BCommon setting, thus it is suitable to contribute to ratio In arranging many signal line 31 (for each sub-pixel 20_R、20_GWith 20_BArrange one) distribution structure simpler distribution knot Structure.

Here, in order to ensure by signal potential V_sigIt is reliably written sub-pixel 20_R、20_GWith 20_B, it is proposed that retain (setting) Long as far as possible is used for signal potential V_sigWrite sub-pixel 20_R、20_GWith 20_BTime period.In order to retain use long as far as possible In write signal current potential V_sigTime period, section turn-on time inevitably making the first switch element 231 is maximum.

In order to section turn-on time making the first switch element 231 is maximum, while the first switch element 231 disconnects, institute There is second switch element 232_R、232_GOr 232_BIn the second switch element that finally switches on and off disconnect.It is assumed that such as, second Switch element 232_R、232_GOr 232_BConnect in turn with this and disconnect, last switch element 232_BAt the first switch element Disconnect while 231 disconnections.

Fig. 4 A to Fig. 4 H show the maximum sequential relationship of section turn-on time for making the first switch element 231 time Sequence oscillogram.

Fig. 4 A to Fig. 4 E respectively illustrates the current potential V of holding wire 31_sigWith control signal GATE₁、GATE_2R、GATE_2GWith GATE_2BWaveform.Additionally, Fig. 4 F and Fig. 4 H respectively illustrates by holding capacitor 22_R、22_GWith 22_BThe current potential PIX kept_R、 PIX_GAnd PIX_BWaveform.

As shown in Fig. 4 A to Fig. 4 H, section turn-on time in order to ensure the first switch element 231 is maximum, it is only necessary to divide control Signal GATE processed₁Activationary time section (being the high time period in this example), control signal GATE₁Be suitable at sub-pixel 20_R、20_G With 20_BBetween control switching on and off of the first switch element equably, i.e. activationary time section is divided into three equal portions Point.By by control signal GATE₁Activationary time section be divided into three moieties, in control signal GATE₁Be converted to non-sharp While the state of living, be suitable to control last switch element 232_BSwitch on and off and control signal GATE_2BIt is changed into non- State of activation.

Incidentally, between control electrode and the distribution of switch element, it is usually present parasitic capacitance.Such as MOS transistor Electrical switch be often used as switch element.Such as, if MOS transistor is used as the first switch element 231 and second switch Element 232_R、232_GWith 232_B, then the gate electrode of MOS transistor is used as the control electrode of switch element.Therefore, brilliant at each MOS Parasitic capacitance is there is between gate electrode and the distribution being electrically connected to regions and source/drain of body pipe.

At second switch element 232_R、232_GWith 232_BControl electrode at when there is parasitic capacitance, by signal electricity Position V_sigWrite holding capacitor 22_R、22_GWith 22_BAfterwards, at switch element 232_R、232_GWith 232_BElectric capacity coupling is produced while disconnection Close.Then, current potential is sent to holding capacitor 22 by this parasitic couplings_R、22_GWith 22_B, thus change respectively by holding capacitor 22_R、 22_GWith 22_BThe current potential PIX kept_R、PIX_GAnd PIX_B。

More specifically, from Fig. 4 A to Fig. 4 H it is readily apparent that the second switch element 232 previously switched on and off_RWith 232_GWhen disconnecting different from the first switch element 231 separated.Therefore, respectively by holding capacitor 22_RWith 22_GKeep Current potential PIX_RAnd PIX_GSlightly decline, i.e. have dropped Δ V1.Current potential Δ V1 now passes through second switch element 232_RWith 232_G's The parasitic capacitance controlling to exist at electrode determines.

On the other hand, the second switch element 232 finally switched on and off_BWhile the first switch element 232 disconnects Disconnect.Therefore by holding capacitor 22_BThe current potential PIX kept_BReduce Δ V2 (more than Δ V1).Current potential Δ V2 now is by the One switch element 231 and second switch element 232_BThe parasitic capacitance at electrode that controls determine.

If that is, last second switch element 232_BIt is changed into from on-state with the first switch element 231 simultaneously Off-state, then owing to being ultimately written the sub-pixel 20 of signal potential_BIn two switch elements 231 and 232_BParasitic capacitance and The coupled level caused is that about twice is big.Therefore, the sub-pixel 20 of signal potential it is ultimately written_BCoupled level (that is, by keeping Electric capacity 22_BThe current potential PIX kept_BChanges delta V2) be different from the sub-pixel 20 of previous write signal current potential_RWith 20_GCoupling electricity Flat, i.e. respectively by holding capacitor 22_RWith 22_GThe current potential PIX kept_RAnd PIX_GChanges delta V1.

If as it has been described above, keeping current potential PIX_R、PIX_GAnd PIX_BChange at multiple sub-pixels 20_R、20_GWith 20_BBetween Difference, then be ultimately written the sub-pixel 20 of signal potential_BIn the change relative to expection signal potential more than other sub-picture Element 20_RWith 20_G。

It is known that in liquid crystal indicator, owing to coupling the change of the holding current potential PIX caused by common electricity Position V_COMCompensating, this coupling is (usual, for being suitable to write signal current potential V by switch element_sigWriting transistor) control electricity At pole exist parasitic capacitance and cause.More specifically, this change is by applying side-play amount (offset) to electric with holding Common electric potential V that the change of position PIX is associated_COMCompensate.

Here, common electric potential V_COMFor applying the liquid crystal capacitance 21 to all pixels as above_R、21_GWith 21_BTo The current potential of electrode.Therefore, respectively by holding capacitor 21_RWith 21_GThe current potential PIX kept_RAnd PIX_GChanges delta V1 can by adjust Whole common electric potential V_COMCompensate.But, compensate by holding capacitor 22_BThe current potential PIX kept_BChanges delta V2 be highly difficult.

Therefore, it can desired signal potential V_sigWrite previous write signal current potential V_sigSub-pixel 20_RWith 20_G.So And, it would be desirable to signal potential V_sigWrite is ultimately written signal potential V_sigSub-pixel 20_BIt is highly difficult.Which results in face Imbalance between color (that is, red, green and blue).

2. according to the description of the liquid crystal indicator of embodiment

The liquid crystal indicator according to embodiment of the present invention of the following stated has been designed to select in using pixel During device driving method, it is ensured that the impact owing to being caused by the coupling controlling the parasitic capacitance at electrode of switch element is multiple The condition of sub-pixel is identical for these pixels.

In the present embodiment, it will again be assumed that pixel 20 includes red sub-pixel 20_R, green sub-pixels 20_GAnd blue subpixels 20_BIt is described.But, the condition of sub-pixel is not limited to the light being suitable to launch three kinds of primary colours (that is, red, green and blue) The condition of sub-pixel.That is, each pixel, in addition to including the sub-pixel being suitable to launch the light of three kinds of primary colours, also includes being suitable to send out Penetrate the one or more other sub-pixel of different colours.More specifically, for example, it is possible to add the sub-pixel being suitable to launch white light To improve brightness.It is alternatively possible to a kind of complementary color that adds is to strengthen color gamut.

Fig. 5 shows the structure example of the pixel of the active matrix liquid crystal display apparatus according to embodiment of the present invention Circuit diagram.In Figure 5, identical with the parts shown in Fig. 3 parts are represented by identical reference marks.

Pixel 20 according to present embodiment is also adopted by selector driving method in pixel.That is, sub-pixel 20 is being included_R、 20_GWith 20_BPixel 20 in, arrange selector portion 23 with by reflection gray level signal potential V_sigSequentially write sub-pixel 20_R、 20_GWith 20_B.Signal potential V_sigThere is provided via holding wire 31.

Selector portion 23 includes the first switch element 231 and three second switch elements 232_R、232_GWith 232_B.For sub-picture Element 20_R、20_GWith 20_BFirst switch element 231 is set jointly.For sub-pixel 20_R、20_GWith 20_BDivide and second switch element is set 232_R、232_GWith 232_B。

First switch element 231 makes its one end be connected to holding wire 31, and as the signal potential V of reflection gray level_sigExecute Add to holding capacitor 22_R、22_GOr 22_BTime connect (become Guan Bi).That is, the first switch element 231 is connected, with by signal potential V_sigWrite (loading) pixel 20.By control signal GATE₁Control switching on and off of the first switch element 231.

Second switch element 232_R、232_GWith 232_BIn the other end being each connected to the first switch element 231 and phase Sub-pixel (that is, the sub-pixel 20 of association_R、20_GWith 20_BIn one) pixel electrode (more specifically, liquid crystal capacitance 21_R、21_G With 21_BBetween).That is, second switch element 232_R、232_GWith 232_BIn its one end that each makes be commonly connected to the first switch The other end of element 231, and make sub-pixel (that is, the sub-pixel 20 that its other end is connected to be associated_R、20_GWith 20_BIn one Individual) pixel electrode.

Signal potential V when reflection gray level_sigHolding capacitor (that is, the holding capacitor 22 that write is associated_R、22_GWith 22_B In one) time, second switch element 232_R、232_GWith 232_BIn each connection.That is, second switch element 232_R、232_G With 232_BEach connection, with the signal potential V that will be loaded by the first switch element 231_sigThe holding capacitor that write is associated (that is, holding capacitor 22_R、22_GWith 22_BIn one).By control signal GATE_2R、GATE_2GAnd GATE_2BControl second switch Element 232_R、232_GWith 232_BSwitch on and off.

Pixel 20 according to present embodiment, in addition to selector driving method in employing pixel, has also combined use storage The memorizer of view data.The memorizer being combined in pixel 20 allows with both of which (that is, analog information pattern and memorizer Display pattern) show.Here, term " analog information pattern " refers to show in an analog fashion the gray level of pixel 20 Pattern.On the other hand, term " memory display mode " refers to based on the binary information (logic stored in memory " 1 " or " 0 ") show the pattern of the gray level of pixel 20 in a digital manner.

In memory display mode, employ storage information in memory.Therefore, there is no need to every frame all write instead Reflect the signal potential of gray level.As a result, than analog information pattern, (wherein, every frame all writes reflection gray scale to memory display mode The signal of level) consume less power.

SRAM (static RAM), DRAM (dynamic random access memory) or other memory elements can be used It is combined in the memorizer in pixel 20.Commonly known DRAM is structurally simple than SRAM.It should be noted, however, that refresh DRAM is to preserve data.

In the present embodiment, the retouching of situation being combined with DRAM (structurally simple than SRAM) in pixel 20 is given State.More specifically, use sub-pixel 20 according to the pixel 20 of present embodiment_R、20_GWith 20_BHolding capacitor 22_R、22_GWith 22_B As DRAM.DRAM is used to contribute to simplifying dot structure as the memorizer being combined in pixel 20 so that in pixel 20 Size reduction aspect, this structure is more favourable than the structure using SRAM.

Pixel 20 according to present embodiment, except being adapted for carrying out in pixel in addition to selector driving method, also includes being suitable to permit Permitted to use sub-pixel 20_R、20_GWith 20_BHolding capacitor 22_R、22_GWith 22_BPolarity inversion portion 24 as DRAM.For sub-pixel altogether With arranging 20_R、20_GWith 20_BPolarity inversion portion 24.Polarity inversion portion 24 inverts by sub-pixel 20_R、20_GWith 20_BHolding capacitor 22_R、22_GWith 22_BThe polarity of the signal potential kept, and signal potential polarity being inverted for refresh operation is again Write holding capacitor 22_R、22_GWith 22_B。

According to the embodiment of the present invention, it is provided that two kinds of display patterns, i.e. analog information pattern and memorizer display mould Formula.Signal drive division 40 shown in Fig. 1 is by the simulation current potential V under analog information pattern_sigWith two under memory display mode System current potential V_XCSExport to the holding wire 31 being associated as the signal potential reflecting any gray level.If additionally, pixel 20 The logic level of the signal potential of middle holding changes, then holding wire drive division 40 even must by reflection under memory display mode The signal potential wanting gray level exports to the holding wire 31 being associated.

As it has been described above, including that polarity inversion portion 24 (is adapted for carrying out by holding capacitor 22_R、22_GWith 22_BThe current potential kept Polarity inversion (logic inversion) and the refresh operation of these capacitors) image element circuit in, for sub-pixel 20_R、20_GWith 20_BJointly First switch element 231 is set.Its reason is to need by holding capacitor 22_R、22_GWith 22_BThe signal potential kept sequentially is held Row is by holding capacitor 22_R、22_GWith 22_BThe polarity inversion of the current potential kept and refresh operation.

In selector portion 23, the first switch element 231 is being suitable to the signal potential (V of reflection gray level_sigOr V_XCS) Write holding capacitor 22_R、22_GWith 22_BThe first operator scheme under connect.That is, the first switch element 231 is in the first operator scheme Lower connection, with by signal potential (V_sigOr V_XCS) write (loading) pixel 20.

First switch element 231 disconnects in the second mode of operation.Second operator scheme is suitable to read by by holding capacitor 22_R、22_GWith 22_BThe signal potential kept, inverts the polarity of these signal potentials with polarity inversion portion 24, and by polarity by instead The current potential turned re-writes holding capacitor 22_R、22_GWith 22_B.By control signal GATE₁Control connecing of the first switch element 231 On and off is opened.

Second switch element 232_R、232_GWith 232_BUnder the first and second operator schemes, reading by holding capacitor 22_R、 22_GWith 22_BThe time period current potential that is interior and that polarity be inverted that reads of the signal potential kept re-writes holding capacitor 22_R、22_GWith 22_BRe-write in the time period and connect.Second switch element 232_R、232_GWith 232_BDisconnect in other times section. By control signal GATE_2R、GATE_2GAnd GATE_2BControl second switch element 232_R、232_GWith 232_BSwitch on and off.

As it has been described above, in employing pixel in the liquid crystal indicator according to present embodiment of selector driving method, In selector driving time section, first the last second switch element connected disconnects, and hereafter the first switch element disconnects.More Body ground, if second switch element 232_R、232_GWith 232_BConnect in turn with red, green and blue and disconnect, then last Individual second switch element 232_BFirst disconnecting, hereafter the first switch element 232 disconnects.This driving control line as shown in Figure 1 drives Dynamic portion 50 performs.

Here, " last second switch element 232_BFirst disconnecting, hereafter the first switch element 231 disconnects " saying Refer to first switch element 231 and last second switch element 232_BDisconnect at different time.Therefore, one is also included Situation, wherein, the first switch element 231 is at second switch element 232_BPreset time after disconnection disconnects in section.

As it has been described above, last second switch element 232_BFirst disconnecting, hereafter the first switch element 231 disconnects.Knot Really, last second switch element 232_BDisconnect at different time with the first switch element 231.That is, second switch element 232_R、232_GWith 232_BSequentially switch on and off in section in the turn-on time of the first switch element 231.

Which ensure that the impact owing to being caused by the coupling controlling the parasitic capacitance at electrode of switch element is multiple Sub-pixel 20_R、20_GWith 20_BCondition at second switch element 232_R、232_GWith 232_BIn turn-off time of any one in section For sub-pixel 20_R、20_GWith 20_BIt is identical.Timing waveform with reference to shown in Fig. 6 A to Fig. 6 H is provided its detailed retouching State.

Fig. 6 A to Fig. 6 H is for describing the operation according to the image element circuit in the liquid crystal indicator of present embodiment Timing waveform.

Fig. 6 A to Fig. 6 E respectively illustrates the current potential V of holding wire 31_sigWith control signal GATE₁、GATE_2R、GATE_2G、 GATE_2BWaveform.Additionally, Fig. 6 F and Fig. 6 H respectively illustrates respectively by holding capacitor 22_R、22_GWith 22_BThe current potential PIX kept_R、 PIX_GAnd PIX_BWaveform.

As shown in Fig. 6 A to Fig. 6 H, when second switch element 232_R、232_GWith 232_BWith red, green and blue order When switching on and off, last second switch element 232_BFirst disconnecting, hereafter the first switch element 231 disconnects.More specifically Ground, second switch element 232_BControl signal GATE_2BFirst it is changed into low level from high level, hereafter the first switch element Control signal GATE of 231₁It is changed into low level from high level.

Due to this sequential relationship, control signal GATE_2R、GATE_2GAnd GATE_2BIn control signal GATE₁Activationary time Sequentially it is changed into low level from high level in section (high time period).That is, with control signal GATE_2RAnd GATE_2GEqually, second open Close element 232_BControl signal GATE_2BEarly than control signal GATE₁It is changed into low level from high level.

As it has been described above, by making control signal GATE_2BEarly than control signal GATE₁It is changed into low level from high level, can To guarantee to be affected sub-pixel 20 due to cause by the coupling of parasitic capacitance_R、20_GWith 20_BCondition for these pixels Speech is identical.I.e., respectively by holding capacitor 22_R、22_GWith 22_BThe all current potential PIX kept_R、PIX_GAnd PIX_BDue to by son Pixel 20_R、20_GWith 20_BIn the coupling of parasitic capacitance and change Δ V1.

By above-mentioned common voltage V_COMAdjustment technology and will be suitable for changes delta V1 side-play amount apply to common voltage V_COM, can be for all sub-pixels 20_R、20_GWith 20_BAnd jointly compensate this changes delta V1.This allows to for sub-pixel 20_R、20_GWith 20_BHolding capacitor 22_R、22_GWith 22_BKeep desired signal potential, thus avoid due to by parasitic capacitance Imbalance between the color that coupling is caused.

In order to set up above-mentioned sequential relationship, it is assumed that control signal GATE₁Activationary time section (high time period) fix, then control Signal GATE processed_2R、GATE_2GAnd GATE_2BIn each activationary time section be inevitably shorter than the activation in Fig. 4 A to Fig. 4 H Time period.This means signal potential V_sigIt is respectively written into sub-pixel 20_R、20_GWith 20_BSecond switch element 232_R、232_GWith 232_BThe length of write time section slightly shorter than the situation shown in Fig. 4 A to Fig. 4 H.

However, it is possible to say, by assuring that by the condition of the coupling of parasitic capacitance for sub-pixel 20_R、20_GWith 20_BIt it is phase The same balance between color that keeps more counteracts slightly shorter write time section (for by signal potential V_sigWrite sub-pixel 20_R、20_GWith 20_B) shortcoming.

It should be noted that, have been described with following situation in this example, i.e. apply the present invention to be combined with memorizer Pixel 20.But, the application of the present invention is not limited to be combined with the pixel of memorizer.The present invention can be additionally used in generally using pixel The pixel 20 of selector driving method.

According in the liquid crystal indicator of this embodiment, inverter circuit or latch cicuit such as can serve as polarity Inversion portion 24.The description of the instantiation in polarity inversion portion 24 is given below.

2-1 example 1

Fig. 7 shows the circuit diagram of the image element circuit according to example 1.In the figure 7, identical with the parts in Fig. 5 portion Part is represented by identical reference marks.

In the image element circuit according to example 1, polarity inversion portion 24_AIncluding inverter circuit the 241, the 3rd switch element 242 and the 4th switch element 243.In this example 1, thin film transistor (TFT) is used for example as the first switch element 231, second switch unit Part 232_R、232_GWith 232_B, the 3rd switch element 242 and the 4th switch element 243.

Hereinafter, these switch elements 231,232_R、232_GWith 232_B, 242 and 243 will be indicated as switching transistor 231、232_R、232_GWith 232_B, 242 and 243.Although N-channel MOS transistor is herein used as switching transistor 231,232_R、 232_GWith 232_B, 242 and 243 but it also may use P channel MOS transistor instead.

Circuit structure

In the figure 7, selector portion 23 has substantially identical with the circuit structure shown in Fig. 5 circuit structure, simply First switch element 231 and second switch element 232_R、232_GWith 232_BReplaced by MOS transistor.

That is, the first switching transistor 231 makes one in its main electrode (drain electrode or source electrode) to be connected to holding wire 31. When in control signal GATE₁Control under will reflection gray level signal potential (V_sigOr V_XCS) write (loading) from holding wire 31 During pixel 20, this first switching transistor 231 enters conducting state.

Second switch transistor 232_RIn its main electrode one is made to be commonly connected to liquid crystal capacitance 21_RPixel electrode and Holding capacitor 22_RAn electrode.Second switch transistor 23_2RIts another main electrode is made to be connected to the first switching transistor 231 Another main electrode.When for red control signal GATE_2RControl under will reflection gray level signal potential (V_sigOr V_XCS) write holding capacitor 22_RTime, this second switch transistor 232_REnter conducting state.

Second switch transistor 232_GIn its main electrode one is made to be commonly connected to liquid crystal capacitance 21_GPixel electrode and Holding capacitor 22_GAn electrode.Second switch transistor 232_GIts another main electrode is made to be connected to the first switching transistor 231 Another main electrode.When for green control signal GATE_2GControl under will reflection gray level signal potential (V_sigOr V_XCS) write holding capacitor 22_GTime, this second switch transistor 232_GEnter conducting state.

Second switch transistor 232_BIn its main electrode one is made to be commonly connected to liquid crystal capacitance 21_BPixel electrode and Holding capacitor 22_BAn electrode.Second switch transistor 232_BIts another main electrode is made to be connected to the first switching transistor 231 Another main electrode.When for blue control signal GATE_2BControl under will reflection gray level signal potential (V_sigOr V_XCS) write holding capacitor 22_BTime, this second switch transistor 232_BEnter conducting state.

In polarity inversion portion 24_AIn, inverter circuit 241 such as includes CMOS inverter.More specifically, inverter circuit 241 include P channel MOS transistor Q_p1With N-channel MOS transistor Q_n1, they are connected in series in power supply potential V_DDAnd V_SSPower supply Between line.

P channel MOS transistor Q_p1With N-channel MOS transistor Q_n1Gate electrode link together, for use as phase inverter electricity The input on road 241.This input is connected to another main electrode of the 3rd switching transistor 242.Additionally, P channel MOS transistor Q_p1With N-channel MOS transistor Q_n1Drain electrode link together, for use as the outfan of inverter circuit 241.This outfan It is connected to another main electrode of the 4th switching transistor 243.

During refresh operation under the memory display mode that inverter circuit 241 configured as described above is described below Between in section reversion by holding capacitor 22_R、22_GWith 22_BThe polarity (that is, logic level) of the current potential kept.

3rd switching transistor 242 makes one in its main electrode another main electricity being connected to the first switching transistor 231 Pole, and make its another main electrode be connected to input (that is, the P channel MOS transistor Q of inverter circuit_p1With N-channel MOS crystal Pipe Q_n1Gate electrode).When in control signal SR₁Control under will reflection gray level signal potential (V_sigOr V_XCS) from holding wire During 31 writing pixel 20, the 3rd switching transistor 242 enters nonconducting state.

Additionally, when in control signal SR₁Control under, under memory display mode perform refresh operation time, the 3rd opens Close transistor 242 and enter conducting state, and keep this state to continue section preset time before following every frame end closely.Carry in passing And, when the 3rd switching transistor 242 turns on, by the holding capacitor 22 as DRAM_R、22_GWith 22_BThe current potential kept is via the Three switching transistors 242 are read the input to inverter circuit 241.

4th switching transistor 243 makes one in its main electrode another main electricity being connected to the first switching transistor 231 Pole, and make its another main electrode be connected to outfan (that is, the P channel MOS transistor Q of inverter circuit 241_p1And N-channel MOS Transistor Q_n1Drain electrode).When in control signal SR₂Control under will reflection gray level signal potential (V_sigOr V_XCS) from letter During number line 31 writing pixel 20, the 4th switching transistor 243 enters nonconducting state.

Additionally, when in control signal SR₂Control under, under memory display mode perform refresh operation time, the 4th opens Close transistor 243 and enter conducting state, and after every frame starts, keep the time period that this state persistently gives immediately.Carry in passing And, when the 4th switching transistor 243 turns on, the signal potential that polarity (logic level) has been inverted is via the 4th switch crystal Pipe 243 and second switch transistor 232_R、232_GWith 232_BAnd it is written into holding capacitor 22_R、22_GWith 22_B。

Circuit operation

It follows that operation (that is, the sub-pixel 20 of image element circuit that will be given according to examples detailed above 1_R、20_GWith 20_BAt every kind Operation under display pattern) description.

(1) analog information pattern

Fig. 8 A to Fig. 8 F is the sequential ripple for describing the operation under analog information pattern of the image element circuit according to example 1 Shape figure.Fig. 8 A to Fig. 8 F respectively illustrates holding wire 31, control signal GATE₁, for red control signal GATE_2R, be used for Green control signal GATE_2G, for blue control signal GATE_2BAnd control signal SR₁Or SR₂The waveform of current potential.

In this example, in each leveled time section (1H/ line) for the purpose driven, liquid crystal capacitance 21 will be applied to_R、 21_GWith 21_BPixel electrode and counter electrode between the polarity inversion of voltage, i.e. perform line reversion and drive.It is known that be Prevent the ratio resistance (specific resistance) of liquid crystal in liquid crystal indicator and other characteristics (substrate intrinsic Resistance) deterioration, perform (be designed to given interval about common electric potential V_COMReversion applies the polarity of the voltage to liquid crystal ) AC driving.

In this embodiment, perform line reversion driving to drive as this AC.Drive, such as Fig. 8 A to perform the reversion of this line Shown in, in each leveled time section by the polarity inversion of the signal potential (that is, the current potential of holding wire 31) of reflection gray level.At figure In waveform shown in 8A, high level current potential is V_DD1, low level current potential is V_SS1.Additionally, Fig. 8 A shows that amplitude is from V_DD1Extremely V_SS1Maximum magnitude.Fall according to gray level from V it practice, the current potential of holding wire 31 presents_DD1To V_SS1In the range of electricity Flat.

Showing control signal GATE₁Waveform Fig. 8 B in, high level current potential is V_DD2, low level current potential is V_SS2。 Control signal GATE₁Rise to high level current potential V_DD2, and electric from holding wire 31 write holding at the signal potential of reflection gray level Hold 22_R、22_GWith 22_BWrite time section in be maintained at this level.

Showing control signal GATE equally_2R、GATE_2GAnd GATE_2BFig. 8 C of waveform, Fig. 8 D and Fig. 8 E in, high electricity Ordinary telegram position is V_DD2, low level current potential is V_SS2.Signal potential in reflection gray level writes holding capacitor 22 from holding wire 31_R、 22_GWith 22_BWrite time section in, i.e. in control signal GATE₁It is in high level current potential V_DD2Time period in, control signal GATE_2R、GATE_2GAnd GATE_2BSuch as sequentially rise to high level current potential V with red, green and blue_DD2。

It should be noted that, control signal GATE_2R、GATE_2GAnd GATE_2BIt is maintained at high level current potential V_DD2Time period rise each other The most overlapping.Additionally, in control signal GATE_2R、GATE_2GAnd GATE_2BIt is maintained at high level current potential V_DD2Time period in, for each The signal potential V of the reflection gray level of color_sigExport respectively to holding wire 31 from the holding wire drive division 40 shown in Fig. 1.

Equally, control signal SR is being shown₁Or SR₂Waveform Fig. 8 F in, high level current potential is V_DD2, low level current potential For V_SS2.Control signal SR₁Or SR₂Low level current potential V it is generally under analog information pattern_SS2。

(2) memory display mode

Under memory display mode, perform write operation and refresh operation.Write operation is by the signal of reflection gray level Current potential writes holding capacitor 22 from holding wire 31_R、22_GWith 22_B.Refresh operation refreshes by holding capacitor 22_R、22_GWith 22_BKeep Current potential.In these operations, such as, perform write operation, to change the content of information to be shown.It should be noted that, be suitable to instead The signal potential reflecting gray level writes holding capacitor 22 from holding wire 31_R、22_GWith 22_BWrite operation with analog information pattern be Identical.Therefore, descriptions thereof is omitted.

Fig. 9 A to Fig. 9 H is for being described under memory display mode by according to performed by the image element circuit of example 1 The timing waveform of refresh operation, it is shown that the relation that (1F) (frame-by-frame) drives on a frame-by-frame basis.

Fig. 9 A to Fig. 9 E respectively illustrates control signal GATE_2R、GATE_2GAnd GATE_2B、SR₁Or SR₂And CS current potential V_CS Waveform.Additionally, Fig. 9 F to Fig. 9 H respectively illustrates write holding capacitor 22_R、22_GWith 22_BSignal potential PIX_R、PIX_GWith PIX_BWaveform.

From the timing waveform as shown in Fig. 9 A to Fig. 9 H it is readily apparent that in every three frames with impulse form produce control Signal GATE processed_2R、GATE_2GAnd GATE_2BIn each high level current potential.On the contrary, in every frame, control is produced with impulse form Signal SR₁Or SR₂High potential.In every frame, this CS current potential V_CSBetween high level current potential and low level current potential alternately.

On the other hand, in Fig. 9 F, Fig. 9 G and Fig. 9 H, CS current potential V_CSWaveform shown by dashed lines, and reflect gray level Signal potential PIX_R、PIX_GAnd PIX_BWaveform illustrated by solid line.The signal potential PIX of reflection gray level_R、PIX_GAnd PIX_BEvery frame All along with CS current potential V_CSEvery frame changes and changes.CS current potential V_CSWith signal potential PIX_R、PIX_GAnd PIX_BBetween electric potential relation Every three frames change.

That is, by the holding capacitor 22 for each color_R、22_GWith 22_BThe current potential PIX kept_R、PIX_GAnd PIX_BEvery three frames are sent out Raw polarity inversion is also refreshed.Naturally, signal potential PIX_R、PIX_GAnd PIX_BBetween electric potential relation from previous polarity invert Current polarity reversion and refresh operation is remained to refresh operation.Therefore, in this example, it is desirable to holding capacitor 22_R、22_GWith 22_BThere is sufficiently large electric capacity, in order to though refresh rate be every three frames once, still keep reflect gray level signal potential PIX_R、 PIX_GAnd PIX_B。

It should be noted that, control signal GATE₁Low level current potential it is generally under memory display mode.As a result, first Switching transistor 231 enters nonconducting state (Guan Bi switching state), so that sub-pixel 20_R、20_GWith 20_BIn each with letter Number line 31 electrically insulates.

It follows that by the detailed description of the operation that provides a frame.Figure 10 A to Figure 10 D is for describing memorizer display mould The timing waveform of the operation of the scan line under formula.Here, the sub-pixel 20 of green (G) will be given_GThe description conduct of operation Example.But, the sub-pixel 20 of other colors_RWith 20_BOperate the most in the same manner.

Figure 10 A to Figure 10 D shows control signal GATE the most in an exaggerated way_2G、SR₁And SR₂And CS current potential V_CS? The waveform of the boundary between frame.It should be noted that, in Figure 10 A to Figure 10 D, present frame is represented by reference marks N, next frame by Reference marks N+1 represents.

, be suitable to make in section to the preset time followed closely after next frame N+1 starts before present frame N terminates from following closely Two switching transistors 232_GEnter control signal GATE of conducting and nonconducting state_2GIt is maintained at high level current potential V_DD2.Following closely Preset time before every frame end in section, is suitable to make the 3rd switching transistor 242 enter conducting or the control of nonconducting state Signal SR₁It is maintained at high level current potential V_DD2.Preset time after following every frame closely and starting in section, is suitable to make the 4th switch crystalline substance Body pipe 243 enters control signal SR of conducting and nonconducting state₂It is maintained at high level current potential V_DD2。

At (second switch transistor 232_GDue to control signal GATE_2GRise to high level current potential V_DD2And enter conducting shape State) boundary between frame, the 3rd switching transistor 242 is due to control signal SR₁First high level current potential V is risen to_DD2And Enter conducting state.As a result, by holding capacitor 22_GThe current potential PIX kept_GVia second switch transistor 232_GWith the 3rd switch Transistor 242 and be read, and be provided to the input of inverter circuit 241.

Inverter circuit 241 inverts from holding capacitor 22_GThe holding current potential PIX read_GPolarity (logic level).Due to This action of inverter circuit 241, is in high level current potential V_DD1Input current potential be reversed to the low level current potential of outfan V_SS1。

In next frame N+1, the 4th switching transistor 243 is owing to rising to high level current potential V_DD2Control signal SR₂And Enter conducting state.This makes polarity (logic level) be inverted signal potential (that is, the phase inverter electricity of device circuit 241 reversion The output current potential on road 241) via the 4th switching transistor 243 and second switch transistor 232_GAnd write holding capacitor 22_G.Knot Really, make by holding capacitor 22_GThe current potential PIX kept_GPolarity inversion.This sequence of operations makes by holding capacitor 22_GKeep Current potential PIX_GPolarity inversion and be refreshed.

Then, in refresh operation, the holding wire 31 with heavy load capacity is not charged or discharges.In other words, Due to inverter circuit 241 and switching transistor 231,232_G, 242 and the action of 243, by holding capacitor 22_GThe current potential kept PIX_GPolarity inversion can be made in the case of the holding wire with heavy load capacity not being charged or discharged and brushed Newly.

By holding capacitor 22_GThe current potential PIX kept_GAbove-mentioned polarity inversion and refresh operation under memory display mode Every three frames are repeated once.Here, give sub-pixel 20_GThe polarity inversion performed and the description of refresh operation.But, often In frame, to red sub-pixel 20_R, green sub-pixels 20_GWith blue subpixels 20_BSequentially carry out aforesaid operations.It should be noted that, it is suitable Sequence is arbitrary.

Image element circuit according to examples detailed above 1 provides one can be under analog information pattern and memory display mode The liquid crystal indicator played a role.Additionally, holding capacitor 22_R、22_GWith 22_BDRAM it is used as under memory display mode, from And if contributing to simpler dot structure than SRAM is used as memorizer.As a result, in terms of the granular of pixel 20, this picture Element circuit is more favourable as the image element circuit of memorizer than using SRAM.

Additionally, substantially without electrical connection pixel 20 and holding wire 31 under memory display mode.That is, not to tool In the case of the holding wire 31 having heavy load capacity is charged or discharges, can refresh by holding capacitor 22_R、22_GWith 22_BProtect The current potential PIX held_R、PIX_GAnd PIX_B.This provides the even lower power consumption under memory display mode.

Further, pass through first to make last second switch transistor 232 according to the image element circuit of example 1_BDisconnect And then make the first switching transistor 231 disconnect and provide following function and effect.

That is, at these second switch transistors 232_R、232_GWith 232_BIn any one turn-off time in section, due to By being present in the multiple sub-pixel of impact that the coupling controlling the parasitic capacitance at electrode of second switch transistor is caused 20_R、20_GWith 20_BCondition be identical for these sub-pixels.This makes sub-pixel 20_R、20_GWith 20_BHolding capacitor 22_R、22_GWith 22_BDesired signal potential can be kept, thus avoid the color owing to being caused by the coupling of parasitic capacitance Between imbalance.

According to (using inverter circuit 241 as polarity inversion portion 24_A) in the image element circuit of example 1, phase inverter Circuit 241 includes such as two MOS transistor Q_p1And Q_n1The most extremely simple, thus contribute to simpler pixel knot Structure.As a result, in terms of the granular of pixel 20, this image element circuit is more favourable as the image element circuit of memorizer than using SRAM.

2-2 example 2

Figure 11 shows the circuit diagram of the image element circuit according to example 2.In fig. 11, with the parts phase shown in Fig. 7 With parts represented by identical reference number.

In the image element circuit according to example 2, polarity inversion portion 24_BIncluding latch cicuit the 244, the 3rd switching transistor 242 and the 4th switching transistor 243.In this example 2, thin film transistor (TFT) such as also serves as the switch crystal as switch element Pipe 231,232_R、232_GWith 232_B, 242 and 243.On the other hand, although N-channel MOS transistor be used as switching transistor 231, 232_R、232_GWith 232_B, 242 and 243 but it also may use P channel MOS transistor instead.

Circuit structure

In fig. 11, selector portion 23 has and the identical circuit structure of circuit structure according to example 1.That is, One switching transistor 231 makes one (drain electrode or source electrode) in its main electrode to be connected to holding wire 31.When in control signal GATE₁Control under will reflection gray level signal potential (V_sigOr V_XCS) when holding wire 31 writes (loading) pixel 20, should First switching transistor 231 enters conducting state.

Second switch transistor 232_RIn its main electrode one is made to be commonly connected to liquid crystal capacitance 21_RPixel electrode and Holding capacitor 22_RAn electrode.Second switch transistor 232_RIts another main electrode is made to be connected to the first switching transistor 231 Another main electrode.When for red control signal GATE_2RControl under will reflection gray level signal potential (V_sigOr V_XCS) write holding capacitor 22_RTime, this second switch transistor 232_REnter conducting state.

Second switch transistor 232_GIn its main electrode one is made to be commonly connected to liquid crystal capacitance 21_GPixel electrode and Holding capacitor 22_GOne of them electrode.Second switch transistor 232_GIts another main electrode is made to be connected to the first switching transistor Another main electrode of 231.When for green control signal GATE_2GControl under will reflection gray level signal potential (V_sig Or V_XCS) write holding capacitor 22_GTime, this second switch transistor 232_GEnter conducting state.

In polarity inversion portion 24_BIn, latch cicuit 244 such as includes two CMOS inverter.More specifically, a CMOS Phase inverter includes being connected in series in power supply potential V_DDAnd V_SSPower line between P channel MOS transistor Q_p11And N-channel MOS Transistor Q_n11.Another CMOS inverter similarly includes being connected in series in power supply potential V_DDAnd V_SSPower line between P ditch Road MOS transistor Q_p12With N-channel MOS transistor Q_n12。

P channel MOS transistor Q_p11With N-channel MOS transistor Q_n11Gate electrode link together, for use as latch cicuit The input of 244.This input is connected to another main electrode of the 3rd switching transistor 242.P channel MOS transistor Q_p12And N Channel MOS transistor Q_n12Gate electrode link together, for use as the outfan of latch cicuit 244.This outfan is connected to Another main electrode of four switching transistors 243.

Additionally, P channel MOS transistor Q_p11With N-channel MOS transistor Q_n11Gate electrode via control transistor Q_n13And It is connected to P channel MOS transistor Q_p12With N-channel MOS transistor Q_n12Drain electrode.P channel MOS transistor Q_p12And N-channel MOS transistor Q_n12Gate electrode be connected directly to P channel MOS transistor Q_p11With N-channel MOS transistor Q_n11Drain electrode.

In the refresh operation time period under memory display mode, control transistor Q_n13In control signal SR₃Control Under optionally activate latch cicuit 244.More specifically, when controlling transistor Q_n13During conducting, including two CMOS inverter Latch cicuit 244 is activated.By holding capacitor 22_R、22_GWith 22_BKeep current potential by the activation of latch cicuit 244 in pole Invert in property, and be refreshed.On the other hand, when controlling transistor Q_n13When being not turned on, two phase inverters both function as independent amplification Unit.

3rd switching transistor 242 makes one in its main electrode another main electricity being connected to the first switching transistor 231 Pole, and make its another main electrode be connected to input (that is, the MOS transistor Q of latch cicuit 244_p11And Q_n11Gate electrode).When In control signal SR₁Control under will reflection gray level signal potential (V_sigOr V_XCS) when holding wire 31 writing pixel 20, 3rd switching transistor 242 enters nonconducting state.

Additionally, when in control signal SR₁Control under under memory display mode perform refresh operation time, the 3rd switch Transistor 242 enters conducting state, and keeps the most persistently following section preset time before every frame end closely.Carry in passing And, when the 3rd switching transistor 242 turns on, by the holding capacitor 22 as DRAM_R、22_GWith 22_BThe current potential kept is via the Three switching transistors 242 and the input that is read to latch cicuit 244.

4th switching transistor 243 makes one in its main electrode another main electricity being connected to the first switching transistor 231 Pole, and make its another main electrode be connected to outfan (that is, the MOS transistor Q of latch cicuit 244_p12And Q_n12Gate electrode).When In control signal SR₂Control under will reflection gray level signal potential (V_sigOr V_XCS) when holding wire 31 writing pixel 20, 4th switching transistor 243 enters nonconducting state.

Additionally, when in control signal SR₂Control under under memory display mode perform refresh operation time, the 4th switch Transistor 243 enters conducting state, and keeps the most persistently following the time period after every frame starts closely.Incidentally, When the 4th switching transistor 243 turns on, the signal potential warp being inverted by its polarity of latch cicuit 244 (logic level) By the 4th switching transistor 243 and second switch transistor 232_R、232_GWith 232_BAnd write holding capacitor 22_R、22_GWith 22_B。

Circuit operation

It follows that the description of the operation of image element circuit that will be given according to examples detailed above 2, i.e. sub-pixel 20_R、20_GWith 20_B Operation under each display pattern.

(1) analog information pattern

Figure 12 A to Figure 12 G is the sequential for describing the operation under analog information pattern of the image element circuit according to example 2 Oscillogram.Figure 12 A to Figure 12 G respectively illustrates holding wire 31, control signal GATE₁, for red control signal GATE_2R、 For green control signal GATE_2GWith control signal GATE for blueness_2B, control signal SR₁Or SR₂And control signal SR₃The waveform of current potential.

In this example, for the purpose driven, in each leveled time section (1H/ line), liquid crystal capacitance will be applied to 21_R、21_GWith 21_BPixel electrode and counter electrode between the polarity inversion of voltage, i.e. perform line reversion and drive that (AC drives Dynamic).Drive to perform the reversion of this line, as illustrated in fig. 12, in every leveled time section, by the signal potential of reflection gray level Polarity (that is, the current potential of holding wire 31) reversion.

In the waveform of the signal potential of the reflection gray level shown in fig. 12, high level current potential is V_DD1, low level electricity Position is V_SS1.Additionally, Figure 12 A shows that amplitude is from V_DD1To V_SS1The maximum magnitude of change.It practice, the current potential of holding wire 31 in Now fall according to gray level from V_DD1To V_SS1In the range of level.

Showing control signal GATE₁Waveform Figure 12 B in, high level current potential is V_DD2, and low level current potential is V_SS2.Control signal GATE₁Rise to high level current potential V_DD2, and protect from holding wire 31 write at the signal potential reflecting gray level Hold electric capacity 22_R、22_GWith 22_BWrite time section in be maintained at this level.

Equally, control signal GATE is being shown_2R、GATE_2GAnd GATE_2BFigure 12 C of waveform, Figure 12 D and Figure 12 E in, High level current potential is V_DD2, low level current potential is V_SS2.Signal potential in reflection gray level writes holding capacitor from holding wire 31 22_R、22_GWith 22_BWrite time section in, i.e. in control signal GATE₁It is in high level current potential V_DD2Time period in, control Signal GATE_2R、GATE_2GAnd GATE_2BSuch as sequentially rise to high level current potential V with red, green and blue_DD2。

It should be noted that, control signal GATE_2R、GATE_2GAnd GATE_2BIt is maintained at high level current potential V_DD2Time period the most not Overlapping.Additionally, in control signal GATE_2R、GATE_2GAnd GATE_2BIt is maintained at high level current potential V_DD2Time period in, reflect each face The signal potential V of the gray level of color_sigExport respectively to holding wire 31 from the holding wire drive division 40 shown in Fig. 1.

Equally, control signal SR is being shown₁Or SR₂And SR₃Waveform Figure 12 F and Figure 12 G in, high level current potential is V_DD2, low level current potential is V_SS2.Under analog information pattern, control signal SR₁Or SR₂It is generally in low level current potential V_SS2, and And control signal SR₃It is generally in high level current potential V_DD2。

(2) memory display mode

Under memory display mode, perform write operation and refresh operation.Write operation is by the signal of reflection gray level Current potential writes holding capacitor 22 from holding wire 31_R、22_GWith 22_B.Refresh operation refreshes by holding capacitor 22_R、22_GWith 22_BKeep Current potential.In these operate, such as, perform write operation, to change the content of information to be shown.It should be noted that, be suitable to by The signal potential of reflection gray level writes holding capacitor 22 from holding wire 31_R、22_GWith 22_BWrite operation and analog information pattern It is identical.Therefore, descriptions thereof is eliminated.

Figure 13 A to Figure 13 I is for being described under memory display mode by the image element circuit execution according to example 2 The timing waveform of refresh operation, it is shown that the relation that (1F) drives on a frame-by-frame basis.

Figure 13 A to Figure 13 F respectively illustrates control signal GATE_2R、GATE_2G、GATE_2B、SR₁Or SR₂、SR₃And CS electricity Position V_CSWaveform.Additionally, Figure 13 G to Figure 13 I respectively illustrates write holding capacitor 22_R、22_GWith 22_BSignal potential PIX_R、 PIX_GAnd PIX_BWaveform.

From the timing waveform as shown in Figure 13 A to Figure 13 I it is readily apparent that in every three frames with impulse form produce Control signal GATE_2R、GATE_2G、GATE_2BIn each high level current potential.On the contrary, in every frame, control is produced with impulse form Signal SR processed₁Or SR₂High potential.Control signal SR is produced with impulse form in every frame₃Low level current potential.In every frame, CS current potential V_CSBetween high level current potential and low level current potential alternately.

On the other hand, in Figure 13 G, Figure 13 H and Figure 13 I, CS current potential V_CSWaveform be illustrated by the broken lines, and reflect gray scale The signal potential PIX of level_R、PIX_GAnd PIX_BWaveform represented by solid line.The signal potential PIX of reflection gray level_R、PIX_GAnd PIX_B Every frame is all along with CS current potential V_CSThe change of every frame and change.CS current potential V_CSWith signal potential PIX_R、PIX_GAnd PIX_BBetween electricity Position every three frames of relation change.

That is, by the holding capacitor 22 for each color_R、22_GWith 22_BThe current potential PIX kept_R、PIX_GAnd PIX_BEvery three frames are sent out Raw polarity inversion is also refreshed.Naturally, signal potential PIX_R、PIX_GAnd PIX_BBetween electric potential relation from previous polarity invert Current polarity reversion and refresh operation is remained to refresh operation.Therefore, in this example, it is desirable to holding capacitor 22_R、22_GWith 22_BThere is sufficiently large electric capacity, in order to though refresh rate be every three frames once, still with keep reflection gray level signal potential PIX_R、PIX_GAnd PIX_B。

It should be noted that, control signal GATE₁Low level current potential it is generally under memory display mode.As a result, first Switching transistor 231 enters nonconducting state (closed-switch-state), so that sub-pixel 20_R、20_GWith 20_BEach and signal Line 31 electrically insulates.

It follows that the detailed description of operation that will be given in a frame.Figure 14 A to Figure 14 E is to show for describing memorizer The timing waveform of the scan line operation under pattern.Here, the sub-pixel 20 of green (G) will be given_GOperation as an example.So And, for the sub-pixel 20 of other colors_RWith 20_BOperate in the same manner.

Figure 14 A to Figure 14 E shows control signal GATE the most in an exaggerated way_2G、SR₁、SR₂And SR₃And CS current potential V_CSThe waveform of boundary between frames.It should be noted that, in Figure 14 A to Figure 14 E, present frame is represented by reference marks N, under One frame is represented by reference marks N+1.

, be suitable in section to the preset time after the beginning following next frame N+1 closely before the end following present frame N closely Make second switch transistor 232_GEnter conducting or control signal GATE of nonconducting state₂It is maintained at high level current potential V_DD2.? Follow the preset time before the end of every frame closely in section, be suitable to make the 3rd switching transistor 242 enter conducting or nonconducting state Control signal SR₁It is maintained at high level current potential V_DD2.Preset time after following every frame closely and starting in section, is suitable to make the 4th Switching transistor 243 enters conducting or control signal SR of nonconducting state₂It is maintained at high level current potential V_DD2。

Be suitable to make the control transistor Q of latch cicuit 244_n13Enter conducting or control signal SR of nonconducting state₃Substantially On present high level current potential V_DD2.But, following closely from holding capacitor 22_GRead the signal potential PIX of reflection gray level_GStart it Before, control signal SR₃Drop to low level current potential V_SS2.When through section preset time, control signal SR₃Again present high level Current potential V_DD2.In control signal SR₁It is in high level current potential V_DD2Time period in, control signal SR₃It is in high level current potential V_DD2。

At (second switch transistor 232_GDue to control signal GATE_2GRise to high level current potential V_DD2And enter conducting shape State) boundary between frame, the 3rd switching transistor 242 is due to control signal SR₁First high level current potential V is risen to_DD2's And enter conducting state.As a result, by holding capacitor 22_GThe current potential PIX kept_GVia second switch transistor 232_GOpen with the 3rd Close transistor 242 and be read, and be provided to the input of latch cicuit 244.

In control signal SR₁It is maintained at high level current potential V_DD2Time period in (that is, within the read operation time period), control Signal SR processed₃Rise to high level current potential V_DD2, so that controlling transistor Q_n13Enter conducting state and activate latch cicuit 244.That is, the latch function of latch cicuit 244 is enabled.This is by holding capacitor 22_GThe current potential PIX kept_GRepair to its original letter Number current potential.That is, holding current potential PIX has been recovered_GLogic swing.Refresh operation is designed to make holding current potential PIX_GRecover it to patrol Collect and swing.

At the end of refresh operation, control signal SR₁Again drop to low level current potential V_SS2, so that controlling transistor Q_n13Enter nonconducting state.Now, the signal potential PIX of gray level is reflected_G(from holding capacitor 22 in present frame N_GRead Take, recover its logic swing by latch cicuit 244 and invert its logic level (polarity)) including MOS transistor Q_p12 And Q_n12CMOS inverter input occur.

In next frame N+1, control signal SR₂Rise to high level current potential V_DD2, make the 4th switching transistor 243 enter Conducting state.As a result, signal potential (that is, the latch of logic swing and inverting logic levels is recovered by latch cicuit 244 The output voltage of circuit 244) via the 4th switching transistor 243 and second switch transistor 232_GAnd write holding capacitor 22_G。 This makes by holding capacitor 22_GThe current potential PIX kept_GPolarity inversion.This sequence of operations can make by holding capacitor 22_GKeep Current potential PIX_GPolarity inversion and be refreshed.

Then, the holding wire 31 with heavy load capacity is not charged or discharges in refresh operation.In other words, Due to latch cicuit 244 and switching transistor 231,232_G, 242 and the action of 243, by holding capacitor 22_GThe current potential kept PIX_GPolarity inversion and quilt can be made in the case of the holding wire 31 with heavy load capacity not being charged or discharged Refresh.

By holding capacitor 22_GThe current potential PIX kept_GAbove-mentioned polarity inversion and refresh operation under memory display mode Every three frames are repeated once.Here, give sub-pixel 22_GThe polarity inversion performed and the description of refresh operation.But, often In frame, to red sub-pixel 20_R, green sub-pixel 20_GWith blue sub-pixel 20_BSequentially carry out aforesaid operations.Should note Meaning, order is arbitrary.

Image element circuit according to examples detailed above 2 provides the function identical with the image element circuit according to example 1 and effect. That is, holding capacitor 22_R、22_GWith 22_BDRAM it is used as, if thus had than SRAM is used as memorizer under memory display mode Help simpler dot structure.As a result, in terms of the granular of pixel 20, image element circuit is than using SRAM as memorizer more Favorably.

Additionally, substantially without connecting pixel 20 and holding wire 31 under memory display mode.That is, not to having In the case of the holding wire 31 of heavy load capacity is charged or discharges, can refresh by holding capacitor 22_R、22_GWith 22_BKeep Current potential PIX_R、PIX_GAnd PIX_B.This provides the even lower power consumption under memory display mode.

Further, even pass through first to make last second switch transistor 232 according to the image element circuit of example 2_B Disconnect and then make the first switching transistor 231 disconnect and provide following function and effect.

That is, at these second switch transistors 232_R、232_GWith 232_BIn any one turn-off time in section, due to The multiple sub-pixel of impact 20 caused by being present in the coupling of the parasitic capacitance at the gate electrode of second switch transistor_R、 20_GWith 20_BCondition be identical for these sub-pixels.This makes sub-pixel 20_R、20_GWith 20_BHolding capacitor 22_R、 22_GWith 22_BDesired signal potential can be kept, thus avoid between the color owing to being caused by the coupling of parasitic capacitance Uneven.

Additionally, according to (using latch cicuit 244 as polarity inversion portion 24_B) image element circuit of example 2 is than according to (making With inverter circuit 241) image element circuit of example 1 further advantageous in that, although circuit structure is the most complicated, still can preserve The signal potential that polarity has been inverted.

3. variation

Following situation is described, i.e. be three sub-pixels 20 in embodiment of above_R、20_GWith 20_BJointly arrange one Polarity inversion portion 24 (24_AOr 24_B).But, it is only for example, and present invention can apply to generally use selector in pixel The display device of driving method.Therefore, the polarity inversion portion as described in example is not essential to the invention.Optional Ground, for example, it is possible to share a polarity inversion portion 24 between the pixel (sub-pixel) more than four.

More specifically, in the liquid crystal indicator that can carry out colored display, for example, it is possible to two unit pixel Share (that is, between six sub-pixels) between (being each made up of red sub-pixel, green sub-pixels and blue subpixels) One polarity inversion portion 24.The pixel (sub-pixel) sharing unipolarity inversion portion 24 is the most, can reduce more many compositions liquid crystal Show panel 10_ACircuit block, thus be favorably improved display panels 10_AYield.

4. application examples

Above-mentioned liquid crystal indicator according to the present invention is applicable as spreading all over the various electronic equipments that all spectra uses Display device, is delivered to electronic equipment or the image of video signal produced in the electronic device or video with display.Such as, liquid Crystal device is applicable as the various electronic equipments shown in Figure 15 to Figure 19 G and (includes digital camera, individual's meter on knee The personal digital assistant of calculation machine, such as mobile phone and video camera) display device.

Various electronics is used to set according to the liquid crystal indicator of the present invention as spreading all over all spectra as it has been described above, use Standby display device contributes to more fine definition and the reduction of powder consumption of electronic equipment of electronic installation.That is, retouching from embodiment State it is clear that use the holding capacitor in each pixel as DRAM according to the liquid crystal indicator of the present invention, thus have Help simpler dot structure, therefore, it is possible to make pixel granular.Additionally, when using selector driving method in pixel, Can by assuring that due to caused by the coupling of parasitic capacitance affect multiple sub-pixels condition for these sub-pixels For identical keep color balance.For above reason, contribute to various electronics according to the liquid crystal indicator of the present invention and set The higher definition of standby display device and the colorrendering quality of improvement.

Liquid crystal indicator according to the present invention includes the liquid crystal indicator sealed with modular form.Such as, correspond to The display module of in these liquid-crystal apparatus has the sealing (not shown) around pixel array unit.This display module By use sealing as binding agent adhere to such as clear glass to being formed to portion.This is transparent can include to portion Light filter and protecting film, and farther include photomask.It should be noted that, the circuit part of FPC (flexible printed circuit board) is permissible It is arranged between external equipment and pixel array unit exchange signal and other information.

Will be given below applying the description of the instantiation of the electronic equipment of the present invention.

Figure 15 shows the perspective view of the outward appearance of the television set of the application present invention.According to should the television set of use-case include The video display screen portion 101 being made up of front panel 102, filter glass 103 and miscellaneous part.This television set is by using root Manufacture as video display screen portion 101 according to the display device of the present invention.

Figure 16 A and Figure 16 B shows the perspective view of the outward appearance of the digital camera of the application present invention.Figure 16 A is front view, Figure 16 B is rearview.According to the digital camera of use-case including flash light emission portion 111, display part 112, menu switch 113, shutter release button 114 and miscellaneous part.This digital camera is by using the display device according to the present invention as display part 112 manufacture.

Figure 17 shows the perspective view of the outward appearance of the laptop PC of the application present invention.According to should use-case Laptop PC includes being suitable to be manipulated to input text or the keyboard 122 of other information, be suitable to show the aobvious of image Show the miscellaneous part in portion 123 and main body 121.This laptop PC is by using the display according to the present invention to fill Put and manufacture as display part 123.

Figure 18 shows the perspective view of the video camera of the application present invention.According to the video camera of use-case including main part 131, be arranged on facial side surfaces to obtain the camera lens 132 of the image of object, shooting starts/shutdown switch 133, display part 134 and miscellaneous part.This video camera is to be manufactured as display part 134 according to the display device of the present invention by use.

Figure 19 A to Figure 19 G shows showing of the outward appearance of the personal digital assistant (such as mobile phone) of the application present invention Figure.Figure 19 A is the front view under open mode, and Figure 19 B is its side view, and Figure 19 C is the front view under closed mode, Figure 19 D Being left view, Figure 19 E is right view, and Figure 19 F is top view, and Figure 19 G is look up figure.According to should the mobile phone of use-case include Upper body 141, lower case 142, connecting portion (hinge in this example) 143, display 144, slave display 145, picture Lamp 146, photographing unit 147 and miscellaneous part.According to should the mobile phone of use-case be by using the display according to the present invention to fill Put and manufacture as display 144 and slave display 145.

The present invention is contained in the Japanese Priority Patent application JP 2010-submitted on June 24th, 2010 to Japan Office Theme disclosed in 144152, entire contents is hereby expressly incorporated by reference.

It will be appreciated by those skilled in the art that, require and other factors according to design, various amendment, group can be carried out Conjunction, sub-portfolio and deformation, as long as they are in the range of claims or its equivalent.

Claims

1. a liquid crystal indicator, including:

First switch element, for each pixel, described first switch element is that multiple sub-pixels of one pixel of composition are common Arranging, described first switch element has the first end being connected to holding wire；

Multiple second switch elements, for each pixel, arrange a described second switch element for each sub-pixel, described many Each pixel electrode being connected to one of the plurality of sub-pixel in individual second switch element and described first switch element Between second end；And

Drive division, is configured to sequentially switch on and off the plurality of second in section in the turn-on time of described first switch element and opens Close element, and first disconnect the last second switch element connected in order, then at the second switch of described last connection Preset time after element disconnects disconnects described first switch element after section so that owing to being coupling in institute by parasitic capacitance The condition affecting the plurality of sub-pixel controlling to cause at electrode stating switch element is phase for the plurality of sub-pixel With,

Wherein, the plurality of sub-pixel each includes capacity cell,

Wherein said first switch element does not have directly the connecting of described capacity cell being connected to each the plurality of sub-pixel Connect, and

The current potential that the described capacity cell of the most each the plurality of sub-pixel keeps is in the second switch unit of described last connection Described first switch element will not be increased up in time period after part disconnection disconnect.

Liquid crystal indicator the most according to claim 1, wherein,

Described pixel includes that polarity inversion portion, described polarity inversion portion are that the plurality of sub-pixel is arranged jointly, and be suitable to make by The polarity inversion of the signal potential that the capacity cell of the plurality of sub-pixel keeps, and the signal potential that polarity has been inverted Re-write described capacity cell.

Liquid crystal indicator the most according to claim 2, wherein,

Described first switch element is being suitable to write the described signal potential of reflection gray level the first behaviour of described capacity cell Connect under operation mode, and being suitable to read holding current potential that described capacity cell keeps, to utilize described polarity inversion portion to make described The polarity inversion of current potential and current potential polarity inverted re-write under the second operator scheme of described capacity cell disconnected Open, and

The plurality of second switch element, under described first operator scheme and described second operator scheme, is reading described electric capacity In the reading time period keeping current potential that element keeps, and at the current potential weight having utilized polarity inversion portion to make its polarity inversion Re-writing in the time period of newly written described capacity cell is connected.

Liquid crystal indicator the most according to claim 3, wherein,

Described polarity inversion portion includes the polarity being suitable to invert the signal potential kept by the capacity cell of the plurality of sub-pixel Inverter circuit.

Liquid crystal indicator the most according to claim 3, wherein,

Described polarity inversion portion includes the polarity being suitable to invert the signal potential kept by the capacity cell of the plurality of sub-pixel And keep the latch cicuit of the current potential that polarity inverted.

Liquid crystal indicator the most according to claim 4, wherein,

Described polarity inversion portion includes:

3rd switch element, is connected to the defeated of the other end of described first switch element and described inverter circuit or latch cicuit Entering between end, described 3rd switch element is suitable to disconnect under described first operator scheme, and in the second operation mode, Connect within the described reading time period, thus read the electricity kept by described capacity cell via the plurality of second switch element Position, and described current potential is supplied to described inverter circuit or the input of described latch cicuit；And

4th switch element, is connected to the other end and described inverter circuit or the described latch cicuit of described first switch element Outfan between, described 4th switch element be suitable under described first operator scheme disconnect, and described second operate mould Under formula, connect described re-writing in the time period, thus described anti-phase by having utilized via the plurality of second switch element Device circuit or described latch cicuit make the current potential of its polarity inversion write described capacity cell.

7. a driving method for liquid crystal indicator, described liquid crystal indicator includes: the first switch element, for each picture Element, described first switch element is that multiple sub-pixels of one pixel of composition are arranged jointly, and described first switch element has even It is connected to the first end of holding wire；And multiple second switch element, for each sub-pixel, one described second switch element is set, Each pixel electrode being connected to one of the plurality of sub-pixel in the plurality of second switch element and described first switch Between the other end of element, the plurality of sub-pixel each includes capacity cell, and described first switch element is not Having being directly connected to of described capacity cell being connected to each the plurality of sub-pixel, described driving method includes:

The plurality of second switch element is sequentially switched on and off in section in the turn-on time of described first switch element；And

First disconnect the last second switch element connected in order, then break at the second switch element in described last connection Preset time after opening disconnects described first switch element after section so that owing to being coupling in described switch by parasitic capacitance The condition affecting the plurality of sub-pixel controlling to cause at electrode of element is identical for the plurality of sub-pixel,

8. having an electronic equipment for liquid crystal indicator, described liquid crystal indicator includes:

Drive division, be configured to described first switch element be continuously turned on the time period in sequentially switch on and off the plurality of Two switch elements, and first disconnect the last second switch element connected in order, then in the second of described last connection Preset time after switch element disconnects disconnects described first switch element after section so that owing to being coupled by parasitic capacitance The condition affecting the plurality of sub-pixel controlling to cause at electrode at described switch element for the plurality of sub-pixel is Identical,

Wherein, the plurality of sub-pixel each includes capacity cell, and described first switch element does not have connection To being directly connected to of described capacity cell of each the plurality of sub-pixel, and