CN102298344B - Local hot point mitigating system based on FPGA dynamic partially reconfigurable technology - Google Patents

Abstract

The invention relates to a local hot point mitigating system based on FPGA (Field Programmable Gate Array) dynamic partially reconfigurable technology. In engineering applications, continuous high-temperature operation may cause damage on local functional regions of a FPGA embedded system and further cause system crash. In the system provided by the invention, a real-time operating system schedules tasks operating in the regions with excessive temperature to a reconfigurable region wither lower temperature in real time, a ring oscillator implements that each module in the embedded system detects own temperature, when the embedded system detects that own task operating modules have excessive temperature, the embedded system transmits excessive temperature interruption to an operating system via an interruption control module, and then, the operating system schedules a scheduling strategy task operating thereon to find the reconfigurable region matched with the regions with excessive temperature in size and schedule the reconfigurable tasks in the regions with excessive temperature to the reconfigurable regions with lower temperature. With the system provided by the invention, the problem of local excessive temperature in a FPGA embedded system is mitigated, power consumption of a FPGA chip is reduced and hardware life cycle of the FPGA chip is improved.

Description

A kind of hot localised points mitigation system based on FPGA dynamic part Reconfiguration Technologies

Technical field

The invention belongs to the embedded system field, be specifically related to a kind of field programmable gate array (FPGA) that prevents in operational process, a certain specific function of long-play zone causes regional area overheated and cause the system of FPGA regional area operation exception.

Background technology

Field programmable gate array (FPGA) has good programmable features, and it not only has travelling speed and the reliability of special IC, and has the dirigibility of general processor.Therefore have the characteristics such as high energy efficiency, low-power consumption, construction cycle be short based on the embedded system of FPGA, and can solve more complicated logic function along with continuous reduction, the FPGA integrated level of FPGA embedded system development cost is more and more higher, replace the ASIC product in a lot of occasions, be widely used in the fields such as radio communication, Aero-Space, consumer electronics, Industry Control, measurement test.But along with to the improving constantly of field programmable gate array (FPGA) performance requirement, by promoting the density of logical device in the FPGA, improve its travelling speed, increase capable the appointing of hardware of operation, the FPGA local temperature is risen rapider.FPGA device temperature rising meeting produces a series of bad impacts to FPGA equipment: 1) rising of FPAG temperature can cause the rapid rising of electricity leakage power dissipation, causes the rising of FPGA power consumption.2) rising of temperature reduces the serviceable life of 2 times of 10 ℃ of equipment operating temperature energy extension devices to the serviceable life of FPGA equipment tremendous influence being arranged also.

Yet for traditional embedded system, its hardware platform can not be changed, therefore a certain hardware capability module in the long-play embedded system finally can make the temperature of this hardware module constantly accumulate the regional extent that rises above the normal operation of FPGA equipment.The hot operation functional module that continues can cause the damage in FPGA embedded system local function zone, causes the whole system paralysis.Especially at complicated, rugged environment, such as the zone, deep-sea, outer space etc., FPGA device temperature are difficult to control more, and artificially also are difficult to the temperature of real-time checkout equipment in such environment, or the hardware of updating the equipment.Therefore the invention of this paper is used and is had great significance and actual use value.

Although the FPAG embedded system can be used static overall reconfigurable method, the bit stream file of the different placement-and-routings of programming, but make will require in this way whole system to quit work and again the programming time longer, this can reduce performance and the dirigibility of system greatly, and real-time more seldom arrives assurance.

Publication number is the dynamic local reconfigurable system that the patent of CN101788931A discloses a kind of real-time fault tolerance of hardware.

Summary of the invention

The objective of the invention is for the problems referred to above, propose a kind of hot localised points mitigation system of the dynamic part Reconfiguration Technologies based on FPGA.The present invention uses the dynamic part Reconfiguration Technologies, in the situation that do not interrupt the FPGA operation for embedded system, and regional to the lower restructural of temperature by real time operating system Real-Time Scheduling excess Temperature area operation task.Realize that by using ring oscillator modules in the FPGA embedded system is to the detection of self temperature, when the excess Temperature of discovery self task module operation area, send the excess Temperature interruption by interrupting control module to operating system, operating system can be called the scheduling strategy task of operation on it, seek the restructural zone that is complementary with the excess Temperature area size, the reconfigurable task in scheduling excess Temperature zone is to the lower restructural zone of temperature, thereby relax the too high problem of local temperature in the FPGA embedded system, reduce the fpga chip power consumption, improve the hardware life cycle of fpga chip.

Overall technological scheme of the present invention:

Embedded system can be divided into each functional module according to the function difference that realizes, each hardware capability module can be write structure by hardware description language and be described its realization logic in detail, last each functional module entity is by statement and instantiation in top document, the port of describing between each functional module connects, and realizes building based on the embedded system hardware platform of FPGA.FPGA embedded system in native system has been used the dynamic part reconfigurable function, so this hardware platform can be divided into: static region and dynamic reconfigurable zone two parts.In the hardware static region, comprise the interruption control module, RSIC embedded central processing unit, internal control interface configuration module.Place the hardware reconfiguration task that need to be scheduled in the dynamic reconfigurable zone.Transplant the operation that real time operating system is used for controlling whole embedded system at the embedded system hardware platform.

Described RSIC embedded central processing unit is the hard nucleus management device that is embedded on the FPGA embedded system, is used for explaining instruction and the deal with data of embedded system.Connect respectively each hardware capability module by the CoreConnect bus, such as serial port module, Bus Macro module, internal control interface configuration module.

Described serial port module is used for communicating by letter between embedded system and the computing machine.

Described Bus Macro module is used for connecting static region and dynamic reconfigurable zone, realizes communication between the two.

Described internal control interface configuration module is used for the restructural bit stream file of reading external memory, and uses restructural bit stream file to realize the configuration of hardware bit stream.

Described real time operating system is the operating system that is implanted on the RSIC embedded central processing unit, and on real time operating system running temperature polling tasks and two software tasks of scheduling strategy task.Reception is from the look-at-me of interrupt module, traffic control strategy task.

Described temperature polling tasks is by calling the real time operating system physical layer interface, the frequency that the ring oscillator that inquiry embeds in reconfigurable module is exported, obtain the temperature of reconfigurable module by respective formula, and the temperature of each reconfigurable module is kept in the thermometer for scheduling strategy.

Described ring oscillator is the hardware module that is embedded in the reconfigurable task module, and its frequency can change thereupon in temperature variation, indirectly draws the temperature of reconfigurable module by the frequency that obtains ring oscillator.When excess Temperature, send temperature alarm to interrupting control module.

The temperature of each reconfigurable module in the resulting thermometer of described scheduling strategy task inquiry temperature polling tasks, the scheduling strategy of formulating according to the user, with the dynamic reconfigurable task scheduling of excess Temperature in the relatively low restructural zone of temperature.

Described interruption control module is used for receiving the temperature alarm from reconfigurable module, and sends interrupt request to real time operating system.

The present invention can be applicable in the various FPGA embedded systems with dynamic part reconfigurable function, is the scheduling of practical function module design task, corresponding reconfigurable module bit stream file in each corresponding a plurality of embedded system in restructural zone.Use between the close reconfigurable module of hardware logic resource and can realize transposing by the dynamic part Reconfiguration Technologies.Adopt real time operating system, use and interrupt the real-time that control module improves system, by the reconfigurable module operation area of scheduling decision task scheduling excess Temperature, reduce temperatures at localized regions, prolong the life cycle of FPGA embedded system hardware, improve system reliability.System of the present invention uses dynamic part Reconfiguration Technologies scheduling reconfigurable module, has higher real-time, and also can be used for upgrading hardware module task code realization FPGA embedded system renewal upgrading.

Description of drawings

Fig. 1 dynamic part restructural hot localised points mitigation system block diagram;

Link block diagram between Fig. 2 internal system modules

Fig. 3 system hardware platform bit stream product process figure

Fig. 4 fpga chip structure and schematic layout pattern

Fig. 5 operating system software operational flow diagram;

Fig. 6 software and hardware merges process flow diagram.

Embodiment

Below in conjunction with accompanying drawing the present invention is further analyzed and introduces, by realizing the labor embodiment.

The present invention adopts FPGA dynamic part Reconfiguration Technologies, can dynamically change the hardware task region of operation under the state of system's operation, can effectively solve the too high problem of operation task place temperatures at localized regions.Operation hardware task by the scheduling excess Temperature is regional to the relatively low restructural of temperature, thereby effectively reduces the too high problem of local reconfigurable regional temperature.Adopt this method can greatly improve the processing capability in real time of system, relax temperatures at localized regions in the situation that do not interrupt operation for embedded system.

The present invention is a kind of based on the reconfigurable hot localised points mitigation system of dynamic part, and this example is developed and designed at the Virtex-II of Xilinx Pro platform.This platform is supported the realization of dynamic part Reconfiguration Technologies, and its FPGA inside has been embedded in two Powerpc405 RSIC processors, can utilize the CoreConct bus standard technology a plurality of solid nuclears of link (IP Core) to make based on dynamic part Reconfigurable System Design and the application of SOPC more flexible, in the embedded development external member of this platform with the recursive utilization of IP kernel upgrade, thereby can shorten the construction cycle of system, upgrade-system hardware is saved human resources and cost of development greatly easily.The CoreConnect bus specification that uses in the present invention comprises three kinds of bus architectures and two conversion bridgings, it is respectively: PLB bus (Processor Local Bus, the processor local bus), OPB bus (On-chip Peripheral Bus, the On-Chip peripheral bus), DRC bus (Device Control Register Bus, device control register bus) and PLB2OPB Bridge and OPB2DCR Bridge.

The present embodiment is to develop and design at the Virtex-II of Xilinx Pro platform, its system framework as shown in Figure 1, this enforcement can divide following 4 parts generally:

1) processor system part: comprising hardware PowerPC405 processor and software μ C/OS-II operating system;

2) restructural zone: adopt in this example 4 restructural zones to place the hardware capability module for the FPGA embedded system, its number can be decided according to concrete design;

3) interrupt control module: this module receives the temperature alarm from reconfigurable module, sends excess Temperature to real time operating system and interrupts, and real time operating system is called the scheduling strategy task, realizes that local temperature relaxes;

4) scheduling strategy module: this module comprises realization system hot localised points and relaxes the algorithm that adopts and concrete operation strategy, obtains the temperature of reconfigurable module by calling the temperature polling tasks.

5) temperature poll module: by reading the frequency output of ring oscillator in the reconfigurable module, be converted to the reconfigurable module temperature through formula, and the temperature value of each reconfigurable module is put into thermometer.

Implementation step and explanation:

1. utilize embedded development external member (EDK) design system hardware platform

Be the concrete link between the inside IP kernel of system architecture of the present invention as shown in Figure 2, select the PowerPC405 processor, control all IP kernel modules as central processing unit.Adopt Virtex-II Pro development board to demonstrate as an example platform, use the IP kernel that carries in the Xilinx embedded development external member to design, the concrete IP kernel that uses comprises: PLB_v34 bus IP Core (hardware version 1.02.a), OPB_v20 IP kernel (hardware version 1.10.a), PLB_BRAM controller IP kernel (hardware version 1.00.b, software-driven version 1.00.a), OPB_HWICAP IP kernel (hardware version 1.00.b, software-driven version 1.00.c), PLB2OPB bridge IP kernel (hardware version 1.01.a, software-driven version 1.00.a), OPB_SYSTEMACE IP kernel (hardware version, 1.00.c, software-driven version 1.01.a), OPB_INTC interruptable controller IP kernel (hardware version 1.00.c, software-driven version 1.00.c), JTAG IP kernel (hardware version 2.00.a, software-driven version 1.00.a), OPB_UARTLITE serial communication nuclear IP kernel (hardware version 1.00.b, software-driven version 1.02.a).

The IP kernel in the embedded development external member, also comprise as shown in Figure 2 part reconfigurable module IP kernel, this IP kernel is the function that the user realizes according to embedded functional module needs, uses hardware description language to write, by using ISE Software Create IP kernel module, hang on the OPB bus.

2. system hardware platform bit stream product process

After embedded system is divided into a plurality of functional modules, its functional module is put into the restructural zone, as reconfigurable module, other logics connect control section as static region, do not need the part revised when namely moving in system, the connection between static region and the restructural zone realizes by Bus Macro.In the FPGA embedded system development platform, pass through IP kernel connected mode as shown in Figure 2, in the embedded development external member, connect each IP kernel module, generate top net list file (top.ngc).The restructural zone entity that in the top net list file, comprises static region and instantiation.Because the logic function that restructural zone entity is realized is variable, so it is placed in the top document as a black box, restructural zone entity and static region are just described by being connected between the Bus Macro port.Reconfigurable function module in the FPGA embedded system is write by hardware description language Verilog, generates reconfigurable function module net meter file by compiling in ISE 9.1.02I.The bus macro netlist is provided by Xilinx official, selects suitable net meter file busmacro_xc2vp_l2r_async_enable_narrow.nmc, busmacro_xc2vp_l2r_async_enable_narrow.nmc according to development platform Virtex-II Pro.System hardware platform bit stream product process as shown in Figure 3.

User restraint file (ucf) in Fig. 3 is realized temporal constraint, the pin constraint.Employed time constraints in the FPGA embedded system hardware platform, the pin constraint of OPB_SYSTEMACE IP kernel, the pin constraint of OPB_UARTLITE serial communication nuclear IP kernel etc. is all described in the user restraint file.

By using planahead software, the reconfigurable function module net meter file that will be produced by top net list file and the ISE of embedded development external member (EDK) generation, the user restraint file that Bus Macro net meter file and user oneself write generates static region NCD file and reconfigurable module NCD file by translation, mapping, the system architecture layout signal that generates generates overall static bit stream file and part restructural bit stream file by placement-and-routing as shown in Figure 4 again.Comprise static region logic and initial reconfigurable module in the overall situation bit stream file.Initial reconfigurable module namely is the reconfigurable module of restructural zone initial placement.

3. the transplanting of μ C/OS-II real time operating system and application programming

μ C/OS-II is the disclosed real-time preemptive type embedded OS of source code, and its most of code adopts the C language compilation, and therefore good transplantability is arranged.When transplanting μ C/OS-II operating system, only need to revise OS_CPU.H, OS_CPU_C.C, OS_CPU_A, three files of ASM according to the hardware platform PowerPC405 processor of transplanting.

The OS_CPU.H file is transplanted: the growing direction that 1) storehouse is set.2) definition data type: because different processors has different word lengths, therefore use the data type that defines to guarantee the good transplantability of file.3) interrupt macro definition: need to be in kernel in the protection critical section disabled interrupt, avoid μ C/OS-II critical section code to be subject to the destruction of multitask or interrupt service subroutine.

The OS_CPU_C.C file is transplanted: the main initialization task stack architecture of realizing in this file, in function OSTaskStkInit (), realize.Although wherein also comprise several interface functions, only need in practice statement and do not require necessarily to comprise code.

OS_CPU_A, ASM file are transplanted: need to write 4 assembly language function: OSStartHighRdy (), OSCtxSw (), OSIntCtxSw (), OSTickISR () in presents.OSStartHighRdy () function is responsible for moving high-priority task, by obtaining the highest task stack pointer of priority, recovers all registers from the storehouse of new task, returns from interrupt instruction at last.OSCtxSw () is pressed in the storehouse of current task by the register with current task, and the stack pointer of current task is saved in the current task controll block, then calls high-priority task.It need not OSTickISR () the current task register is preserved realization task switch operating.OSTickISR () provides periodically clock source realization time delay and overtime.

In μ C/OS-II operating system two application tasks are arranged, as shown in Figure 1.The temperature polling tasks is inquired about the temperature of each hardware reconfiguration module by polling mode, and the temperature Query Result is placed in the thermometer.In this example, dispatching algorithm consider in each restructural zone task following may working time length and thermometer in these two factors of temperature regime in the regional, which with this reconfigurable task module minimum reconfigurable task module exchange relative to temperature that decides excess Temperature in the scheduling thermometer, then continue to carry out.The operating system software operational scheme as shown in Figure 5.

4. hardware bit stream and software task merge

The software executable (.elf) that hardware overall situation bit stream file (.bit) by EDK, ISE, planahead Software Create and μ C/OS-II operating system and application program generate after PowerPC405 transplants compiling merges generation and finally can download to the bit stream file that development board moves.Use the EDK shell-command to merge hardware overall situation bit stream file and the last download bit stream file (.bit) of software executable generation.Download bit stream file generated flow process as shown in Figure 6.

Claims (1)

1. hot localised points mitigation system based on FPGA dynamic part Reconfiguration Technologies is characterized in that:

Transplant real time operating system at the RSIC embedded central processing unit, utilize CoreConnect bussing technique disconnecting control module, internal control interface configuration module, serial ports UART module; By placement and the management of functional module in the scheduling strategy task control FPGA embedded system of moving in real time operating system, call the temperature polling tasks, realize the monitoring to the restructural regional temperature; Use the dynamic part Reconfiguration Technologies that the embedded system hardware platform can be divided into: static zones and four dynamic reconfigurable zones; In static region, comprise the interruption control module, RSIC embedded central processing unit, internal control interface configuration module; Place the hardware reconfiguration task that need to be scheduled in the dynamic reconfigurable zone;

Described RSIC embedded central processing unit is the hard nucleus management device that is embedded on the FPGA embedded system, is used for explaining instruction and the deal with data of embedded system; Connect respectively each hardware capability module by the CoreConnect bus, the hardware capability module comprises serial port module, Bus Macro module, internal control interface configuration module;

Described serial port module is used for communicating by letter between embedded system and the computing machine;

Described Bus Macro module is used for connecting static region and dynamic reconfigurable zone, realizes communication between the two;

Described internal control interface is used for the restructural bit stream file of reading external memory, and uses restructural bit stream file to realize the configuration of hardware bit stream;

Described real time operating system is the operating system that is implanted on the RSIC embedded central processing unit, and on real time operating system running temperature polling tasks and two software tasks of scheduling strategy task; Real time operating system receives the look-at-me from interrupt module, traffic control strategy task;

Described temperature polling tasks is by calling the real time operating system physical layer interface, the frequency that the ring oscillator that inquiry embeds in reconfigurable module is exported, obtain the temperature of reconfigurable module by respective formula, and the temperature of each reconfigurable module is kept in the thermometer for scheduling strategy;

Described ring oscillator is the hardware module that is embedded in the reconfigurable task module, and its frequency can change thereupon in temperature variation, indirectly draws the temperature of reconfigurable module by the frequency that obtains ring oscillator; When excess Temperature, send temperature alarm to interrupting control module;

The temperature of each reconfigurable module in the resulting thermometer of described scheduling strategy task inquiry temperature polling tasks, the scheduling strategy of formulating according to the user, with the dynamic reconfigurable task scheduling of excess Temperature in the relatively low restructural zone of temperature;

Described interruption control module is used for receiving the temperature alarm from reconfigurable module, and sends interrupt request to real time operating system.

Images