CN102280431A - Semiconductor encapsulation with protective layer and manufacturing method thereof - Google Patents
Semiconductor encapsulation with protective layer and manufacturing method thereof Download PDFInfo
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- CN102280431A CN102280431A CN2011102172988A CN201110217298A CN102280431A CN 102280431 A CN102280431 A CN 102280431A CN 2011102172988 A CN2011102172988 A CN 2011102172988A CN 201110217298 A CN201110217298 A CN 201110217298A CN 102280431 A CN102280431 A CN 102280431A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor encapsulation with a protective layer and a manufacturing method thereof. The semiconductor encapsulation comprises a carrier, a chip, a plurality of weld lines, an encapsulation gel and a protective layer. The carrier is provided with a plurality of first pins and at least one second pin, each first pin is provided with a first inner pin portion and a first outer pin portion; and the second pin is provided with a second inner pin portion, a second outer pin portion and an extension portion. The chip is configured on the carrier. The weld lines are configured among the chip, the first inner pin portion and the extension portion. The encapsulation gel wraps the chip, the weld lines, the first inner pin portion, the second inner pin portion and the extension portion, and a lower surface of the extension portion is exposed. The first outer pin portion and the second outer pin portion protrude from the lower surface of the encapsulation gel. The protective layer covers the lower surface of the encapsulation gel and the lower surface of the extension portion.
Description
Technical field
The present invention relates to a kind of semiconductor packages and preparation method thereof, and particularly relates to a kind of square flat non-pin (Quad Flat No Lead, QFN) encapsulation and preparation method thereof.
Background technology
Semiconductor packaging includes many encapsulation forms, the square flat non-pin encapsulation that wherein belongs to quad flat package series has short signaling path and comparatively faster signal transmission speed, therefore the square flat non-pin encapsulation is applicable to the Chip Packaging of high-frequency transmission (for example radio frequency band), and encapsulates one of main flow of kenel for hanging down pin position (low pin count).
In the manufacture method of square flat non-pin encapsulation, earlier with a plurality of chip configuration on nead frame (leadframe).Then, make these chips be electrically connected to nead frame by many bonding wires.Afterwards, come covered section nead frame, these bonding wires and these chips by packing colloid.Then, obtain a plurality of square flat non-pin encapsulation by cutting (punching) or sawing (sawing) singulation said structure.At last, provide the printed circuit board (PCB) that is coated with tin cream, by the surface adhering technology (surface mounting technology, SMT) with resulting square flat non-pin welded encapsulation to printed circuit board (PCB).
Yet,, therefore be exposed to the outer nead frame of packing colloid and easily produce oxidative phenomena because packing colloid is not to coat nead frame fully.Moreover, in the process that forms packing colloid, the joint that packing colloid contacts with nead frame is easy to generate not driving fit and space, so that moisture infiltrates in the encapsulating structure soon from here, and then the reliability and the useful life of reducing whole square flat non-pin encapsulation.Therefore, how promoting effectively that the whole reliability of square flat non-pin encapsulation just becomes is that preceding industry is desired most ardently one of important topic of solution.
Summary of the invention
The invention provides a kind of semiconductor packages and preparation method thereof, have the preferred construction reliability.
The present invention proposes a kind of semiconductor packages, comprises carrier, chip, many bonding wires, packing colloid and protective layers.Carrier has a plurality of first pins and at least one second pin.Each first pin has in first the pin portion and the first outer pin portion.Second pin has pin portion, second outer pin and the extension in second.Chip configuration is on carrier.These bonding wires are disposed between chip, these first interior pin portions and the extension.Packing colloid coating chip, these bonding wires, these pin portion and extensions in pin portions, second in first, and expose the lower surface of extension.The lower surface of the outstanding packing colloid of these the first outer pin portions and the second outer pin portion.Protective layer covers the lower surface of packing colloid and the lower surface of extension.
The present invention also proposes a kind of manufacture method of semiconductor packages, and it comprises the steps.Encapsulation unit is provided.Encapsulation unit comprises carrier, chip, many bonding wires and packing colloid.Carrier has a plurality of first pins and at least one second pin.Each first pin has in first the pin portion and the first outer pin portion.Second pin has pin portion, second outer pin portion and the extension in second.Chip configuration is on carrier.These bonding wires are disposed between chip, these first interior pin portions and the extension.Packing colloid coating chip, these bonding wires, these pin portion and extensions in pin portions, second in first, and expose the lower surface of extension.Form protective layer on the lower surface of packing colloid.Protective layer covers the lower surface of packing colloid and the lower surface of extension.
The present invention also proposes a kind of semiconductor packages, and it comprises chip carrier, at least one pin, chip, bonding wire, packing colloid and protective layer.Pin adjacent chips seat, wherein pin has interior pin portion, outer pin portion and extension.Chip configuration is on chip carrier.Bonding wire is disposed between chip and the extension.Packing colloid coating chip, chip carrier, bonding wire, interior pin portion and extension, and expose the lower surface of extension, the lower surface of its outstanding packing colloid of China and foreign countries pin portion.Protective layer covers the lower surface of extension.
Based on above-mentioned because semiconductor packages of the present invention has protective layer, wherein protective layer cover the lower surface of packing colloid and these soldered balls to small part, therefore can improve adhesion between packing colloid and the carrier by this protective layer.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the generalized section of a kind of semiconductor packages of embodiments of the invention.
Fig. 2 A to Fig. 2 C is a kind of generalized section that forms soldered ball and protective layer of the embodiment of the semiconductor packages of Fig. 1.
Fig. 3 A to Fig. 3 B is a kind of generalized section that forms the local step of soldered ball and protective layer of another embodiment of the semiconductor packages of Fig. 1.
Fig. 4 A to Fig. 4 B is a kind of generalized section that forms the local step of soldered ball and protective layer of the another embodiment of the semiconductor packages of Fig. 1.
Fig. 5 is a kind of generalized section that forms the local step of soldered ball and protective layer of an embodiment again of the semiconductor packages of Fig. 1.
Fig. 6 is a kind of generalized section that forms the local step of soldered ball and protective layer of an embodiment again of the semiconductor packages of Fig. 1.
Fig. 7 A and Fig. 7 B are the generalized section that semiconductor packages 300 is engaged to circuit board.
Fig. 8 is a kind of partial cutaway schematic that forms the local step of soldered ball and protective layer of the semiconductor packages of an embodiment more of the present invention.
Fig. 9 is engaged to the generalized section of circuit board for the semiconductor packages of Fig. 8.
Figure 10 is the generalized section of a kind of semiconductor packages of another embodiment of the present invention.
Figure 11 is the generalized section of a kind of semiconductor packages of another embodiment of the present invention.
Figure 12 is the generalized section of a kind of semiconductor packages of another embodiment of the present invention.
Description of reference numerals
10: circuit board 12: joint sheet
14,24: scolder
100,200,300,400,500,600,700: semiconductor packages
110: encapsulation unit 110 ': encapsulant matrix
112: carrier 113 ', 113 ", 113 ' ": pin
113a: the interior pin 113b of portion: outer pin portion
113c: interior composition surface 113d: outer engagement face
113e: flare inclined- plane 113f, 113g: extension
113h, 113i: lower surface 114: chip
115: chip carrier 115 ': depression
115 ": central part 115 ' ": depressed part
116: bonding wire 117: colloid
118: packing colloid 118a: lower surface
119a: first coat of metal 119b: second coat of metal
120: soldered ball 130,130 ', 230: protective layer
130a, 130b: protective material 130s: lower surface
230a:A stage thermosetting resin protective material
Embodiment
Please refer to the generalized section of Fig. 1 for a kind of semiconductor packages of embodiments of the invention.Semiconductor packages 100 comprises encapsulation unit 110, a plurality of soldered ball 120 and protective layer 130.Specifically, encapsulation unit 110 comprises carrier 112, chip 114, many bonding wires 116 and packing colloid 118.
Pin 113 ' is general expression (normal type), pin 113 in the present embodiment " be fan-in formula (fan-in type) and pin 113 ' " be fan-out formula (fan-out type).Fan-in formula pin 113 wherein " comprise that also extension (extending portion) 113f extends outward, that is around encapsulation, extend.Fan-out formula pin 113 ' " also comprise extension 113g toward interior extension, that is extend toward chip 114.
These bonding wires 116 are disposed at chip 114 and pin 113 ', 113 ", 113 ' " between, its chips 114 sees through these bonding wires 116 and these pins 113 ', 113 ", 113 ' " electrically connect.In general expression pin 113 ' aspect, bonding wire 116 is positioned on the 113a of pin portion with the contact of pin 113 ', and at these fan-in formula pins 113 " and these fan-out formula pins 113 ' " aspect, bonding wire 116 and pin 113 ", 113 ' " contact be positioned on extension 113f and the 113g.
Packing colloid 118 coating chips 114, these bonding wires 116 with these in the 113a of pin portion, and expose outer engagement face 113d and the flare inclined-plane 113e of these outer pin 113b of portion.In addition, the encapsulation unit 110 of present embodiment can also comprise first coat of metal 119a and second coat of metal 119b, wherein first coat of metal 119a is disposed on the upper surface of these interior composition surface 113c and chip carrier 115, and second coat of metal 119b is disposed on the lower surface of these outer engagement face 113d and chip carrier 115.The material of first coat of metal 119a can be selected from the group that gold (Au), palladium (Pd), tin (Sn), silver (Ag) and combination thereof are constituted.The material of second coat of metal 119b can be selected similar or be different from the material of first coat of metal 119a.
These soldered balls 120 are disposed at respectively on these outer engagement faces 113d of the outer pin 113b of portion, coat second coat of metal 119b and flare inclined-plane 113e.One or more soldered balls 120 are also configurable in the lower surface of chip carrier 115, coat or partly coat this lower surface fully.
Because the semiconductor packages 100 of present embodiment has protective layer 130; wherein protective layer 130 cover the lower surface 118a of packing colloids 118 and these soldered balls 120 to small part, therefore can improve adhesion between packing colloid 118 and the carrier 112 by this protective layer 130.Moreover, because also can covering these, protective layer 130 is exposed to lower surface 113h outside these soldered balls 120 and the packing colloid 118 and 113i to avoid oxidation, therefore can effectively improve the reliability of semiconductor packages 100.
Below will cooperate Fig. 1 and Fig. 2 A to Fig. 2 C to describe the manufacture method of semiconductor packages 100 in detail.In this mandatory declaration is that following embodiment continues to use the element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content.Explanation about clipped can be with reference to previous embodiment, and following embodiment no longer repeats to give unnecessary details.
Fig. 2 A to Fig. 2 C is a kind of generalized section that forms soldered ball and protective layer of the embodiment of the semiconductor packages 100 of Fig. 1.For convenience of description, the encapsulation unit 110 that Fig. 2 A to Fig. 2 C is illustrated is to be to put upside down setting for the encapsulation unit 110 of Fig. 1.
With reference to figure 2A, at first, provide the encapsulant matrix (a packaged matrix of the packaged units) 110 ' that comprises a plurality of encapsulation units 110 (only schematically illustrating one among Fig. 2 A).Encapsulation unit 110 comprises carrier 112, chip 114, many bonding wires 116, packing colloid 118, first coat of metal 119a and second coat of metal 119b.Carrier 112 has a plurality of pins 113 ', 113 ", 113 ' ".Each pin 113 ' (or pin 113 ", 113 ' ") has the interior pin 113a of portion, be connected in the 113a of pin portion the outer pin 113b of portion, be positioned at composition surface 113c on the 113a of pin portion, be positioned at outer engagement face 113d on the outer pin 113b of portion and the flare inclined-plane 113e of connection outer engagement face 113d.Chip 114 is disposed on the carrier 112.These bonding wires 116 are disposed at chip 114 and these pins 113 ', 113 ", 113 ' " between, its chips 114 sees through these bonding wires 116 and these pins 113 ', 113 ", 113 ' " electrically connect.Packing colloid 118 coating chips 114, these bonding wires 116 with these in the 113a of pin portion, and expose outer engagement face 113d and the flare inclined-plane 113e of these outer pin 113b of portion.First coat of metal 119a is disposed on the upper surface of these interior composition surface 113c and chip carrier 115, and second coat of metal 119b is disposed on the lower surface of these outer engagement face 113d and chip carrier 115.
With reference to figure 2B, form a plurality of soldered balls 120 on the second metal level 119b on these outer engagement faces 113d, wherein these soldered balls 120 coat these flare inclined-planes 113e of these outer engagement face 113d and these general expression pins 113 ', and expose these fan-in formula pins 113 " and these fan-out formula pins 113 ' " these extensions 113f and lower surface 113h and the 113i of 113g.The formation method of a plurality of soldered balls 120 is wicking technology (dip soldering process), paste solder printing technology (solder printing process) or electrodeless plating technology for example.
Please refer to Fig. 2 C; after forming these soldered balls 120; distribute (dispense) on the lower surface 113h and 113i of lower surface 118a, the pin extension 113f of packing colloid 118 and 113g protective material 130a, and form protective layer 130 around these soldered balls 120 and expose the part of each soldered ball 120.It for example is the surface that spin coating (spinning), spraying (spraying) or roller coating (roller coating) mode are coated on the integral surface and the soldered ball 120 of encapsulation unit 110 that protective material 130a can adopt; owing to below the viscosity of protective material 130a is controlled to a certain degree, expose the top (upper portion) of each soldered ball 120 so protective material 130a can be subjected to gravity effect to be deposited to the lower on encapsulation unit 110 surfaces.At this moment, protective layer 130 cover the lower surface 113h of lower surface 118a, the pin extension 113f of packing colloids 118 and 113g and 113i and each soldered ball 120 to small part.Particularly, the lower surface 130s of protective layer 130 presents curved surface or concave shape between soldered ball 120, and the thickness of protective layer 130 is thick away from soldered ball 120 places near soldered ball 120 places ratio.In this, protective material 130a for example is abietic resin (rosin resin), scaling powder.
At last, can adopt for example is laser or cutter, and cutting encapsulant matrix 110 ' and protective layer 130 are to form semiconductor encapsulation 100 at least.
Below will utilize a plurality of embodiment to illustrate and form these soldered balls 120 and protective layer 130,130 ' making step.
Fig. 3 A to Fig. 3 B is a kind of generalized section that forms the local step of soldered ball and protective layer of another embodiment of the semiconductor packages 100 of Fig. 1.For convenience of description, the encapsulation unit 110 that Fig. 3 A to Fig. 3 B is illustrated is to be to put upside down setting for the encapsulation unit 110 of Fig. 1.
Please refer to Fig. 3 A; present embodiment forms the making step of these soldered balls 120 and protective layer 130 similar in appearance to the foregoing description; its difference is: after the second metal level 119b of these soldered balls 120 of formation on these outer engagement faces 113d of Fig. 2 B goes up, adopt aforesaid method coating protective material 130a with the integral surface of covering encapsulant matrix 110 ' and the surface of these soldered balls 120.
Please refer to Fig. 3 B; heated protective material 130a descends its viscosity; protective material 130a can be subjected to lower that gravity effect is deposited to these encapsulation unit 110 surfaces exposing the part of each soldered ball 120 afterwards, and form protective layer 130 cover the lower surface 113h of lower surface 118a, the pin extension 113f of packing colloids 118 and 113g and 113i and each soldered ball 120 to small part.
At last, cutting encapsulant matrix 110 ' and protective layer 130 are to form semiconductor encapsulation 100 at least.
Fig. 4 A to Fig. 4 B is a kind of generalized section that forms the local step of soldered ball and protective layer of the another embodiment of the semiconductor packages 100 of Fig. 1.For convenience of description, the encapsulation unit 110 that Fig. 4 A to Fig. 4 B is illustrated is to be to put upside down setting for the encapsulation unit 110 of Fig. 1.
Please refer to Fig. 4 A; present embodiment forms the making step of these soldered balls 120 and protective layer 130 similar in appearance to the foregoing description; its difference is: the encapsulant matrix 110 ' that comprises a plurality of encapsulation units 110 in providing of Fig. 2 A afterwards; coating protective material 130a is to cover the lower surface 118a of second coat of metal 119b, these outer pin 113b of portion and flare inclined-plane 113e, pin extension 113f and 113g lower surface 113h and 113i and packing colloid 118, and wherein protective material 130a is abietic resin or scaling powder.
Please refer to Fig. 4 B; use is planted ball mode (ball attachment) these soldered balls 120 corresponding these outer pin 113b of portion is arranged on the protective material 130a; heated protective material 130a descends its viscosity afterwards; these soldered balls 120 are sunk among the protective material 130a and with the outer pin 113b of portion by gravity effect to contact; the lasting heating so that these soldered balls 120 reflux (reflow) and coat the flare inclined-plane 113e that second coat of metal 119b reaches the outer pin 113b of portion, and form the part that protective layer 130 centers on these soldered balls 120 and exposes each soldered ball 120.
At last, cutting encapsulant matrix 110 ' and protective layer 130 are to form semiconductor encapsulation 100 at least.
Please refer to a kind of generalized section that form the local step of soldered ball and protective layer of Fig. 5 for the semiconductor packages of an embodiment more of the present invention.Present embodiment and the foregoing description difference are: the encapsulant matrix 110 ' that comprises a plurality of encapsulation units 110 in providing of Fig. 2 A afterwards; coating protective material 130a is with the lower surface 113h that covers second coat of metal 119b, these outer pin 113b of portion and flare inclined-plane 113e, pin extension 113f and 113g and the lower surface 118a of 113i and packing colloid 118, and wherein protective material 130a is abietic resin or scaling powder.Viscosity by control protective material 130a is below to a certain degree; or heated protective material 130a descends its viscosity, exposes the top (upper portion) of each outer pin 113b of portion so protective material 130a can be subjected to gravity effect to be deposited to the lower on encapsulation unit 110 surfaces.At this moment, protective layer 130 covers lower surface 118a, pin extension 113f and the lower surface 113h of 113g and the part flare inclined-plane 113e of 113i and outer engagement face 113d of packing colloid 118.
At last, cutting encapsulant matrix 110 ' and protective layer 130 are to form semiconductor encapsulation 200 at least.
Please refer to a kind of generalized section that form the local step of soldered ball and protective layer of Fig. 6 for the semiconductor packages of an embodiment more of the present invention.Present embodiment and the foregoing description difference are: after the second metal level 119b of these soldered balls 120 of formation on these outer engagement faces 113d of Fig. 2 B went up, adopting for example was that spin coating, spraying or roller coating method coating A stage thermosetting resin protective material 230a are to cover integral surface and these soldered balls 120 of encapsulation unit 110.Adding curing process afterwards again makes protective material 230a convert lower surface 118a, the pin extension 113f of B stage thermoset resin material formation protective layer 230 covering packing colloids 118 and lower surface 113h and 113i and each soldered ball 120 of 113g to.It for example is that lamination (lamination) mode will be integral surface and these soldered balls 120 formation protective layers 230 that B stage protective material 230a covers encapsulation unit 110 that other execution mode also can adopt.
At last, cutting encapsulant matrix 110 ' and protective layer 230 are to form semiconductor encapsulation 300 at least.
Please refer to Fig. 7 A and Fig. 7 B is the generalized section that semiconductor packages 300 is engaged to circuit board.Semiconductor packages 300 is positioned on the circuit board 10 with a plurality of joint sheets 12, wherein on these joint sheets 12 selectively (optionally) dispose a plurality of scolders 14.Then; apply heat and pressure on the back side of semiconductor packages 300; because protective layer 230 is B stage characteristic and can be heated softening; after being heated, temporarily be converted to the A stage; that is present the commitment of thermosetting resin reaction; this material still can fusion and be dissolved in solvent or fluid in, its outward appearance presents liquid state.The protective layer 230 that is converted to the A stage has good plasticity; under the effect of pressure; it can fluidly redistribute and soldered ball 120 can be squeezed easily open the protective layer 230 that is the A stage and be contacted with these scolders 14 then; continue heating so that these soldered balls 120 reflux with scolder 14 and coat joint sheet 12; and the complete slaking of protective layer 230 meetings is to the C stage; that is be the terminal stage of thermosetting resin reaction, this material can not fusion and dissolving, and its outward appearance presents solid-state.So far finish engaging of semiconductor packages 300 and circuit board 10.
Please refer to a kind of partial cutaway schematic that form the local step of soldered ball and protective layer of Fig. 8 for the semiconductor packages of an embodiment more of the present invention.Present embodiment and the foregoing description difference are: the encapsulant matrix 110 ' that comprises a plurality of encapsulation units 110 in providing of Fig. 2 A afterwards; coating B stage thermosetting resin protective material 230a covers the integral surface of encapsulant matrix 110 ', covers the lower surface 113h of second coat of metal 119b, these outer pin 113b of portion and flare inclined-plane 113e, pin extension 113f and 113g and the lower surface 118a of 113i and packing colloid 118 to form protective layer 230.
At last, cutting encapsulant matrix 110 ' and protective layer 230 are to form semiconductor encapsulation 400 at least.
Please refer to Fig. 9 is engaged to circuit board for the semiconductor packages 400 of Fig. 8 generalized section.Semiconductor packages 400 is positioned on the circuit board 10 with a plurality of joint sheets 12, wherein disposes a plurality of scolders 24 on these joint sheets 12.Then; apply heat and pressure on the back side of semiconductor packages 400; because protective layer 230 temporarily is converted to the A stage after being heated; protective layer 230 has good plasticity; under the effect of pressure; it can fluidly redistribute and the outer pin 113b of portion can be squeezed easily open the protective layer 230 that is the A stage and be contacted with these scolders 24 then; continue heating so that these scolders 24 reflux and coat flare inclined-plane 113e and the joint sheet 12 of second coat of metal 119b, the outer pin 113b of portion, and protective layer 230 can complete slaking to the C stage.So far finish engaging of semiconductor packages 400 and circuit board 10.
Please refer to the generalized section of Figure 10 for a kind of semiconductor packages of another embodiment of the present invention.Semiconductor packages 500 encapsulates 100 different its chip carriers 115 that are with aforesaid semiconductor and also comprises depression (cavity) 115 ', and depression 115 ' bottom has smooth central part 115 " and around central part 115 " depressed part (recess) 115 ' ".Chip 114 is disposed at the central part 115 of depression 115 ' by colloid 117 ".So structural arrangements can reduce the integral thickness of semiconductor packages 500.Protective layer 130 covers the lower surface 118a, fan-out formula pin 113 of packing colloids 118 ' " lower surface 113h of extension 113 ' and to the surface of small part soldered ball 120; so can improve the adhesion between packing colloid 118 and the carrier 112 and avoid the oxidation of lower surface 113h, can effectively improve the reliability of semiconductor packages 500.
Please refer to the generalized section of Figure 11 for a kind of semiconductor packages of another embodiment of the present invention.Semiconductor packages 600 encapsulates 300 different its chip carriers 115 that are with aforesaid semiconductor and also comprises depression (cavity) 115 ', and depression 115 ' bottom has smooth central part 115 " and around central part 115 " depressed part (recess) 115 ".Chip 114 is disposed at the central part 115 of depression 115 ' by colloid 117 ".So structural arrangements can reduce the integral thickness of semiconductor packages 600.Protective layer 230 covers second coat of metal 119b, these outer pin 113b of portion and flare inclined-plane 113e thereof, fan-out formula pin 113 ' " the lower surface 113h of extension 113f and lower surface 118a of packing colloid 118; so can improve the adhesion between packing colloid 118 and the carrier 112 and avoid the oxidation of lower surface 113h, can effectively improve the reliability of semiconductor packages 600.
Please refer to the generalized section of Figure 12 for a kind of semiconductor packages of another embodiment of the present invention.Semiconductor packages 700 encapsulates 200 different its chip carriers 115 that are with aforesaid semiconductor and also comprises depression (cavity) 115 ', and depression 115 ' bottom has smooth central part 115 " and around central part 115 " depressed part (recess) 115 ' ".Chip 114 is disposed at the central part 115 of depression 115 ' by colloid 117 ".So structural arrangements can reduce the integral thickness of semiconductor packages 700.Protective layer 130 covers the lower surface 118a, fan-out formula pin 113 of packing colloids 118 ' " part flare inclined-plane 113e of the lower surface 113h of extension 113f and outer engagement face 113d; so can improve the adhesion between packing colloid 118 and the carrier 112 and avoid the oxidation of lower surface 113h, can effectively improve the reliability of semiconductor packages 700.
In sum because the semiconductor packages of present embodiment has protective layer, wherein protective layer cover the lower surface of packing colloid and these soldered balls to small part, therefore can improve adhesion between packing colloid and the carrier by this protective layer.Moreover, because also can covering these, protective layer is exposed to outer pin portion surface outside these soldered balls and the packing colloid to avoid oxidation, therefore can effectively improve the structural reliability of semiconductor packages.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, those of ordinary skill in any affiliated technical field, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (20)
1. semiconductor packages comprises:
Carrier has a plurality of first pins and at least one second pin, and wherein each first pin has in first the pin portion and the first outer pin portion, and this second pin has the second interior pin portion, second outer pin portion and the extension;
Chip is disposed on this carrier;
Many bonding wires are disposed between this chip, this a plurality of first interior pin portion and this extension;
Packing colloid, coat this chip, these a plurality of bonding wires, this a plurality of first interior pin portion, this second interior pin portion and this extension, and expose the lower surface of this extension, the wherein lower surface of outstanding this packing colloid of this a plurality of first outer pin portion and the second outer pin portion; And
Protective layer covers this lower surface of this packing colloid and this lower surface of this extension.
2. semiconductor packages as claimed in claim 1 also comprises a plurality of soldered balls, is disposed at respectively in this a plurality of first outer pin portion and the second outer pin portion, wherein these a plurality of soldered balls of this protective layer cover part.
3. semiconductor packages as claimed in claim 1, wherein the lower surface of this protective layer presents curved surface or concave shape between the pin portion at this outside a plurality of first.
4. semiconductor packages as claimed in claim 1, wherein the material of this protective layer comprises abietic resin or scaling powder.
5. semiconductor packages as claimed in claim 1, wherein this protective layer covers the first outer pin portion and the second outer pin portion.
6. semiconductor packages as claimed in claim 5, wherein the material of this protective layer comprises B stage thermosetting resin.
7. semiconductor packages as claimed in claim 1, wherein this encapsulation unit also comprises:
First coat of metal is disposed in these a plurality of first and second interior pin portions; And
Second coat of metal is disposed in these a plurality of first and second outer pin portions, and wherein this protective layer exposes this second coat of metal fully.
8. semiconductor packages as claimed in claim 1, wherein this chip is positioned in the second pin portion.
9. semiconductor packages as claimed in claim 1, wherein this carrier also comprises chip carrier, wherein this chip is connected with this chip carrier through colloid.
10. semiconductor packages as claimed in claim 9, wherein this chip carrier also comprises depression, wherein this chip is arranged on this depression central authorities.
11. semiconductor packages as claimed in claim 10, wherein this depression also comprises depressed part, and wherein depressed part is around this chip.
12. semiconductor packages as claimed in claim 1, wherein the thickness of this pin portion in first is greater than the thickness of this first outer pin portion.
13. the manufacture method of a semiconductor packages comprises:
Encapsulation unit is provided, this encapsulation unit comprises carrier, chip, many bonding wires and packing colloid, wherein this carrier has a plurality of first pins and at least one second pin, wherein each first pin has in first the pin portion and the first outer pin portion, this second pin has pin portion in second, second outer pin portion and the extension, this chip configuration is on this carrier, these a plurality of bonding wires are disposed at this chip, between this a plurality of first interior pin portion and this extension, this packing colloid coats this chip, these a plurality of bonding wires, this a plurality of first interior pin portion, this is pin portion and this extension in second, and exposes the lower surface of this extension; And
Form protective layer on the lower surface of this packing colloid, wherein this protective layer covers this lower surface of this packing colloid and this lower surface of this extension.
14. the manufacture method of semiconductor packages as claimed in claim 13 also comprises:
Forming before this protective layer, forming a plurality of soldered balls in this outside a plurality of first in the pin portion.
15. the manufacture method of semiconductor packages as claimed in claim 14 wherein forms the step of this protective layer, comprising:
After forming these a plurality of soldered balls, the coating protective material is to cover this lower surface of these a plurality of soldered balls and this packing colloid; And
Heat this protective material, exposing the part of each soldered ball, and form this protective layer.
16. the manufacture method of semiconductor packages as claimed in claim 13 also comprises:
The coating protective material is to cover this a plurality of first outer pin portion, this lower surface of this packing colloid and this lower surface of this extension;
A plurality of soldered balls are set on this protective material, wherein these a plurality of soldered balls are to should a plurality of first outer pin portion; And
Heat this protective material and this a plurality of soldered balls,, and form the part that this protective layer centers on these a plurality of soldered balls and exposes each soldered ball so that these a plurality of soldered balls directly contact this a plurality of first outer pin portion.
17. a semiconductor packages comprises:
Chip carrier;
At least one pin, contiguous this chip carrier, wherein this pin has interior pin portion, outer pin portion and extension;
Chip is disposed on this chip carrier;
Bonding wire is disposed between this chip and this extension;
Packing colloid coats this chip, this chip carrier, this bonding wire, this interior pin portion and this extension, and exposes the lower surface of this extension, wherein is somebody's turn to do the lower surface of outstanding this packing colloid of outer pin portion; And
Protective layer covers this lower surface of this extension.
18. semiconductor packages as claimed in claim 17 wherein should interior pin portion be configured in this chip below.
19. semiconductor packages as claimed in claim 18 also comprises:
At least one second pin, contiguous this chip carrier, wherein this second pin has pin portion, the second outer pin portion and second extension in second, and wherein this second interior pin portion is configured in this chip side, and this second extension extends towards chip; And
At least one second bonding wire is disposed between this chip and this second extension;
Wherein, this packing colloid coats this second interior pin portion and exposes the lower surface of this second extension, this lower surface of this outstanding this packing colloid of second outer pin portion, and this protective layer covers this lower surface of this second extension.
20. semiconductor packages as claimed in claim 17 also comprises:
Soldered ball is disposed at the lower surface of chip carrier, and part coats this lower surface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610033643.5A CN105448877B (en) | 2011-08-01 | 2011-08-01 | Semiconductor packages |
| CN201110217298.8A CN102280431B (en) | 2011-08-01 | 2011-08-01 | Semiconductor packages with protective layer and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110217298.8A CN102280431B (en) | 2011-08-01 | 2011-08-01 | Semiconductor packages with protective layer and preparation method thereof |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610033643.5A Division CN105448877B (en) | 2011-08-01 | 2011-08-01 | Semiconductor packages |
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| CN102280431A true CN102280431A (en) | 2011-12-14 |
| CN102280431B CN102280431B (en) | 2016-02-17 |
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| CN201110217298.8A Active CN102280431B (en) | 2011-08-01 | 2011-08-01 | Semiconductor packages with protective layer and preparation method thereof |
| CN201610033643.5A Active CN105448877B (en) | 2011-08-01 | 2011-08-01 | Semiconductor packages |
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| CN103094235A (en) * | 2012-12-14 | 2013-05-08 | 华天科技（西安）有限公司 | AAQFN package part using electroplating process and manufacture process thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN102280431B (en) | 2016-02-17 |
| CN105448877B (en) | 2019-08-23 |
| CN105448877A (en) | 2016-03-30 |
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