CN102270979B - Power-on resetting circuit - Google Patents
Power-on resetting circuit Download PDFInfo
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- CN102270979B CN102270979B CN 201110090370 CN201110090370A CN102270979B CN 102270979 B CN102270979 B CN 102270979B CN 201110090370 CN201110090370 CN 201110090370 CN 201110090370 A CN201110090370 A CN 201110090370A CN 102270979 B CN102270979 B CN 102270979B
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Abstract
The invention discloses a power-on resetting circuit, which provides a power-on resetting function for a multi-voltage source integrated circuit. The power-on resetting circuit comprises a voltage division circuit and a monitoring circuit. The voltage division circuit comprises a first N-channel metal oxide semiconductor (NMOS) transistor, a resistor and one or more series-wound diodes, wherein the gate voltage of the first NMOS transistor is controlled by a low voltage source VDD_L; the resistor is connected with the source of the first NMOS transistor and a power supply VS; and the one or more series-wound diodes are connected with a high voltage source VDD_H and the drain of the first NMOS transistor. The monitoring circuit comprises a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a second NMOS transistor and an inverter, wherein the source of the first PMOS transistor is connected to the low voltage source VDD_L; the source of the second PMOS transistor is connected to the drain of the first PMOS transistor; the second NMOS transistor is connected with the drain of the second PMOS transistor and the power supply VSS; the gates of the second NMOS transistor, the first PMOS transistor and the second PMOS transistor are commonly connected to the source of the first NMOS transistor; and the input end of the inverter is connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor.
Description
Technical field
The present invention relates to a kind of integrated circuit to a plurality of voltage sources provides the circuit of electrification reset function.
Background technology
Now, for the electronic device integrated circuit, generally all comprise an electrification circuit system.The electronic device power up provides a vdd voltage, and device voltage is raised to threshold voltage (3.3V) from 0V, and during this, because electronic device may continue before logic state, so its current logic state is uncertain.Uncertain internal logic state may cause the unpredictable behavior of integrated circuit, affects the normal function of device.Internal lock or upset that an electrify restoration circuit (POR) can provide reset signal to come reset device in order to better define logic state during powering on, thereby have guaranteed the device normal operation.
A traditional por circuit (such as Fig. 1) comprises a Schmidt trigger circuit 110, this por circuit is by P12, P13, four transistors of N12, N13, a stable capacitor C O, a PMOS transistor current source P11, a divider resistance that is formed by R1 and R2, form with nmos pass transistor N1, at signal of PORB node output be used for resetting internal logic of an electronic device.Transistor P11 can provide the electric current of the source from VDD to the divider resistance, transistor N1 can produce a triggering signal to Schmidt circuit 110 at the S2 node, this Schmidt circuit 110 can fluctuate by filtered voltage, vise simultaneously the output voltage values of PORB node when powering on, the initial value of PORB node is low level.
In power up, VDD rises to predeterminated voltage 3.3V from low level, it all is 0V that the grid of transistor P11 and P12 begins, therefore P11 and P12 conducting, electric current flows through P11 and produces a voltage at the S1 node, this point voltage value calculates by formula VIN * R2/ (R1+R2), and wherein VIN is the drain voltage of P11.Electric current produces a voltage by P12 at the S2 node, and this point voltage is followed the rising of VDD.When S1 was the electric resistance partial pressure value of VDD, the S2 node voltage was higher than the S1 node voltage.When the S2 node voltage reaches the threshold voltage of transistor N13, the N13 conducting.This moment, PORB node voltage clamper was at 0V.Rise when the VDD continuation, transistor N1 grid voltage reaches its threshold voltage, and the N1 conducting drags down the S2 node voltage simultaneously.At this moment, the P12 conducting, P12 and N1 form an impedance dividing potential drop at the S2 Nodes.If must be more much larger than P12 the N1 size design, can easily the S2 node be pulled down to 0V.This moment, N13 turn-offed, and the P13 conducting causes the PORB node to change to the logic height from logic low.PORB is logic when high, and then P12 turn-offs, the N12 conducting, and P11 turn-offs.Therefore stoped direct current to flow through the impedance dividing potential drop, made simultaneously power consumption minimum.
In recent years, increasing integrated circuit is by a plurality of voltage feds, and these voltage sources provide and equate or unequal magnitude of voltage that the logical gate of integrated circuit may be to need 1.8V voltage, and the IO part may need 3.3V voltage, and analog module may need the voltage of 3.3V or other values.For the integrated circuit of this a plurality of voltage sources, traditional por circuit can't be realized its electrification reset function.In addition, when these voltage sources are opened one by one with different order, its electrification reset function of the realization that traditional por circuit can not be suitable.Therefore, need an integrated circuit to the multivoltage source that the circuit of electrification reset function is provided.
Summary of the invention
Technical problem to be solved by this invention is to overcome the deficiencies in the prior art, provides a kind of integrated circuit to the multivoltage source that the electrify restoration circuit of electrification reset function is provided.
First technical scheme of the present invention is: a kind of electrify restoration circuit comprises two parts circuit:
First's circuit comprises:
The first nmos pass transistor, its grid voltage is controlled by low-voltage source VDD_L;
Resistance connects source electrode and power supply VSS, the wherein VDD_L 〉=VSS of the first nmos pass transistor;
One or more series diodes connect the drain electrode of high voltage source VDD_H and the first nmos pass transistor, wherein VDD_H 〉=VDD_L;
The second portion circuit comprises:
The one PMOS transistor, its source electrode are connected on the low-voltage source VDD_L;
The 2nd PMOS transistor, its source electrode are connected to the transistorized drain electrode of a PMOS;
The second nmos pass transistor, it connects the transistorized drain electrode of the 2nd PMOS and power supply VSS, and the grid of the second nmos pass transistor, the transistorized grid of a PMOS and the transistorized grid of the 2nd PMOS are connected to the source electrode of the first nmos pass transistor jointly;
Inverter, its input are connected to the drain electrode of the transistorized drain electrode of the 2nd PMOS and the second nmos pass transistor, and inverter forms an output signal RSTB simultaneously, is used for responding the opening and closing of high voltage source VDD_H and low-voltage source VDD_L.
In first's circuit, need one or more be in series be connected in diode between high voltage source VDD_H and the first nmos transistor drain, one or more diodes here also can replace in order to the PMOS transistor that the diode form connects.
In the second portion circuit, can further comprise the 3rd PMOS transistor, its grid is connected to the input of inverter, and source electrode is connected to the transistorized drain electrode of a PMOS, and drain electrode is connected to power supply VSS.
Inverter needs by low-voltage source VDD_L and power supply VSS power supply, and inverter can be exported the variation that a RSTB signal responds high voltage source VDD_H and low-voltage source VDD_L.When powering on, when low-voltage source VDD_L and high voltage source VDD_H are in or are higher than them separately during predeterminated voltage, inverter can be exported a magnitude of voltage that equates with VDD_L.VDD_H approximates greatly 3.3V.VDD_L approximates greatly 1.8V.
Second technical scheme of the present invention is: a kind of electrify restoration circuit comprises two parts circuit:
First's circuit comprises:
One or more nmos pass transistors that are connected in series, wherein the grid voltage of the first nmos pass transistor is controlled by low-voltage source VDD_L;
Resistance connects source electrode and power supply VSS, the wherein VDD_L 〉=VSS of the first nmos pass transistor;
One or more series diodes are connected to the drain electrode of high voltage source VDD_H and the first nmos pass transistor, wherein VDD_H 〉=VDD_L;
The second portion circuit comprises:
The one PMOS transistor, its source electrode is connected to low-voltage source VDD_L;
The 2nd PMOS transistor, its source electrode are connected to the transistorized drain electrode of a PMOS;
The second nmos pass transistor, it connects the transistorized drain electrode of the 2nd PMOS and power supply VSS, and the grid of the second nmos pass transistor, the transistorized grid of a PMOS and the transistorized grid of the 2nd PMOS are connected to the source electrode of the first nmos pass transistor jointly;
Inverter, its input are connected to the drain electrode of the transistorized drain electrode of the 2nd PMOS and second nmos pass transistor.
In first's circuit, need one or more diodes that are connected in high voltage source VDD_H and the first nmos transistor drain that are in series, one or more diodes here can replace in order to the PMOS transistor that the diode form connects.Between one or more diodes and the first nmos pass transistor, can further comprise the 3rd nmos pass transistor, its grid voltage is by median voltage source V DD_M control, wherein VDD_H 〉=VDD_M 〉=VDD_L.
In the second portion circuit, can further comprise the 3rd PMOS transistor, its grid is connected to the input of inverter, and source electrode is connected to the transistorized drain electrode of a PMOS, and drain electrode is connected to power supply VSS.Same inverter needs by low-voltage source VDD_L and VSS power supply.Inverter can be exported a RSTB signal and respond high voltage source VDD_H, the variation of intermediate value voltage source V DD_M and low-voltage source VDD_L at this moment.If the voltage of high voltage source VDD_H, median voltage source V DD_M and low-voltage source VDD_L is equal to or higher than self predeterminated voltage value, then the output voltage of inverter is fixing equates with VDD_L.
The invention has the beneficial effects as follows: the electrify restoration circuit that the present invention relates to provides a simple circuit structure to monitor and has powered on and power down (being the observation circuit of second portion), when integrated circuit has a plurality of power supply, this electrify restoration circuit that does not turn-off can provide a reliable reset signal, guarantees the normal operation of device; This electrify restoration circuit is not subjected to the constraint of the order that powers on of a plurality of power supplies in addition, can reduce the electric leakage of power supply yet.
Description of drawings
Fig. 1 is traditional electrify restoration circuit schematic diagram in the prior art;
Fig. 2 is the schematic diagram of the electrify restoration circuit that two voltage sources are powered simultaneously among the present invention;
Fig. 3 and Fig. 4 are illustrating the electrify restoration circuit wave form varies of two voltage feds;
Fig. 5 is the schematic diagram of a plurality of voltage sources electrify restoration circuit of powering simultaneously.
Embodiment
As shown in Figure 2, electrify restoration circuit:
The electric voltage observation circuit 220 that comprises a bleeder circuit 210 and the high voltage source VDD_H that provides and low-voltage source VDD_L are monitored.
The voltage of electric voltage observation circuit 220 monitoring node A is correspondingly exported a reset signal RSTB simultaneously.This electric voltage observation circuit 220 comprises PMOS transistor P3 and P4(the one PMOS transistor, the 2nd PMOS transistor), nmos pass transistor N2(second nmos pass transistor), their cascades are connected between low-voltage source VDD_L and the power supply VSS, wherein the source electrode of P3 is connected with low-voltage source VDD_L, and the source electrode of P4 is connected with the drain electrode of P3.The source electrode of resistance R and nmos pass transistor N1 is connected in node A, and the grid of P3, P4 and N2 links to each other with node A.This electric voltage observation circuit 220 also comprises an inverter INV, and the input of INV is connected to the drain electrode of P4 and N2.INV is by low-voltage source VDD_L and power supply VSS power supply, and INV exports a RSTB signal, the IC interior logic in the electronic device that is used for resetting.Extra PMOS transistor P5(the 3rd a PMOS transistor), its grid is connected to the input of INV, and drain electrode is connected to power supply VSS, and source electrode is connected to the drain electrode of P3 or the source class of P4.N2, P3, P4 and P5 form a Schmidt trigger circuit, and P5 can provide Schmidt trigger circuit sluggish, and the trigger voltage of electrification reset can also be set.
In current narration, VDD_H, VDD_M and VDD_L represent respectively high level, middle level and low level positive voltage: VDD_H 〉=VDD_M 〉=VDD_L.VDD_H, VDD_M are different voltage sources with VDD_L, and different voltage can be provided, and for example, VDD_H, VDD_M and VDD_L can provide respectively 3 independently voltage: 3.3V, 3.3V and 1.8V.Power supply VSS can be connected to ground." powering on " refers to that power supply opens from power terminal, and level rises to predeterminated voltage during this period of time from 0." power down " refers to that power supply closes from power terminal, and level drops to 0 during this period of time from current level.
The operating principle of electrify restoration circuit 200 can be described with the voltage oscillogram under two kinds of different situations of Fig. 3 and Fig. 4.
According to Fig. 2 and Fig. 3, power on and power down between, voltage waveform is divided into the characteristic time point of T1-T8.At the T1 point, beginning " powering on ", high voltage source VDD_H and low-voltage source VDD_L(are hereinafter to be referred as VDD_H, VDD_L) begin to raise, in this example, the VDD_H rate of climb is faster than VDD_L.When VDD_L was increased to above the N1 threshold voltage, N1 was from the off state to the opening.The voltage of node A is determined by VDD_L.At the T2 point, VDD_H at first reaches default magnitude of voltage.But between T2 and T3 point, before the voltage of node A reached its operating voltage that powers on, RSTB continued to be output as low level.At the T3 point, when VDD_L further raises, RSTB follows VDD_L voltage and rises.At the T4 time point, when VDD_L reached its predeterminated voltage, RSTB also reached its predeterminated voltage, and its value equates with VDD_L.Namely from the T3 time point, supply voltage has reached their circuit operation voltage separately.Signal of RSTB output informs that integrated circuit can carry out work.
At the T5 time point, beginning " power down ", VDD_L voltage begins to descend.VDD_H voltage begins to descend at the T6 time point.As shown in Figure 3, the decrease speed of VDD_L magnitude of voltage is slower than VDD_H.The magnitude of voltage of node A is decided by VDD_L, and its value is followed VDD_L and descended together.At the T7 time point, when dropping to, the magnitude of voltage of node A powers on below the operating voltage level, and electric voltage observation circuit 220 resets, and RSTB is output as low level simultaneously.VDD_H and VDD_L arrive low level at the T8 time point.
Only just can be at power-on reset signal of RSTB end output when high voltage source voltage and low supply voltage reach preset value simultaneously by Fig. 3 and top description explanation electrify restoration circuit 200.In other words, as long as any one voltage does not reach self predeterminated voltage in the voltage source, the output of RSTB remains low level.
Another one example (such as Fig. 2 and 4), the voltage VDD_H that power supply provides and VDD_L begin to rise from T1 constantly, and in this example, the speed that VDD_L rises is faster than the rate of climb of VDD_H.At the T2 point, VDD_L can at first reach its predeterminated voltage value., T2 constantly the VDD_H magnitude of voltage still be lower than its predeterminated voltage value, mean that the magnitude of voltage of node A still is lower than its predeterminated voltage value, this moment, the magnitude of voltage of node A was determined by VDD_H fully.When VDD_H when T3 arrives its predeterminated voltage value constantly the time, RSTB also rises to its predeterminated voltage value (equating with the VDD_L magnitude of voltage).From T3 constantly, VDD_H and VDD_L have reached respectively the power on magnitude of voltage of action need of integrated circuit.The RSTB signal can notify device to start working.
During power-off, such as T5 among the figure constantly, VDD_H voltage begins to descend, and VDD_L still keeps its predeterminated voltage.This moment, the voltage of node A was decided by VDD_L voltage, therefore also remained unchanged.At T6 constantly, the voltage drop of node A is under its predeterminated voltage, and electric voltage observation circuit (220) resets, and RSTB voltage is reduced to low level simultaneously.At T7 constantly, VDD_L voltage begins to descend, and decrease speed is faster than VDD_H, and at T8 constantly, VDD_H and VDD_L magnitude of voltage reach low level.
This example (such as Fig. 4) shows electrify restoration circuit 200(such as Fig. 2 again) only when high voltage and low-voltage arrive separately predeterminated voltage simultaneously, just can be at power-on reset signal of RSTB Nodes output.If wherein any one does not reach its predeterminated voltage for high voltage and low-voltage, the RSTB Nodes remains low level.
Electrify restoration circuit of the present invention can satisfy the integrated circuit of a plurality of voltage feds equally.Such as Fig. 5, an electrify restoration circuit 300 is comprised of a bleeder circuit 310 and an electric voltage observation circuit 320, is used for realizing having the electrification reset function of the integrated circuit of three voltage sources (VDD_H, VDD_M, VDD_L) power supply.Except two diode P1 and P2, a nmos pass transistor N1 and a resistance R, this bleeder circuit 310 comprises another one nmos pass transistor N3(the 3rd nmos pass transistor between P1 and N1), its grid voltage is controlled by VDD_M.Observation circuit 320 is identical with the domain of above-mentioned observation circuit 220.
The Push And Release of nmos pass transistor is determined by VDD_M and VDD_L.Among VDD_M and the VDD_L any one reaches the threshold voltage of N1, then N1 and N3 conducting.Therefore the magnitude of voltage of node A is determined by VDD_H, VDD_M and VDD_L.When all supply power voltages reached its predeterminated voltage, electrify restoration circuit 300 was at power-on reset signal of RSTB Nodes output.Any one supply power voltage does not wherein reach its predeterminated voltage, and the output of RSTB remains low level.
Use this circuit beneficial effect to be, when a plurality of power supply was arranged, this electrify restoration circuit that does not turn-off can provide a reliable reset signal, guaranteed the normal operation of device.This does not turn-off the constraint that electrify restoration circuit is not subjected to the order that powers on of a plurality of power supplies yet.The electric voltage observation circuit that an electric power starting is provided again simultaneously and has closed.Therefore, compare with traditional electrify restoration circuit, technical had progressive and innovation.
In the situation that does not deviate from present description, the electronic device in the circuit described herein can exchange with the electronic device of other structure.The resistance of different structure, electric capacity, transistor and amplifier can reach the function of narrating above equally.The PMOS transistor that connects with the diode form can be substituted by the diode of other structures, and electric voltage observation circuit can be substituted by other designs.Electrify restoration circuit described herein can provide reset signal to 2,3,4 or more power supply.
Claims (10)
1. an electrify restoration circuit is characterized in that, comprises two parts circuit:
First's circuit comprises:
The first nmos pass transistor, its grid voltage is controlled by low-voltage source VDD_L;
Resistance connects source electrode and power supply VSS, the wherein VDD_L 〉=VSS of the first nmos pass transistor;
One or more series diodes connect the drain electrode of high voltage source VDD_H and the first nmos pass transistor, wherein VDD_H 〉=VDD_L;
The second portion circuit comprises:
The one PMOS transistor, its source electrode are connected on the low-voltage source VDD_L;
The 2nd PMOS transistor, its source electrode are connected to the transistorized drain electrode of a PMOS;
The second nmos pass transistor, it connects the transistorized drain electrode of the 2nd PMOS and power supply VSS, and the grid of the second nmos pass transistor, the transistorized grid of a PMOS and the transistorized grid of the 2nd PMOS are connected to the source electrode of the first nmos pass transistor jointly;
Inverter, its input are connected to the drain electrode of the transistorized drain electrode of the 2nd PMOS and the second nmos pass transistor, and inverter forms an output signal RSTB simultaneously, is used for responding the opening and closing of high voltage source VDD_H and low-voltage source VDD_L.
2. a kind of electrify restoration circuit according to claim 1, it is characterized in that: wherein also include the 3rd PMOS transistor in the second portion circuit, its grid is connected to the input of inverter, and source electrode is connected to the transistorized drain electrode of a PMOS, and drain electrode is connected to power supply VSS.
3. a kind of electrify restoration circuit according to claim 1 is characterized in that: described inverter is by low-voltage source VDD_L and power supply VSS power supply.
4. a kind of electrify restoration circuit according to claim 1, it is characterized in that: if the voltage of high voltage source VDD_H and low-voltage source VDD_L is equal to or higher than self predeterminated voltage value, then the output voltage of inverter is fixing equates with the voltage of low-voltage source VDD_L.
5. a kind of electrify restoration circuit according to claim 1 is characterized in that: described one or more series diodes are the PMOS transistors that connect with the diode form.
6. an electrify restoration circuit is characterized in that, comprises two parts circuit:
First's circuit comprises:
One or more nmos pass transistors that are connected in series, wherein the grid voltage of the first nmos pass transistor is controlled by low-voltage source VDD_L;
Resistance connects source electrode and power supply VSS, the wherein VDD_L 〉=VSS of the first nmos pass transistor;
One or more series diodes are connected to the drain electrode of high voltage source VDD_H and the first nmos pass transistor, wherein VDD_H 〉=VDD_L;
The second portion circuit comprises:
The one PMOS transistor, its source electrode is connected to low-voltage source VDD_L;
The 2nd PMOS transistor, its source electrode are connected to the transistorized drain electrode of a PMOS;
The second nmos pass transistor, it connects the transistorized drain electrode of the 2nd PMOS and power supply VSS, and the grid of the second nmos pass transistor, the transistorized grid of a PMOS and the transistorized grid of the 2nd PMOS are connected to the source electrode of the first nmos pass transistor jointly;
Inverter, its input are connected to the drain electrode of the transistorized drain electrode of the 2nd PMOS or second nmos pass transistor.
7. a kind of electrify restoration circuit according to claim 6, it is characterized in that: between one or more series diodes and the first nmos pass transistor, also comprise the 3rd nmos pass transistor, its grid is by median voltage source V DD_M control, wherein VDD_H 〉=VDD_M 〉=VDD_L.
8. a kind of electrify restoration circuit according to claim 6, it is characterized in that: if the voltage of high voltage source VDD_H, median voltage source V DD_M and low-voltage source VDD_L is equal to or higher than self predeterminated voltage value, then the output voltage of inverter is fixing equates with VDD_L.
9. a kind of electrify restoration circuit according to claim 6, it is characterized in that: also comprise the 3rd PMOS transistor in the second portion circuit, its grid is connected to the input of inverter, and source electrode is connected to the transistorized drain electrode of a PMOS, and drain electrode is connected to power supply VSS.
10. a kind of electrify restoration circuit according to claim 6 is characterized in that: described one or more series diodes are the PMOS transistors that connect with the diode form.
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| CN 201110090370 CN102270979B (en) | 2011-04-12 | 2011-04-12 | Power-on resetting circuit |
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| CN 201110090370 CN102270979B (en) | 2011-04-12 | 2011-04-12 | Power-on resetting circuit |
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| CN102270979B true CN102270979B (en) | 2013-03-20 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130169255A1 (en) * | 2011-12-30 | 2013-07-04 | Tyler Daigle | Regulator power-on-reset with latch |
| CN102571069B (en) * | 2012-03-19 | 2015-03-04 | 中科芯集成电路股份有限公司 | Single-power-supply positive and negative logic conversion circuit |
| CN103427812B (en) * | 2012-05-25 | 2015-04-01 | 国家电网公司 | Power-on reset circuit and method thereof |
| US9960760B2 (en) * | 2013-07-25 | 2018-05-01 | Analog Devices Global | Multi-level output cascode power stage |
| CN103997323B (en) * | 2014-06-09 | 2017-01-25 | 上海华力微电子有限公司 | Reset circuit low in power consumption and high in stability |
| CN105634453A (en) * | 2014-11-03 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | Power-on reset circuit |
| EP3136437A1 (en) * | 2015-08-27 | 2017-03-01 | Nexperia B.V. | Semiconductor device and associated methods |
| CN106059550A (en) * | 2016-06-03 | 2016-10-26 | 乐视控股（北京）有限公司 | System reset circuit and electronic device |
| CN106357249B (en) * | 2016-11-04 | 2020-04-07 | 上海晟矽微电子股份有限公司 | Power-on reset circuit and integrated circuit |
| US10193545B1 (en) * | 2017-08-28 | 2019-01-29 | Silicon Laboratories Inc. | Power-on reset system for secondary supply domain |
| CN108418573B (en) * | 2018-02-07 | 2024-02-06 | 中国科学院半导体研究所 | Power supply sampling circuit and zero-power-consumption power-on reset circuit comprising same |
| CN112865772B (en) * | 2021-02-08 | 2022-03-08 | 苏州领慧立芯科技有限公司 | Power-on reset circuit |
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| US5930129A (en) * | 1997-08-08 | 1999-07-27 | Oki Electric Industry Co., Ltd. | Power on reset circuit |
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| US7417476B1 (en) * | 2007-04-24 | 2008-08-26 | Smartech Worldwide Limited | Power-on-reset circuit with output reset to ground voltage during power off |
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| US5930129A (en) * | 1997-08-08 | 1999-07-27 | Oki Electric Industry Co., Ltd. | Power on reset circuit |
| CN1637945A (en) * | 2003-12-30 | 2005-07-13 | 海力士半导体有限公司 | Power-up circuit semiconductor memory device |
| US7417476B1 (en) * | 2007-04-24 | 2008-08-26 | Smartech Worldwide Limited | Power-on-reset circuit with output reset to ground voltage during power off |
| CN101873125A (en) * | 2009-04-22 | 2010-10-27 | 北京芯技佳易微电子科技有限公司 | Reset circuit |
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Correction item: Patentee|Address Correct: Jianrong integrated circuit technology (Zhuhai) Co., Ltd.|519015 Guangdong city of Zhuhai province Jida Bailian Road No. 184 building 4 floor three-dimensional technology False: Zhuorong integrated circuit technology Co., Ltd.|Rooms 1306-1309, 13\F, 19 science Avenue West, Hong Kong Science Park, Shatin, New Territories, China Number: 02-02 Volume: 38 |
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