CN102262606A - System and method for allocating inter-integrated circuit (I2C) communication address - Google Patents
System and method for allocating inter-integrated circuit (I2C) communication address Download PDFInfo
- Publication number
- CN102262606A CN102262606A CN2010101860933A CN201010186093A CN102262606A CN 102262606 A CN102262606 A CN 102262606A CN 2010101860933 A CN2010101860933 A CN 2010101860933A CN 201010186093 A CN201010186093 A CN 201010186093A CN 102262606 A CN102262606 A CN 102262606A
- Authority
- CN
- China
- Prior art keywords
- eeprom
- slot
- cpu
- mailing address
- electronic installation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a system and a method for allocating an inter-integrated circuit (I2C) communication address. The method and the system are used for automatically allocating different I2C communication addresses to a plurality of electronic devices connected with a main board. Each electronic device comprises a central processing unit (CPU) and an electrically erasable programmable read-only memory (EEPROM). The method comprises the following steps of: respectively inserting the plurality of electronic devices into slots of the main board through a connector card; connecting the A0 pin of the EEPROM and the general purpose input/output (GPIO-2) port of the CPU, and connecting the A1 pin of the EEPROM and the GPIO-1 port of the CPU; defining a slot number for each slot by adjusting the potential of a resistance connected with the slot; distinguishing the slot number of each electronic device through the GPIO-1 port and GPIO-2 port of each CPU respectively; and allocating an I2C communication address to the EEPROM of the electronic device in the corresponding slot according to each slot number.
Description
Technical field
The present invention relates to a kind of I2C mailing address distribution method of electronic installation, particularly share the I2C mailing address distribution system and the method for same I2C bus about a kind of a plurality of electronic installations.
Background technology
At present, a lot of computing machines (for example server) adopt a kind of blade point type system (Blade typesystem), and with in the mainboard of blade point type system combination in casing.As shown in Figure 1, be the synoptic diagram of a kind of blade point type system.This blade point type system includes CPU (Central Processing Unit, central processing unit) and EEPROM (Electrically Erasable Programmable Read-OnlyMemory, electric erasable read-only memory).Required parameter value when depositing the blade point type system boot in this EEPROM, between CPU and the EEPROM by I2C bus (I2C Bus) as both control of communication interfaces.When the blade point type system boot, CPU reads default parameter value running by the I2C bus from EEPROM, and detects the slot numbering that is inserted in the integration mainboard by GPIO-1 port, GPIO-2 port.Wherein, when CPU read preset parameter value by I2C bus and EEPROM communication, the I2C address of its EEPROM can define a mailing address by the pin (for example A1 among Fig. 1 and A0 pin) of EEPROM usually, is commonly defined as " 0x50 ".At this moment, CPU can communicate by I2C bus reading of data from EEPROM according to this mailing address.
Yet, when using a plurality of blade point type system combinations on a mainboard, have a plurality of IC chips to communicate by the I2C bus with the CPU of each blade point type system and integrate on the mainboard.Because the I2C bus of all blade point type systems all links together via integrating mainboard, " 0x50 " mailing address that EEPROM on the I2C bus will take place thus repeats, cause the CPU of each blade point type system can't correctly from EEPROM, read preset parameter value, thereby cause the traffic operation mistake and normal operational system.Be head it off, the mailing address of EEPROM in each blade point type system need be set different I2C addresses respectively, for example be set to " 0x50 ", " 0x51 ", " 0x52 ", " 0x53 " respectively.Yet the mode of this setting I2C address is exactly A0 and the external resistance of A1 pin by adjusting each EEPROM, and it is connected to electronegative potential or noble potential respectively.
Though can solve the problem of mailing address conflict thus, hardware is the A1 that sets EEPROM, the outer meeting resistance of A0 address when manufacturing the blade point type system in a large number, just has the blade point type system hardware of multiple setting different communication address.The hardware of these different set if manufacturing personnel do not offer a clear explanation is easy to obscure and mixes up, and in addition, if be inserted into when integrating the mainboard use, the problem of mailing address repeated collisions can take place still.
Invention information
In view of above content, be necessary to provide a kind of I2C mailing address distribution system and method, can go out a plurality of electronic installations (for example blade point type system) mailing address that interior EEPROM is different by automatic setting, when manufacturing the hardware of blade point type system, need not at each hardware definition mailing address.
Described I2C mailing address distribution system is used to a plurality of electronic installations that patch on mainboard to distribute different I2C mailing addresses automatically.Each electronic installation comprises CPU and EEPROM.Described I2C mailing address distribution system comprises: link block, be used for being connected with the GPIO-2 port of CPU and the A1 pin of EEPROM when being connected, CPU in the electronic installation and EEPROM are established a communications link with the GPIO-1 port of CPU when the A0 of EEPROM pin; Identification module, be used for when a plurality of electronic installations insert each slot of mainboard by patching card, be slot numbering of each slot definition by regulating the resistance current potential that each slot connects, and by the GPIO-1 port of each CPU, the slot numbering that the GPIO-2 port identifies each electronic installation place respectively; Address assignment module, being used for according to each slot numbering is that EEPROM distributes an I2C mailing address in the electronic installation on the associated socket.
Described I2C mailing address distribution method is used to a plurality of electronic installations that patch on mainboard to distribute different I2C mailing addresses automatically.Each electronic installation comprises CPU and EEPROM.The method comprising the steps of: a plurality of electronic installations are inserted respectively in the slot of mainboard by patching card; The A0 pin of EEPROM in each electronic installation is connected with the GPIO-2 port of CPU, and the A1 pin of EEPROM is connected with the GPIO-1 port of CPU; Be slot numbering of each slot definition by regulating the resistance current potential that each slot connects; By the GPIO-1 port of each CPU, the slot numbering that the GPIO-2 port identifies each electronic installation place respectively; According to each slot numbering is that EEPROM distributes an I2C mailing address in the electronic installation on the associated socket.
Compared to prior art, I2C mailing address distribution system of the present invention and method, when a plurality of blade point type system patches in the slot of a mainboard by its slot card, can distribute different I2C mailing addresses for EEPROM in each blade point type system is automatic, thereby solve a plurality of shared same I2C buses of blade point type system and mailing address repeated collisions problem takes place.
Description of drawings
Fig. 1 is the synoptic diagram of a kind of blade point type system.
Fig. 2 is the enforcement Organization Chart of I2C mailing address distribution system of the present invention preferred embodiment.
Fig. 3 is the functional block diagram of I2C mailing address distribution system of the present invention preferred embodiment.
Fig. 4 is the process flow diagram of I2C mailing address distribution method of the present invention preferred embodiment.
The main element symbol description
I2C mailing address distribution system 10
Starting module 104
Embodiment
As shown in Figure 2, be the enforcement Organization Chart of I2C mailing address distribution system of the present invention 10 preferred embodiments.In the present embodiment, this I2C mailing address distribution system 10 solidifies respectively and runs in each electronic installation, and this electronic installation is a kind of blade point type system (Blade type system).As Fig. 2 four blade point type systems are shown, for example blade point type system-1, blade point type system-2, blade point type system-3, blade point type system-4, each blade point type system comprises CPU (Central ProcessingUnit, central processing unit) and EEPROM (Electrically Erasable ProgrammableRead-Only Memory, electric erasable read-only memory).Required systematic parameter when storing the blade point type system boot in each EEPROM communicates by I2C bus (I2C Bus) between each CPU EEPROM corresponding with it, and this I2C bus is the control interface that communicates between CPU and the EEPROM.
Each blade point type system inserts respectively in the slot of an integration mainboard by its slot card, and this mainboard comprises a plurality of slots, for example slot-1, slot-2, slot-3, slot-4.Each slot is connected with two resistance respectively, CPU defines the numbering (ID) of each slot by the current potential of regulating each resistance, this slot numbering is with a binary numeric representation, being numbered of slot-1 " 00 " for example, being numbered of slot-2 " 01 ", being numbered of slot-3 " 10 ", being numbered of slot-4 " 11 ".Each slot links together by the I2C bus on the mainboard, is circumscribed with a plurality of IC chips on the I2C bus, for example IC-1, IC-2, IC-3, IC-4.The I2C bus on the mainboard is shared by each blade point type system, and can communicate with each IC chip.
Each CPU comprises GPIO-1 port (General-Purpose Input Output Port, universal input and output port) and GPIO-2 port, and each EEPROM comprises A0 pin and A1 pin.Wherein, the A1 pin of EEPROM is connected with the GPIO-1 of CPU, and the A0 pin is connected with GPIO-2.Described A0 pin, A1 pin are used to EEPROM and CPU to communicate I2C mailing address of definition, and for example the I2C mailing address is " 0x50 ", " 0x51 ", " 0x52 ", " 0x53 ".Each CPU is inserted in the slot numbering of integrating mainboard by GPIO-1 port, the corresponding blade point type system of GPIO-2 port detecting, be that according to slot numbering each EEPROM distributes an I2C mailing address, and control corresponding blade point type system according to the I2C mailing address by I2C bus reading system parameter from the EEPROM of correspondence and start shooting.
As shown in Figure 3, be the functional block diagram of I2C mailing address distribution system of the present invention 10 preferred embodiments.This I2C mailing address distribution system 10 comprises link block 101, identification module 102, address assignment module 103 and starting module 104.Each functional module is formed by a plurality of computationses, is used to be shared on the corresponding I2C mailing address of a plurality of blade point type system assignment on the same I2C bus, thereby makes each blade point type system finish correct start running.
When described link block 101 is used for that A0 pin as EEPROM in each blade point type system is connected with the GPIO-2 port of CPU and the A1 pin of EEPROM is connected with the GPIO-1 port of CPU, CPU in this blade point type system is set up corresponding communication with EEPROM be connected.
Described identification module 102 is used for patching card when inserting the slot of mainboard when each blade point type system by it, is slot numbering of each slot definition by regulating the resistance current potential that each slot connects.This slot numbering is with a binary number value representation, and for example slot-1 to the pairing numbering of slot-4 is respectively " 00 ", " 01 ", " 10 " reach " 11 ".Described identification module 102 also is used for the slot numbering that GPIO-1, GPIO-2 port by each CPU identifies each blade point type system place respectively.For example, blade point type system-1 patches card by it and is inserted on the slot-1 of mainboard, and the slot numbering that 102 of identification modules identify blade point type system-1 place is " 00 ".
It is I2C mailing address of EEPROM distribution of the blade point type system on the associated socket that described address assignment module 103 is used for according to each slot numbering.For example, address assignment module 103 is for the I2C mailing address that the EEPROM in blade point type system-1 to the blade point type system-4 distributes is respectively " 0x50 ", " 0x51 ", " 0x52 " reaches " 0x53 ".
Described starting module 104 is used for the I2C mailing address that distributes according to each EEPROM and controls the running of starting shooting of corresponding blade point type system by the I2C bus from this EEPROM reading system parameter, thereby avoids because generation mailing address repeated collisions problem on the same I2C bus is shared by a plurality of blade point type systems.The I2C mailing address that for example blade point type system-1 distributed is " 0x50 ", and 104 of starting modules are finished correct start according to this I2C mailing address reading system parameter from the EEPROM of correspondence and operated.
As shown in Figure 4, be the process flow diagram of I2C mailing address distribution method of the present invention preferred embodiment.In the present embodiment, when a plurality of electronic installations patch when integrating the slot of mainboard for one by its slot card, implementing the present invention can distribute different I2C mailing addresses automatically for EEPROM in the electronic installation, shares same I2C bus and mailing address repeated collisions problem takes place thereby solve a plurality of electronic installations.Present embodiment is that example is described electronic installation with four blade point type systems, and blade point type system-1 for example shown in Figure 2 is to blade point type system-4.
Step S41, the user patches card with a plurality of blade point type system by it and inserts respectively in the slot of integrating mainboard, and to slot-4, each blade point type system comprises CPU and EEPROM as slot-1.
Step S42, when the A0 pin of EEPROM in each blade point type system is connected with the GPIO-2 port of CPU and the A1 pin of EEPROM when being connected with the GPIO-1 port of CPU, link block 101 is set up corresponding communication with CPU in the cutting edge of a knife or a sword formula system with EEPROM and is connected.
Step S43, when each blade point type system patches card when inserting each slot of mainboard respectively by it, identification module 102 is slot numbering of each slot definition by the resistance current potential of regulating each slot and connecting.This slot numbering is with a binary number value representation, and for example slot-1 to the pairing slot numbering of slot-4 is respectively " 00 ", " 01 ", " 10 " reach " 11 ".
Step S44, identification module 102 identify the slot numbering at each blade point type system place respectively by GPIO-1, the GPIO-2 port of each CPU.For example, blade point type system-1 patches card by it and is inserted on the slot-1 of mainboard, and the slot numbering that 102 of identification modules identify blade point type system-1 place is " 00 ".
Step S45, address assignment module 103 is that the intrasystem EEPROM of blade point type on the associated socket distributes an I2C mailing address according to each slot numbering.For example, address assignment module 103 is for the I2C mailing address that the EEPROM in blade point type system-1 to the blade point type system-4 distributes is respectively " 0x50 ", " 0x51 ", " 0x52 " reaches " 0x53 ".
Step S46, starting module 104 is controlled the running of starting shooting of corresponding blade point type system according to I2C mailing address that each EEPROM distributed by I2C bus reading system parameter from this EEPROM, thereby avoids owing to mailing address repeated collisions problem takes place the shared same I2C bus of a plurality of blade point type systems.The I2C mailing address that for example blade point type system-1 distributed is " 0x50 ", and 104 of starting modules are finished correct start according to this I2C mailing address reading system parameter from the EEPROM of correspondence and operated.
Claims (10)
1. an I2C mailing address distribution system is used to a plurality of electronic installations that patch on mainboard to distribute different I2C mailing addresses, and each electronic installation comprises CPU and EEPROM, it is characterized in that, described I2C mailing address distribution system comprises:
Link block is used for being connected with the GPIO-2 port of CPU and the A1 pin of EEPROM when being connected with the GPIO-1 port of CPU when the A0 of EEPROM pin, and CPU and EEPROM in each electronic installation are established a communications link;
Identification module, be used for when a plurality of electronic installations insert the slot of mainboard respectively by patching card, be slot numbering of each slot definition by regulating the resistance current potential that each slot connects, and by the GPIO-1 port of each CPU, the slot numbering that the GPIO-2 port identifies each electronic installation place respectively; And
Address assignment module, being used for according to each slot numbering is that EEPROM distributes a 12C mailing address in the electronic installation on the associated socket.
2. I2C mailing address distribution system as claimed in claim 1 is characterized in that, stores electronic installation required systematic parameter of when start in each EEPROM, communicates by an I2C bus between each CPU EEPROM corresponding with it.
3. I2C mailing address distribution system as claimed in claim 2, it is characterized in that, this system also comprises starting module, be used for the I2C mailing address that distributes according to each EEPROM by the I2C bus from the running of starting shooting of the corresponding electronic installation of this EEPROM reading system parameter control.
4. I2C mailing address distribution system as claimed in claim 1 is characterized in that each slot is connected with two resistance respectively, is used to the slot numbering of a binary numeral of each slot definition.
5. I2C mailing address distribution system as claimed in claim 1 is characterized in that, described electronic installation is an a kind of blade point type system.
6. an I2C mailing address distribution method is used to a plurality of electronic installations that patch on mainboard to distribute different I2C mailing addresses, and each electronic installation comprises CPU and EEPROM, it is characterized in that, the method comprising the steps of:
A plurality of electronic installations are inserted respectively in the slot of mainboard by patching card;
The A0 pin of EEPROM in each electronic installation is connected with the GPIO-2 port of CPU, and the A1 pin of EEPROM is connected with the GPIO-1 port of CPU;
Be slot numbering of each slot definition by regulating the resistance current potential that each slot connects;
By the GPIO-1 port of each CPU, the slot numbering that the GPIO-2 port identifies each electronic installation place respectively; And
According to each slot numbering is that EEPROM distributes an I2C mailing address in the electronic installation on the associated socket.
7. I2C mailing address distribution method as claimed in claim 6 is characterized in that, stores electronic installation required systematic parameter of when start in each EEPROM, communicates by an I2C bus between each CPU EEPROM corresponding with it.
8. I2C mailing address distribution method as claimed in claim 7 is characterized in that this method also comprises step:
According to I2C mailing address that each EEPROM distributed by the running of starting shooting of I2C bus corresponding electronic installation of reading system parameter control from this EEPROM.
9. I2C mailing address distribution method as claimed in claim 6 is characterized in that each slot is connected with two resistance respectively, is used to the slot numbering of a binary numeral of each slot definition.
10. I2C mailing address distribution method as claimed in claim 6 is characterized in that, described electronic installation is an a kind of blade point type system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101860933A CN102262606A (en) | 2010-05-28 | 2010-05-28 | System and method for allocating inter-integrated circuit (I2C) communication address |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101860933A CN102262606A (en) | 2010-05-28 | 2010-05-28 | System and method for allocating inter-integrated circuit (I2C) communication address |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102262606A true CN102262606A (en) | 2011-11-30 |
Family
ID=45009240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101860933A Pending CN102262606A (en) | 2010-05-28 | 2010-05-28 | System and method for allocating inter-integrated circuit (I2C) communication address |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102262606A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105606763A (en) * | 2014-11-14 | 2016-05-25 | 日本特殊陶业株式会社 | Measurement apparatus |
| CN111651395A (en) * | 2020-03-25 | 2020-09-11 | 新华三信息技术有限公司 | Address configuration method, device, equipment and machine-readable storage medium |
| CN114328314A (en) * | 2021-12-31 | 2022-04-12 | 华勤通讯香港有限公司 | Address automatic acquisition method, device, terminal equipment and storage medium |
| CN115103111A (en) * | 2022-06-14 | 2022-09-23 | 希姆通信息技术（上海）有限公司 | Method for realizing camera compatibility |
-
2010
- 2010-05-28 CN CN2010101860933A patent/CN102262606A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105606763A (en) * | 2014-11-14 | 2016-05-25 | 日本特殊陶业株式会社 | Measurement apparatus |
| CN111651395A (en) * | 2020-03-25 | 2020-09-11 | 新华三信息技术有限公司 | Address configuration method, device, equipment and machine-readable storage medium |
| CN114328314A (en) * | 2021-12-31 | 2022-04-12 | 华勤通讯香港有限公司 | Address automatic acquisition method, device, terminal equipment and storage medium |
| CN115103111A (en) * | 2022-06-14 | 2022-09-23 | 希姆通信息技术（上海）有限公司 | Method for realizing camera compatibility |
| CN115103111B (en) * | 2022-06-14 | 2023-10-13 | 希姆通信息技术（上海）有限公司 | Method for realizing camera compatibility |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| RU2018142253A (en) | METHODS AND DEVICE FOR CONNECTING WITH THE POSSIBILITY OF TRANSMITTING DATA OF FIELD DEVICES WITH A REMOTE TERMINAL UNIT | |
| US7475806B1 (en) | Method and system of universal RFID communication | |
| CN100590648C (en) | Memory cards including a standard security function | |
| US9158723B2 (en) | Expanded protocol adapter for in-vehicle networks | |
| CN101499961B (en) | Blade server and method for managing blade address | |
| CN102262606A (en) | System and method for allocating inter-integrated circuit (I2C) communication address | |
| CN108386965B (en) | PLC networking method through equipment unique code pairing and identification card pairing | |
| CN114003538B (en) | Identification method of intelligent network card and intelligent network card | |
| EP2688258A1 (en) | Single board communication method, system and single board | |
| WO2011145829A2 (en) | Microsd device loaded with a smart card | |
| CN103853678A (en) | Board management device and board management system and control card using same | |
| CN109309737B (en) | Wireless assignment of network addresses | |
| CN106936653A (en) | A kind of recognition methods of optical mode block type and device | |
| CN111209030A (en) | Firmware configuration method and device | |
| CN105306324A (en) | Ethernet multiplexed communication system and Ethernet interface setting method applied to Ethernet multiplexed communication system | |
| CN111028719A (en) | Lamp panel connecting plate and LED display screen | |
| US20140297050A1 (en) | Control device and method for operating such a control device | |
| CN116226019A (en) | System and method for managing multiple types of IO board cards based on universal controller | |
| CN113220614A (en) | Method, system and medium for adaptively managing I2C and I3C devices | |
| CN112231251B (en) | Board card slot identification method and device, communication equipment and readable storage medium | |
| CN100535882C (en) | Method for operating expansion card | |
| CN109599172A (en) | A kind of dynamically configurable card cage and its Dynamic Configuration | |
| CN107798267B (en) | Method for configuring a communication module of at least one reader device and communication module | |
| CN106850461B (en) | Forwarding board channel multiplexing method and device | |
| CN103365377A (en) | Cabinet upright column, back board, groove bit identification system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20111130 |