CN102255614A - Clock generation circuit and clock generation method - Google Patents
Clock generation circuit and clock generation method Download PDFInfo
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- CN102255614A CN102255614A CN2010101900983A CN201010190098A CN102255614A CN 102255614 A CN102255614 A CN 102255614A CN 2010101900983 A CN2010101900983 A CN 2010101900983A CN 201010190098 A CN201010190098 A CN 201010190098A CN 102255614 A CN102255614 A CN 102255614A
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Abstract
The invention discloses a clock generation circuit and a clock generation method. The clock generation circuit comprises a phase detector, a first filter device, a charge pump, a second filter device and a controllable oscillator, wherein the phase detector is used for detecting a phase difference between a first clock and a second clock to generate a detection result; the first filter device is used for filtering the detection result; the charge pump is used for generating a control signal according to the filtered detection result; the second filter device is used for filtering the control signal; and the controllable oscillator is used for generating an output clock according to the filtered control signal, wherein the output clock is used for generating the second clock.
Description
Technical field
The invention relates to a clock generating circuit and its correlation technique, especially the finger phase-locked loop that can improve a ripple signal with its correlation technique.
Background technology
Please refer to Figure 1A and Figure 1B.Being a schematic diagram of a traditional phase-locked loop circuit (Phase-locked LoopCircuit) 10 shown in Figure 1A, is the sequential chart of each signals in the phase-locked loop circuit 10 shown in Figure 1B.Traditional phase-locked loop circuit 10 includes a phase/frequency detector (Phase/Frequency Detector) 12, one charge pump 14, one a low communication ripple device 16 and a voltage-controlled oscillator (VCO) 18, connected mode between its element please refer to Figure 1A, does not give unnecessary details in addition at this.Generally speaking, traditional phase-locked loop circuit 10 is to utilize phase/frequency detector 12 to detect one with reference to the phase difference between a clock pulse S1 ' and the feedback clock pulse S2 ', and utilize charge pump 14 to receive the first phase signal Sd1 ' and the second phase signal Sd2 ' to produce a current signal Sa ' corresponding to phase difference, wherein these phase signals Sd1 ', Sd2 ' they are that pattern with pulse wave presents.In addition, when the phase-lead of reference clock pulse S1 ' feeds back the phase place of clock pulse S2 ', the first phase signal Sd1 ' of phase/frequency detector 12 is a low voltage level for the high-voltage level second phase signal Sd2 ', otherwise, when the phase lag of reference clock pulse S1 ' is fed back clock pulse S2 ', the first phase signal Sd1 ' is a high-voltage level for the low voltage level second phase signal Sd2 ', yet, at charge pump 14 with these phase signals Sd1 ', Sd2 ' is converted in the process of current signal Sa ', because charge pump 14 can have the reaction time to a certain degree, so charge pump 14 often can't verily produce the current signal Sa ' of a pulse wave pattern.Therefore, in order to make this current signal Sa ' intactly present the pulse wave pattern the same with phase signal Sd1 ', Sd2 ', all can include a matrix current adjustment circuit in addition in traditional charge pump 14, be used for revising the current signal Sa ' that charge pump 14 is produced, so that current signal Sa ' has the pulse wave form the same haply with phase signal Sd1 ', Sd2 '.Yet, when current signal Sa ' presents the pulse wave pattern, represent that then this current signal Sa ' has the signal composition of high frequency, thus, what be coupled in charge pump 14 rears in the phase-locked loop circuit 10 must have the ability that the high-frequency signal composition with current signal Sa ' filters a low communication ripple device 16, with produce one than the control signal Scon ' of low frequency to a voltage-controlled oscillator (VCO) 18.In other words, this low pass filter 16 must be the low pass filter of a multipole point, be to account for the more circuit area of tool on it is general, and the degree of difficulty of its setting also is higher relatively.
Can learn from above-mentioned description content, the circuit area that matrix current adjustment circuit has not only increased traditional phase-locked loop 10 is set, also increase the circuit area and the design difficulty of low pass filter 16 simultaneously.Moreover, the current signal Sa ' that charge pump 14 is produced is adjusted to the unpromising traditional phase-locked loop circuit 10 of pulse wave pattern and brings significant benefit, may make the control signal Scon ' of a voltage-controlled oscillator (VCO) 18 ripple (Ripple) signal (that is the arrow indication place at time point t1, t2...t4 place) occur on the contrary.Therefore, how to improve the problem that above-mentioned traditional phase-locked loop faces and become the problem of needing solution in the mixed signal field badly.
Summary of the invention
Therefore, a purpose of the present invention be to provide the phase-locked loop that can improve a ripple signal with its correlation technique.
Provide a kind of clock generating circuit according to one aspect of the present invention.Clock generating circuit includes phase detectors, one first filter, a charge pump, one second filter and a may command oscillator.These phase detectors are used for detecting the phase difference between one first clock pulse and one second clock pulse, to produce a testing result.This first filter is used for this testing result is carried out filtering operation.This charge pump is used for producing a control signal according to filtered this testing result.This second filter is used for this control signal is carried out filtering operation.This may command oscillator is used for producing an output clock pulse according to filtered this control signal, and wherein this output clock pulse is used for producing this second clock pulse.
Provide a kind of clock generating circuit on the other hand according to the present invention.Clock generating circuit includes phase detectors, a charge pump, one second filter and a may command oscillator.These phase detectors are used for detecting the phase difference between one first clock pulse and one second clock pulse, to produce a testing result.This charge pump is used for producing a control signal according to this testing result, and wherein this charge pump includes one first filter, and it is used for this testing result to the M signal between this control signal is carried out filtering operation.This second filter is used for this control signal is carried out filtering operation.This may command oscillator is used for producing an output clock pulse according to filtered this control signal, and wherein this output clock pulse is used for producing this second clock pulse.
Provide a kind of clock pulse generation methods according to another aspect of the present invention.This clock pulse generation methods includes the following step: detect the phase difference between one first clock pulse and one second clock pulse, to produce a testing result; This testing result is carried out filtering operation; Utilize a charge pump to come to produce a control signal according to filtered this testing result; This control signal is carried out filtering operation; And according to filtered this control signal produce one output clock pulse, wherein this output clock pulse is used for producing this second clock pulse.
Provide a kind of clock pulse generation methods according to further aspect of the present invention.This clock pulse generation methods includes the following step: detect the phase difference between one first clock pulse and one second clock pulse, to produce a testing result; Utilize a charge pump to produce a control signal, and this testing result to the M signal between this control signal is carried out filtering operation according to this testing result; This control signal is carried out filtering operation; And according to filtered this control signal produce one output clock pulse, wherein this output clock pulse is used for producing this second clock pulse.
Useful technique effect of the present invention is: with respect to traditional phase-locked loop, the loop filter in the clock generating circuit of the present invention has lower cost of manufacture.Moreover, because the frequency of control signal is lower, and then make after the filtering that loop filter produced control signal will relatively level off to a straight line, and can not occur as the control signal of traditional phase-locked loop at ripple signal that each cycle produced.Like this, the staggered attached signal (spur) that mixes of the output clock pulse that produced of may command oscillator just can improve significantly.On the other hand, because present embodiment does not need to produce the control signal of a pulse wave pattern, therefore with regard to need not to design the control signal that at a high speed a charge pump produces the pulse wave pattern, further to fall the cost of clock generating circuit.
Description of drawings
Figure 1A is a schematic diagram of a traditional phase-locked loop circuit.
Figure 1B is the sequential chart of interior each signal of this phase-locked loop circuit of Figure 1A.
Fig. 2 A is an embodiment schematic diagram of a kind of clock generating circuit of the present invention.
Fig. 2 B is the sequential chart of control signal after testing result and the filtering behind one first clock pulse, one second clock pulse, one first phase signal, one first filtering of this clock generating circuit.
Fig. 3 is the one first embodiment schematic diagram of thin portion circuit of phase detectors, one first filter and a charge pump of this clock generating circuit.
Fig. 4 is the embodiment schematic diagram of another charge pump of the present invention's one clock generating circuit.
Fig. 5 is that an embodiment stream of a kind of clock pulse generation methods of the present invention is figure.
Fig. 6 is another embodiment flow chart of a kind of clock pulse generation methods of the present invention.
Embodiment
Please refer to Fig. 2 A.It shown in Fig. 2 A an embodiment schematic diagram of a kind of clock generating circuit 100 of the present invention.Clock generating circuit 100 includes phase detectors 102, one first filter 104, a charge pump 106, one second filter 108 and a may command oscillator 110.Phase detectors 102 are used for detecting a phase difference between one first clock pulse S1 and the one second clock pulse S2 to produce a testing result.First filter 104 is coupled to phase detectors 102, is used for this testing result is carried out a filtering operation.Charge pump 106 is coupled to first filter 104, is used for according to producing a control signal Sc via first filter, 104 filtered these testing results.Second filter 108 is coupled to charge pump 106, is used for control signal Sc is carried out a filtering operation to produce control signal Scf after the filtering.May command oscillator 110 is coupled to second filter 108 and phase detectors 102, is used for producing an output clock pulse Sout according to control signal Scf after the filtering, wherein exports clock pulse Sout and is used for producing the second clock pulse S2.In the present embodiment, output clock pulse Sout directly feeds back to phase detectors 102 and is used as the second clock pulse S2.In another embodiment of the present invention, output clock pulse Sout can also by one frequently frequency eliminating circuit carry out feeding back to phase detectors 102 again behind the frequency frequency elimination and be used as the second clock pulse S2, it also is category of the present invention place.On the other hand, though the clock generating circuit 100 of present embodiment is to implement according to this with a phase-locked loop circuit (Phase-locked Loop Circuit), yet it is not as restriction of the present invention place.Be familiar with this operator after reading the disclosed technical characterictic of the present invention, by suitably revising, also spirit of the present invention can be applied in the data clock pulse reflex circuit (Data Clock Recovery Circuit), and obtain similar effect, it also is category of the present invention place.
On the other hand, in order to distinguish the leading or backward relation of phase place between the first clock pulse S1 and the second clock pulse S2, the testing result that phase detectors 102 are produced can include one first phase signal Sd1 and one second phase signal Sd2, wherein the first phase signal Sd1 represents the phase place of the leading second clock pulse S2 of the first clock pulse S1, and on behalf of the first clock pulse S1, the second testing result Sd2 fall behind the phase place of the second clock pulse S2.In addition, first filter 104 includes one first filter 1042 and one second filter 1044.First filter 1042 is accepted the first phase signal Sd1, and the first phase signal Sd1 is carried out filtering operation to produce filtered first a phase signal Sdf1.Second filter 1044 is accepted the second phase signal Sd2, and the second phase signal Sd2 carried out filtering operation to produce filtered second a phase signal Sdf2, wherein charge pump 106 is coupled to first filter 1042 and second filter 1044, is used for producing control signal Sc according to filtered first phase signal Sdf1 and the filtered second phase signal Sdf2.In the present embodiment, control signal Sc is a current signal.
Generally speaking, when clock generating circuit 100 carries out a phase-locked operation, it only can be that the first clock pulse S1 leads over the second clock pulse S2 or the first clock pulse S1 and lags behind a kind of among the second clock pulse S2 that phase place between the first clock pulse S1 and the second clock pulse S2 is closed, and because the operation that the first clock pulse S1 leads over the second clock pulse S2 is the operation that lags behind the second clock pulse S2 similar in appearance to the first clock pulse S1, so this paper situation of only leading over the second clock pulse S2 at the first clock pulse S1 illustrates the technical characterictic of clock generating circuit 100.This field has knows that usually the knowledgeable ought to understand when the first clock pulse S1 lags behind the second clock pulse S2 reading after the disclosed method of this paper, and clock generating circuit 100 also can have similar technical characterictic.Please refer to Fig. 2 B, is the sequential chart of control signal Scf after testing result Sdf2 and the filtering after testing result Sdf1 after the first clock pulse S1, the second clock pulse S2, the first phase signal Sd1, the second phase signal Sd2, first filtering of clock generating circuit 100 of the present invention, second filtering shown in Fig. 2 B.Because the first clock pulse S1 leads over the second clock pulse S2, so phase detectors 102 produce first phase signal Sd1 to the first filter 1042 to carry out filtering.Please note, though Fig. 2 A of the present invention and Fig. 2 B all draw the first phase signal Sd1, but be the first phase signal Sd1 that not necessarily will produce the pulse wave pattern that is illustrated as Fig. 2 B in side circuit, be that technical characterictic of the present invention is for convenience of description just done explanation with the first phase signal Sd1 of pulse wave pattern herein.In another embodiment of the present invention, phase detectors 102 of the present invention can also directly be coupled to charge pump 106, and first filter 1042 is coupled to the connection end point between phase detectors 102 and the charge pump 106, carry out filtering with signal to this connection end point, thus, the oscillogram of the first phase signal Sd1 will be same as the oscillogram of testing result Sdf1 after first filtering haply.Same, second filter 1044 also is applicable to above-mentioned technical characterictic.
Behind the filtering operation by first filter 1042, the waveform of the first phase signal Sd1 that phase detectors 102 are produced will become the waveform of testing result Sdf1 after first filtering.Can learn that from Fig. 2 B the waveform in each cycle of testing result Sdf1 is to rise lentamente and descend lentamente after first filtering, is not to present pulse shape as traditional phase-locked loop.Then, charge pump 106 will produce first electric current I 1 according to testing result Sdf1 after first filtering.Similarly, the waveform in each cycle of first electric current I 1 also is to rise lentamente and descend lentamente.Please note, in some cases, be under the imperfect situation that delay arranged for example at circuit, the pulse bandwidth of the first phase signal Sd1 can come longly than the phase difference between the first clock pulse S1 and the second clock pulse S2, and the part of its prolongation can produce corresponding second a phase signal Sd2, and then cause second electric current I 2 not to be zero current, but can have a current value less than first electric current I 1.Therefore in other words, in the case, phase detectors 102 also can produce the second phase signal Sd2, and testing result Sdf2 also can have the change in voltage of a correspondence after second filtering, shown in Fig. 2 B.And after first filtering after testing result Sdf1 and second filtering voltage of testing result Sdf2 by charge pump 106 will export control signal Sc after changeing the processing of electric current.In addition, the time width T in each cycle of the first phase signal Sd1 represents the phase place extent between the first clock pulse S1 and the second clock pulse S2.Further, the non-overlapped part of testing result Sdf2 after the testing result Sdf1 and second filtering after first filtering, that is the oblique line part in each cycle among the signal Sc1 of Fig. 2 B, and the area of each cycle oblique line part of signal Sc1 is the total current that corresponding charge pump 106 was produced in each cycle.Please note, this total current can equal the total current that the charge pump of the traditional phase-locked loop phase-locked loop of first filter 104 (that is do not have) is produced haply in each cycle, and the signal Sc1 among Fig. 2 B only is in order to the total electricity of the control signal Sc that charge pump 106 is exported to be described, in fact, charge pump 106 is exported only control signal Sc.The area of the waveform of the control signal that charge pump produced (that is the control signal Sa ' among corresponding Figure 1A) of tradition phase-locked loop can be equal to the area of the oblique line part among the signal Sc1 haply.Therefore, compared to traditional phase-locked loop, the present invention is arranged at first filter 1042 between phase detectors 102 and the charge pump 106, prolonging the stable state time (Settling Time) of first electric current I 1 that charge pump 106 produced, but its charge pump with traditional phase-locked loop is the same haply at the electric current that the phase produced weekly.
Then, 108 couples of control signal Sc of second filter operation of carrying out a low-pass filtering is to produce control signal Scf after the filtering.With respect to traditional phase-locked loop, because the control signal Sc cording of present embodiment has lower frequency, therefore the design of second filter 108 just can be loose many, that is can reduce the complexity of second filter 108 and then the cost of reduction clock generating circuit 100.For instance, the limit number of second filter 108 just can be come to such an extent that lack than traditional loop filter.Moreover, the frequency of control signal Sc in the clock generating circuit 100 of the present invention is lower, therefore control signal Scf will relatively level off to a straight line after the filtering that produced of second filter 108, and can not occur as the control signal Scon ' of traditional phase-locked loop at ripple (ripple) signal that each cycle produced.Thus, the may command oscillator 110 staggered attached signal (spur) that mixes that produces output clock pulse Sout just can improve significantly.In addition, in traditional phase-locked loop, the ripple signal can be transferred into the power end of other circuit by power line, and then influence the normal operation of other circuit (as a voltage controlled oscillator), and in the present embodiment, because the ripple signal of control signal Scf has been eliminated significantly after the filtering, so this problem has also been solved in the lump.On the other hand, can learn from above-mentioned disclosed technical characterictic, because present embodiment does not need to produce the control signal Sc of a pulse wave pattern, therefore just need not to design at a high speed a charge pump 106 and produce the control signal Sc of pulse wave pattern, so can further fall the cost of clock generating circuit 100.
Please refer to Fig. 3, shown in Figure 3 is the embodiment schematic diagram of thin portion circuit of phase detectors 102, first filter 104 and the charge pump 106 of clock generating circuit 100 of the present invention.Charge pump 106 includes one first current source 1062, one first switch 1064, one second current source 1066 and a second switch 1068.First current source 1062 includes a P type semiconductor field effect transistor M 1, and the one source terminal is coupled to one first supply voltage VDD, and a gate terminal receives one first reference voltage Vr1.First switch 1064 includes a P type semiconductor field effect transistor M 2, and the one source terminal is coupled to a drain electrode end of P type semiconductor field effect transistor M 1, and a gate terminal is coupled to first filter 1042 of first filter 104.Second current source 1066 includes a N type semiconductor field effect transistor M 3, and the one source terminal is coupled to a second source voltage GND, and a gate terminal receives one second reference voltage Vr2.Second switch 1068 includes a N type semiconductor field effect transistor M 4, the one source terminal is coupled to a drain electrode end of N type semiconductor field effect transistor M 3, one gate terminal is coupled to second filter 1044 of first filter 104, one drain electrode end couples the drain electrode end of P type semiconductor field effect transistor M 2, to form the output of charge pump 106, in order to output control signal Sc.First filter 1042 includes a capacity cell C1 and a resistive element R1.The one first end points Nc11 of capacity cell C1 is coupled to the gate terminal of P type semiconductor field effect transistor M 2, and the one second end points Nc12 of capacity cell C1 is coupled to the first supply voltage VDD.One first end points of resistive element R1 is coupled to the gate terminal of P type semiconductor field effect transistor M 2, and the one second end points Nr11 of resistive element R1 is coupled to phase detectors 102, is used for accepting the first phase signal Sd1.The first end points Nc11 that note that capacity cell C1 is used for exporting testing result Sdf1 after first filtering.In addition, second filter 1044 includes a capacity cell C2 and a resistive element R2.The one first end points Nc21 of capacity cell C2 is coupled to the gate terminal of N type semiconductor field effect transistor M 4, and the one second end points Nc22 of capacity cell C2 is coupled to second source voltage GND.One first end points of resistive element R2 is coupled to this gate terminal of N type semiconductor field effect transistor M 4, and the one second end points Nr21 of resistive element R2 is coupled to phase detectors 102, is used for accepting the second phase signal Sd2.The first end points Nc21 that note that capacity cell C2 is used for exporting testing result Sdf2 after second filtering.
When the phase detectors 102 output first phase signal Sd1, the low pass filter of being made up of capacity cell C1 and resistive element R1 will carry out filtering to produce testing result Sdf1 after first filtering in the first end points Nc11 of capacity cell C1 the second end points N2 of clock generating circuit 100 (that is corresponding to) to the first phase signal Sd1.Then, testing result Sdf1 controls P type semiconductor field effect transistor M 2 so that the P type semiconductor field effect transistor M 2 control signal Scs (that is current signal) of output shown in Fig. 2 B after first filtering.Please note, when the phase detectors 102 outputs second phase signal Sd2,1044 couples second phase signal Sd2 of second filter carry out filtering, and this field has knows that usually the knowledgeable ought to understand the running of second filter 1044 after reading above-mentioned disclosed invention, so do not give unnecessary details in addition.
On the other hand, though first filter 1042 shown in Figure 3 and second filter 1044 all are to do in fact with resistance capacitance (RC) filter, it is not as restriction of the present invention place.In another embodiment of the present invention, first filter 1042 and second filter 1044 can also only come to do in fact with a capacity cell.In other words, in this another embodiment, the gate terminal of P type semiconductor field effect transistor M 2 and N type semiconductor field effect transistor M 4 is directly to be coupled to phase detectors 102.
Please refer again to Fig. 2 A, in another embodiment of the present invention, first filter 104 of clock generating circuit 100 is integrated in the charge pump 106, so charge pump 106 directly receives the first phase signal Sd1 and the second phase signal Sd2.Shown in Figure 4 is the schematic diagram of charge pump 206 of another embodiment of clock generating circuit of the present invention.In other words, in the present embodiment, charge pump 206 includes one first filter 204, and wherein first filter 204 is used for this testing result (Sd1, Sd2) a to M signal of the signal path between the control signal Sc is carried out filtering operation.In addition, charge pump 206 includes one first current source 2062, one first transduction circuit 2064, one first current mirror 2066, one second current source, 2068, one second transduction circuits 2070, one second current mirror 2072 and one the 3rd current mirror 2074 in addition.First transduction circuit 2064 includes two N type semiconductor field effect transistor M 1 ', M2 ', and wherein N type semiconductor field effect transistor M 1 ', M2 ' constitute one differential to (Differential Pair) transduction circuit.First current mirror 2066 includes a P type semiconductor field effect transistor M 3 ' and a P type semiconductor field effect transistor M 4 ' that connects into diode pattern (diode-connected).Second transduction circuit 2070 includes two N type semiconductor field effect transistor M 5 ', M6 ', and wherein N type semiconductor field effect transistor M 5 ', M6 ' constitute one differential to (Differential Pair) transduction circuit.Second current mirror 2072 includes a P type semiconductor field effect transistor M 7 ' and a P type semiconductor field effect transistor M 8 ' that connects into the diode pattern.The 3rd current mirror 2074 includes a N type semiconductor field effect transistor M 9 ' and a N type semiconductor field effect transistor M 10 ' that connects into the diode pattern.
Further, first end points of first current source 2062 is coupled to the source terminal that one first supply voltage GND ' and second end points are coupled to N type semiconductor field effect transistor M 1 ', M2 '.The drain electrode end of P type semiconductor field effect transistor M 3 ' is coupled to the drain electrode end of N type semiconductor field effect transistor M 1 ', and the source terminal of P type semiconductor field effect transistor M 3 ' is coupled to a second source voltage VDD '.The gate terminal of P type semiconductor field effect transistor M 3 ' is coupled to the gate terminal of P type semiconductor field effect transistor M 4 '.The source terminal of P type semiconductor field effect transistor M 4 ' is coupled to second source voltage VDD '.Similarly, first end points of second current source 2068 is coupled to the source terminal that the first supply voltage GND ' and second end points are coupled to N type semiconductor field effect transistor M 5 ', M6 '.The drain electrode end of P type semiconductor field effect transistor M 7 ' is coupled to the drain electrode end of N type semiconductor field effect transistor M 5 ', and the source terminal of P type semiconductor field effect transistor M 8 ' is coupled to second source voltage VDD '.The gate terminal of P type semiconductor field effect transistor M 8 ' is coupled to the gate terminal of P type semiconductor field effect transistor M 7 '.The source terminal of P type semiconductor field effect transistor M 8 ' is coupled to second source voltage VDD '.It is one first electric current I 1 ' to be used for the receiving second phase signal Sd2 so that the second phase signal Sd2 is transduceed that the gate terminal of N type semiconductor field effect transistor M 1 ', M2 ' is coupled to phase detectors 102.First current mirror 2066 is second electric current I 2 ' with first electric current I, 1 ' reflection (mirror).Then, the 3rd current mirror 2074 is the 3rd electric current I 3 ' with second electric current I, 2 ' reflection.In like manner, the gate terminal of N type semiconductor field effect transistor M 5 ', M6 ' is coupled to phase detectors 102 to be used for receiving the first phase signal Sd1 being one the 4th electric current I 4 ' with first phase signal Sd1 transduction.Second current mirror 2072 is the 5th electric current I 5 ' with the 4th electric current I 4 ' reflection.In the present embodiment, the 3rd electric current I 3 ' that charge pump 106 is produced and the 5th electric current I 5 ' are used for producing control signal Sc, and are sent to second filter 108 of next stage.On the other hand, first filter 2042 of first filter 204 is coupled to the gate terminal between P type semiconductor field effect transistor M 7 ' and the P type semiconductor field effect transistor M 8 ', and second filter 2044 of first filter 204 is coupled to the gate terminal between P type semiconductor field effect transistor M 3 ' and the P type semiconductor field effect transistor M 4 '.Note that first filter 2042 is used for the first phase signal Sd1 is carried out filtering operation to one first voltage signal of the signal path between the control signal Sc (that is signal of P type semiconductor field effect transistor M 7 ' and the gate terminal of P type semiconductor field effect transistor M 8 ').Second filter 2044 is used for the second phase signal Sd2 is carried out filtering operation to one second voltage signal of the signal path between the control signal Sc (that is signal of P type semiconductor field effect transistor M 3 ' and the gate terminal of P type semiconductor field effect transistor M 4 ').In the present embodiment, though first filter 2042 and second filter 2044 all are to do in fact with a capacity cell, yet it is not as restriction of the present invention place.In other words, any filter with single limit is category of the present invention place.
When the phase detectors 102 outputs first phase signal Sd1, second transduction circuit 2070 is one the 4th electric current I 4 ' with first phase signal Sd1 transduction, because first filter 2042 is coupled between the gate terminal and second source voltage VDD ' of P type semiconductor field effect transistor M 7 ', therefore the voltage level on the gate terminal of P type semiconductor field effect transistor M 7 ' can't change moment, but testing result Sdf1 changes after first filtering shown in Fig. 2 B, thus, flow through the 5th electric current I 5 ' of P type semiconductor field effect transistor M 8 ' also can have similar waveform.In like manner, when the phase detectors 102 outputs second phase signal Sd2, the existence of second filter 2044 also can make that control signal Sc has similar technical characterictic, this field has knows that usually the knowledgeable ought to understand the running of second filter 2044 after reading above-mentioned disclosed invention, so do not give unnecessary details in addition.
Please refer to Fig. 5.Shown in Figure 5 is an embodiment flow chart of a kind of clock pulse generation methods 500 of the present invention.The clock pulse generation methods 500 of present embodiment can Fig. 2 A clock generating circuit 100 realized that therefore follow-up method of operation about clock pulse generation methods 500 is that collocation clock generating circuit 100 illustrates.This field has knows that usually the knowledgeable should understand, and realizes that with clock generating circuit 100 clock pulse generation methods 500 only is spiritual place of the present invention for convenience of description, and it is not as restriction of the present invention.Moreover if can reach identical result substantially, the sequence of steps that does not need necessarily to shine in the flow process shown in Figure 5 is carried out, and step shown in Figure 5 not necessarily will carry out continuously, that is other step also can be inserted wherein.Clock pulse generation methods 500 includes the following step:
Step 502: detect this phase difference between the first clock pulse S1 and the second clock pulse S2 to produce a testing result (Sd1, Sd2);
Step 504: this testing result is carried out filtering operation;
Step 506: utilize charge pump 106 to produce control signal Sc according to filtered this testing result (Sdf1, Sdf2);
Step 508: control signal Sc is carried out filtering operation; And
Step 510: produce output clock pulse Sout according to filtered this control signal (Scf), wherein export clock pulse Sout and be used for producing the second clock pulse S2.
In step 502, testing result includes the first phase signal Sd1 and the second phase signal Sd2.In step 504, the filtering operation that testing result is carried out includes and utilizes first filter 1042 to come the first phase signal Sd1 is carried out filtering operation and utilizes second filter 1044 to come the second phase signal Sd2 is carried out filtering operation, and wherein charge pump 106 produces control signal Sc according to filtered first phase signals (Sdf1) and filtered second phase signal (Sdf2).In step 506, since after first filtering after the testing result Sdf1 and second filtering waveform of testing result Sdf2 be not the pulse wave signal that produces as traditional phase-locked loop, but rising lentamente and descend lentamente shown in Fig. 2 B, so control signal Sc also can have similar waveform.In step 508,108 couples of control signal Sc of second filter carry out this second filtering operation to produce control signal Scf after the filtering, and its waveform is illustrated in Fig. 2 B.Compared to traditional phase-locked loop, control signal Scf will relatively level off to a straight line after the filtering, and can not occur as the control signal Scon ' of traditional phase-locked loop at ripple (ripple) signal (arrow place) that each cycle produced.
Please refer to Fig. 6.Shown in Figure 6 is an embodiment flow chart of a kind of clock pulse generation methods 600 of the present invention.The clock pulse generation methods 600 of present embodiment can Fig. 2 A the charge pump 206 of clock generating circuit 100 collocation Fig. 4 realized that therefore follow-up method of operation about clock pulse generation methods 600 is that collocation clock generating circuit 100 illustrates with charge pump 206.Clock pulse generation methods 600 includes the following step:
Step 602: detect this phase difference between the first clock pulse S1 and the second clock pulse S2 to produce a testing result (Sd1, Sd2);
Step 604: utilize charge pump 206 to produce control signal Sc, and this testing result a to M signal of the signal path between the control signal Sc is carried out filtering operation according to this testing result;
Step 606: control signal Sc is carried out filtering operation; And
Step 608: produce output clock pulse Sout according to filtered control signal (Scf), wherein export clock pulse Sout and be used for producing the second clock pulse S2.
In the clock pulse generation methods 600 of present embodiment, testing result also includes the first phase signal Sd1 and the second phase signal Sd2, and step 604 includes in addition: a) utilize first filter 2042 to come the first phase signal Sd1 is carried out filtering operation to one first voltage signal of the signal path between the control signal Sc; And b) utilize second filter 2044 to come the second phase signal Sd2 is carried out filtering operation to one second voltage signal of the signal path between the control signal Sc.
In sum, with respect to traditional phase-locked loop, the loop filter in the clock generating circuit 100 of the present invention has lower cost of manufacture.Moreover, because the frequency of control signal Sc is lower, and then make after the filtering that loop filter produced control signal Scf will relatively level off to a straight line, and can not occur as the control signal Scon ' of traditional phase-locked loop at ripple (ripple) signal that each cycle produced.Thus, the staggered attached signal (spur) that mixes of the output clock pulse Sout that produced of may command oscillator 110 just can improve significantly.On the other hand, because present embodiment does not need to produce the control signal Sc of a pulse wave pattern, therefore just need not to design the control signal Sc that at a high speed a charge pump 106 produces the pulse wave pattern, further to fall the cost of clock generating circuit 100.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to spirit of the present invention and the application's claim scope change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. clock generating circuit includes:
One phase detectors are used for detecting the phase difference between one first clock pulse and one second clock pulse, to produce a testing result;
One first filter is used for this testing result is carried out filtering operation;
One charge pump is used for producing a control signal according to filtered this testing result;
One second filter is used for this control signal is carried out filtering operation; And
One may command oscillator is used for producing an output clock pulse according to filtered this control signal, and wherein this output clock pulse is used for producing this second clock pulse.
2. clock generating circuit according to claim 1 is characterized in that, this testing result includes one first phase signal and one second phase signal, and this first filter includes:
One first filter is used for this first phase signal is carried out filtering operation; And
One second filter is used for this second phase signal is carried out filtering operation.
3. clock generating circuit according to claim 2 is characterized in that, this charge pump produces this control signal according to filtered this first phase signal and filtered this second phase signal.
4. clock generating circuit according to claim 2 is characterized in that, this first, second filter is all the low pass filter with single limit.
5. clock generating circuit according to claim 2 is characterized in that, this charge pump includes:
One first current source, one first end points is coupled to one first reference voltage;
One first switch has a control end points and is coupled to this first filter, and one first is coupled to one second end points of this first current source with reference to end points, and one second with reference to end points;
One second current source, one first end points is coupled to one second reference voltage; And
One second switch has a control end points and is coupled to this second filter, and one first is coupled to one second end points of this second current source with reference to end points, and one second couple this first switch with reference to end points this second with reference to end points, in order to export this control signal.
6. clock generating circuit according to claim 5, it is characterized in that, this first filter includes a capacity cell, and one first end points of this capacity cell is coupled to this control end points of this first switch, and one second end points of this capacity cell is coupled to a voltage source.
7. clock generating circuit according to claim 6, it is characterized in that, this first filter includes a resistive element in addition, and one first end points of this resistive element is coupled to this control end points of this first switch, and one second end points of this resistive element is used for accepting this first phase signal.
8. clock generating circuit includes:
One phase detectors are used for detecting the phase difference between one first clock pulse and one second clock pulse, to produce a testing result;
One charge pump is used for producing a control signal according to this testing result, and this charge pump includes:
One first filter is used for this testing result to the M signal between this control signal is carried out filtering operation;
One second filter is used for this control signal is carried out filtering operation; And
One may command oscillator is used for producing an output clock pulse according to filtered this control signal, and wherein this output clock pulse is used for producing this second clock pulse.
9. clock generating circuit according to claim 8 is characterized in that, this testing result includes one first phase signal and one second phase signal, and this first filter includes:
One first filter is used for this first phase signal to one first voltage signal between this control signal is carried out filtering operation; And
One second filter is used for this second phase signal to one second voltage signal between this control signal is carried out filtering operation.
10. clock generating circuit according to claim 9 is characterized in that, at least one filter includes a capacity cell in this first, second filter.
11. a clock pulse generation methods includes:
Detect the phase difference between one first clock pulse and one second clock pulse, to produce a testing result;
This testing result is carried out filtering operation;
Utilize a charge pump to come to produce a control signal according to filtered this testing result;
This control signal is carried out filtering operation; And
Produce an output clock pulse according to filtered this control signal, wherein this output clock pulse is used for producing this second clock pulse.
12. clock pulse generation methods according to claim 11 is characterized in that, this testing result includes one first phase signal and one second phase signal, and the step that this testing result is carried out filtering operation is included:
Utilize one first filter to come this first phase signal is carried out filtering operation; And
Utilize one second filter to come this second phase signal is carried out filtering operation.
13. clock pulse generation methods according to claim 12 is characterized in that, this charge pump produces this control signal according to filtered this first phase signal and filtered this second phase signal.
14. clock pulse generation methods according to claim 12 is characterized in that, this first, second filter is all the low pass filter with single limit.
15. a clock pulse generation methods includes:
Detect the phase difference between one first clock pulse and one second clock pulse, to produce a testing result;
Utilize a charge pump to produce a control signal, and this testing result to the M signal between this control signal is carried out filtering operation according to this testing result;
This control signal is carried out filtering operation; And
Produce an output clock pulse according to filtered this control signal, wherein this output clock pulse is used for producing this second clock pulse.
16. clock pulse generation methods according to claim 15, it is characterized in that, this testing result includes one first phase signal and one second phase signal, and this testing result to the step that this M signal between this control signal carries out filtering operation is included:
Utilize one first filter to come this first phase signal to one first voltage signal between this control signal is carried out filtering operation; And
Utilize one second filter to come this second phase signal to one second voltage signal between this control signal is carried out filtering operation.
17. clock pulse generation methods according to claim 16 is characterized in that, this first, second filter is all the low pass filter with single limit.
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| CN201010190098.3A CN102255614B (en) | 2010-05-20 | 2010-05-20 | Clock generation circuit and clock generation method |
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| CN201010190098.3A CN102255614B (en) | 2010-05-20 | 2010-05-20 | Clock generation circuit and clock generation method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1108662C (en) * | 1996-09-24 | 2003-05-14 | 三菱电机半导体软件株式会社 | PLL circuit |
| EP1693967A1 (en) * | 2003-12-10 | 2006-08-23 | Matsushita Electric Industrial Co., Ltd. | Delta-sigma type fraction division pll synthesizer |
| CN101471624A (en) * | 2007-12-29 | 2009-07-01 | 瑞昱半导体股份有限公司 | Voltage-controlled oscillator |
| CN101494457A (en) * | 2008-01-25 | 2009-07-29 | 奇景光电股份有限公司 | Delay locked loop circuit and method for eliminating jitter and offset therein |
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2010
- 2010-05-20 CN CN201010190098.3A patent/CN102255614B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1108662C (en) * | 1996-09-24 | 2003-05-14 | 三菱电机半导体软件株式会社 | PLL circuit |
| EP1693967A1 (en) * | 2003-12-10 | 2006-08-23 | Matsushita Electric Industrial Co., Ltd. | Delta-sigma type fraction division pll synthesizer |
| CN101471624A (en) * | 2007-12-29 | 2009-07-01 | 瑞昱半导体股份有限公司 | Voltage-controlled oscillator |
| CN101494457A (en) * | 2008-01-25 | 2009-07-29 | 奇景光电股份有限公司 | Delay locked loop circuit and method for eliminating jitter and offset therein |
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| CN102255614B (en) | 2017-04-19 |
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Effective date of registration: 20201022 Address after: No. 1, Xingzhu Road, Hsinchu Science Park, Taiwan, China Patentee after: MEDIATEK Inc. Address before: 518057, Guangdong, Shenzhen hi tech Zone, South District, science and technology, South ten road, Shenzhen Institute of Aerospace Science and technology innovation, C block, building 4 Patentee before: Mstar Semiconductor,Inc. Patentee before: MEDIATEK Inc. Effective date of registration: 20201022 Address after: 4 / F, block C, Shenzhen Aerospace Science and Technology Innovation Research Institute, science and technology south 10th Road, South District, Shenzhen high tech Zone, Guangdong Province Patentee after: Mstar Semiconductor,Inc. Patentee after: MEDIATEK Inc. Address before: 518057, Guangdong, Shenzhen hi tech Zone, South District, science and technology, South ten road, Shenzhen Institute of Aerospace Science and technology innovation, C block, building 4 Patentee before: Mstar Semiconductor,Inc. Patentee before: MSTAR SEMICONDUCTOR Inc. |
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