CN102254891A - Flip chip packaging structure and manufacturing method thereof - Google Patents
Flip chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN102254891A CN102254891A CN2011102202803A CN201110220280A CN102254891A CN 102254891 A CN102254891 A CN 102254891A CN 2011102202803 A CN2011102202803 A CN 2011102202803A CN 201110220280 A CN201110220280 A CN 201110220280A CN 102254891 A CN102254891 A CN 102254891A
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- layer
- metal
- chip
- lead wire
- metal lead
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
The invention provides a flip chip packaging structure and a manufacturing method thereof. The flip chip packaging structure comprises a printed circuit board (PCB), a chip, glass fiber and a plastic package material, wherein the printed circuit board is provided with a metal lead layer and a metal I/O (Input/Output) layer used for electrical connection with an external terminal; the chip is arranged on the metal lead layer of the printed circuit board in a flip manner; the glass fiber is arranged at the edge of the metal lead layer of the printed circuit board and surrounds the chip; the plastic package material is used for packaging the chip; and the metal lead layer of the printed circuit board is electrically connected with the metal I/O layer through use of an anisotropism conductive material. According to the flip chip packaging structure and the manufacturing method thereof provided by the embodiment of the invention, the anisotropism conductive material is used for replacing a through hole formed in the PCB, thus the production process is simplified and the production cost is reduced.
Description
Technical field
The present invention relates to the Flip-Chip Using field, more particularly, the present invention relates to a kind of flip chip packaging structure and manufacture method thereof of utilizing the electrical connection between the conductive layer that anisotropic conductive material realizes PCB.
Background technology
The trend of current electronic product is continuous integrated increasing device and function in a compact package or complete machine, and the encapsulation technology that therefore increases the packaging density that comprises active and passive device seems particularly important.
Chip on board technology (Chip-on-Board, COB) be referred to as chip directly placed technology (Direct Chip Attach, DCA), be adopt bonding agent or automatically methods such as tape welding, wire bond, flip chip bonding exposed integrated circuit (IC) chip directly is mounted on a technology on the circuit board.The COB technology comprises Wire Bonding Technology, tape automated bonding technology and flip-chip (Flip Chip) technology.Specifically, flip-chip in the face of substrate, is realized the interconnection of chip and substrate with the chip active area by the solder bump that presents arrayed on the chip.
The encapsulating structure of flip-chip of the prior art is described with reference to Fig. 1 below.Fig. 1 shows the schematic diagram according to the encapsulating structure of the flip-chip of prior art.
As shown in Figure 1, the encapsulating structure according to the flip-chip of prior art comprises: PCB 100, and chip 10 is arranged on the PCB 100; Metal level 20 and 30 lays respectively on the upper and lower surface of PCB 100; Through hole 40 is formed among the PCB 100 and utilizes metal that metal level 20 and metal level 30 is electrically connected; Projection 50 between chip 10 and metal level 20, is used for chip 10 is electrically connected to PCB 100; Epoxy encapsulation material (EMC) is used to seal PCB 100 and realizes encapsulation.
By above-mentioned flip chip packaging structure as can be known, flip chip packaging structure shown in Figure 1 is realized the electrical connection between the multiple layer metal layer of PCB by the technology of filling metal in passing the through hole of PCB.For COB PCB simple in structure, the cost of above-mentioned encapsulating structure is higher.Therefore, demand the encapsulating structure of a kind of technology flip-chip simple and with low cost urgently.
Summary of the invention
But the object of the present invention is to provide a kind of simplified manufacturing technique and flip chip packaging structure that reduces cost and manufacture method thereof.
To achieve these goals, the invention provides a kind of flip chip packaging structure, described flip chip packaging structure comprises: printed circuit board (PCB), the metal I/O layer that has the metal lead wire layer and be used for being electrically connected with outside terminal; Chip, upside-down mounting are installed on the metal lead wire layer of printed circuit board (PCB); Glass fibre, the edge that is arranged on the metal lead wire layer of printed circuit board (PCB) also centers on described chip; Plastic packaging material is used to seal described chip, and wherein, the metal lead wire layer of printed circuit board (PCB) is electrically connected by anisotropic conductive material with metal I/O layer.
In exemplary embodiment according to the present invention, described anisotropic conductive material can be anisotropy conductiving glue or anisotropic conductive film, and projection can be arranged on the described metal I/O layer and is arranged in anisotropic conductive material.
In order to realize purpose of the present invention, the present invention also provides a kind of method of making flip chip packaging structure, and the step that described method comprises has: provide the edge to be provided with the metal lead wire frame of glass fibre; Described metal lead wire frame is arranged on the supporting layer; Flip-chip is electrically connected on described metal lead wire frame and with metal lead wire frame; Inject plastic packaging material and come encapsulate chip; Remove described supporting layer; Utilize anisotropic conductive material that metal I/O layer is sticked on the metal lead wire frame.
In exemplary embodiment according to the present invention, described anisotropic conductive material can be anisotropy conductiving glue or anisotropic conductive film.Projection can be arranged on the described metal I/O layer and be arranged in anisotropic conductive material.
Description of drawings
Fig. 1 is the schematic diagram that flip chip packaging structure of the prior art is shown;
Fig. 2 shows the schematic diagram of flip chip packaging structure according to an exemplary embodiment of the present invention;
Fig. 3 shows the plan view from above of the PCB in the flip chip packaging structure according to an exemplary embodiment of the present invention;
Fig. 4 shows the floor map of the metal I/O layer in the flip chip packaging structure according to an exemplary embodiment of the present invention;
Fig. 5 to Fig. 8 shows the schematic diagram of making the method for flip chip packaging structure according to exemplary embodiment of the present invention.
Embodiment
Below, describe embodiments of the invention in detail with reference to accompanying drawing.
Fig. 2 shows the schematic diagram of flip chip packaging structure according to an exemplary embodiment of the present invention, Fig. 3 shows the plan view from above of the PCB in the flip chip packaging structure according to an exemplary embodiment of the present invention, and Fig. 4 shows the floor map of the metal I/O layer in the flip chip packaging structure according to an exemplary embodiment of the present invention.
With reference to Fig. 2, flip chip packaging structure 200 comprises PCB100 ' according to an exemplary embodiment of the present invention, comprises metal lead wire 20, metal I/O layer 30 and the anisotropic conductive material layer 40 between metal lead wire 20 and metal I/O layer 30; Chip 10, upside-down mounting is on metal lead wire 20; Projection 50 is arranged on the metal I/O layer 30 and is positioned at anisotropic conductive material layer 40; Projection 60 is electrically connected to metal lead wire 20 between chip 10 and metal lead wire 20 and with chip 10,, be electrically connected to PCB 100 ' that is; Glass fibre 70 is used for fixing PCB 100 '; EMC 80, are filled between the glass fibre 70, are used for plastic packaging and protect chip 10.
(a) among Fig. 3 and (b) show the plan view from above of PCB according to an exemplary embodiment of the present invention respectively.Shown in (a) among Fig. 3, PCB 100 ' comprises metal lead wire 20, metal I/O layer (not shown) and glass fibre 70.Equally, shown in (b) among Fig. 3, PCB 100 ' comprises metal lead wire 20, metal I/O layer (not shown) and glass fibre 70.Metal lead wire 20 and metal I/O layer (not shown) are fixed on glass fibre 70 belows, and are provided with anisotropic conductive material layer 40 between metal lead wire 20 and metal I/O layer 30 (not shown).(a) in Fig. 3 and (b) in, the shape difference of metal lead wire 20.Specifically, in (a) in Fig. 3, metal lead wire 20 becomes emitting shape along the diagonal of whole PCB, and in (b) in Fig. 3, metal lead wire 20 is arranged as a plurality of parallel line segments.Therefore, the shape of metal lead wire 20 can be set as required, the invention is not restricted to this.
As shown in Figure 4, in PCB 100 ' according to an exemplary embodiment of the present invention, the shape of metal I/O layer 30 designs as required, the invention is not restricted to this.In Fig. 4, projection 50 is formed on the metal I/O layer 30.
Extremely shown in Figure 4 as Fig. 2, when pressure being applied to PCB 100 ', anisotropic conductive material layer 40 can be realized being electrically connected, promptly, metal lead wire 20 and metal I/O layer 30 are electrically connected by anisotropic conductive material layer 40, and the pad on the chip 10 is electrically connected to metal lead wire 20 by projection 60.Therefore, connection and the distribution between pad on the chip 10 and the metal I/O layer 30 is achieved.
The characteristic of anisotropic conductive material is that the part that is under pressure realizes conducting, and other parts (being not applied to the part of pressure) keep open circuit.In an embodiment according to the present invention, anisotropic conductive material layer 40 can be anisotropic conductive film (ACF) or anisotropic conductive cream (ACP).
Fig. 5 to Fig. 8 shows the schematic diagram of making the method for flip chip packaging structure according to exemplary embodiment of the present invention.
At first, provide lead frame, as (a) among Fig. 3 or (b).Specifically, glass fibre is processed an opening, the glass fibre that will have opening then is bonded in the metal level top, and will be exposed to the shape that metal level in the opening is processed into required lead frame.The method of processing lead frame can adopt the method that is fit in the prior art.
Shown in (a) among Fig. 5, the lead frame that provides is arranged on the supporting layer 90, then chip 10 is utilized projection 60 (not shown) upside-down mountings to be installed on the metal lead wire 20.(b) among Fig. 5 shows the vertical view of finishing after the above-mentioned steps.
Shown in (a) among Fig. 6, utilize EMC 80 to encapsulate and protect chip 10.(b) among Fig. 6 shows the vertical view of finishing after the above-mentioned steps.
Shown in (a) among Fig. 7, remove supporting layer 90, adhere to the anisotropic conductive material layer 40 such as ACF or ACP then below metal lead wire 20, the upper surface that at last upper surface is provided with the metal I/O layer 30 of projection invests the lower surface of anisotropic conductive material layer 40.(b) among Fig. 7 shows the vertical view of finishing after the above-mentioned steps.
In an embodiment of the present invention, supporting layer 90 can be the plastic film class material of viscosity, and can mechanically supporting layer 90 be peeled off.Alternatively, supporting layer 90 also can be ultraviolet irradiation adhesive tape (UV tape), in this case, can peel off by nature after the ultraviolet irradiation adhesive tape loses viscosity.
According to the step of above-mentioned Fig. 5 to Fig. 7, finally obtained the encapsulating structure of the flip-chip of encapsulation as shown in Figure 8.In structure as shown in Figure 8, chip is electrically connected to metal lead wire by projection, and metal lead wire is electrically connected to metal I/O layer 30 by projection and anisotropic conductive material layer 40, and metal I/O layer 30 is electrically connected to outside terminal.That is to say, realize being electrically connected of chip and external devices by two metal levels that use anisotropic conductive material layer incoming call connection PCB.
Therefore, in an embodiment according to the present invention, when pressure is applied to flip chip packaging structure, anisotropic conductive material can be realized being electrically connected, specifically, the metal I/O layer of PCB is electrically connected by anisotropic conductive material with the metal lead wire layer of PCB, and bonding pads is electrically connected to the metal lead wire layer of PCB by projection, thereby has realized the electrical connection between the metal I/O layer of bonding pads and PCB.
In an embodiment according to the present invention, owing to use anisotropic conductive material to replace through hole, so production technology is simple relatively and reduced cost such as ACF or ACP.In addition, in an embodiment according to the present invention, only just can be applied to different chips easily by the shape that changes metal lead wire.
Although described the present invention, the invention is not restricted to embodiment set forth herein in conjunction with exemplary embodiment.Under the situation that does not break away from the spirit or scope of the present invention, can make various modifications in form and details.
Claims (6)
1. flip chip packaging structure, described flip chip packaging structure comprises:
Printed circuit board (PCB), the metal I/O layer that has the metal lead wire layer and be used for being electrically connected with outside terminal;
Chip, upside-down mounting are installed on the metal lead wire layer of printed circuit board (PCB);
Glass fibre, the edge that is arranged on the metal lead wire layer of printed circuit board (PCB) also centers on described chip;
Plastic packaging material is used to seal described chip,
Wherein, the metal lead wire layer of printed circuit board (PCB) is electrically connected by anisotropic conductive material with metal I/O layer.
2. flip chip packaging structure according to claim 1 is characterized in that described anisotropic conductive material is anisotropy conductiving glue or anisotropic conductive film.
3. flip chip packaging structure according to claim 2 is characterized in that projection is arranged on the described metal I/O layer and is arranged in anisotropic conductive material.
4. method of making flip chip packaging structure, the step that described method comprises has:
Provide the edge to be provided with the metal lead wire frame of glass fibre;
Described metal lead wire frame is arranged on the supporting layer;
Flip-chip is electrically connected on described metal lead wire frame and with metal lead wire frame;
Inject plastic packaging material and come encapsulate chip;
Remove described supporting layer;
Utilize anisotropic conductive material that metal I/O layer is sticked on the metal lead wire frame.
5. method according to claim 4 is characterized in that described anisotropic conductive material is anisotropy conductiving glue or anisotropic conductive film.
6. method according to claim 4 is characterized in that projection is arranged on the described metal I/O layer and is arranged in anisotropic conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011102202803A CN102254891A (en) | 2011-08-01 | 2011-08-01 | Flip chip packaging structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011102202803A CN102254891A (en) | 2011-08-01 | 2011-08-01 | Flip chip packaging structure and manufacturing method thereof |
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| CN102254891A true CN102254891A (en) | 2011-11-23 |
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| CN2011102202803A Pending CN102254891A (en) | 2011-08-01 | 2011-08-01 | Flip chip packaging structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258820A (en) * | 2013-04-09 | 2013-08-21 | 北京兆易创新科技股份有限公司 | Reinforced SPI port Flash chip and chip packing method |
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| US6287894B1 (en) * | 1999-10-04 | 2001-09-11 | Andersen Laboratories, Inc. | Acoustic device packaged at wafer level |
| US20030017327A1 (en) * | 2001-07-19 | 2003-01-23 | Korea Advanced Institute Of Science And Technology | High adhesion triple layered anisotropic conductive adhesive film |
| KR20030033706A (en) * | 2001-10-24 | 2003-05-01 | 앰코 테크놀로지 코리아 주식회사 | Flipchip Package |
| US20040177921A1 (en) * | 2001-06-29 | 2004-09-16 | Akira Yamauchi | Joining method using anisotropic conductive adhesive |
| TW200710934A (en) * | 2005-09-09 | 2007-03-16 | Int Semiconductor Tech Ltd | Chip module having a flip chip mounted on a metal film (COM), a chip card and the metal film carrier |
| CN1977574A (en) * | 2005-02-03 | 2007-06-06 | 松下电器产业株式会社 | Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device and electronic device using multilayer wiring board |
| CN101303984A (en) * | 2001-06-07 | 2008-11-12 | 株式会社瑞萨科技 | Method of manufacturing semiconductor device |
| CN101363128A (en) * | 2007-08-07 | 2009-02-11 | 恩伊凯慕凯特股份有限公司 | Non-cyanogen type electrolytic gold plating bath for bump forming |
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2011
- 2011-08-01 CN CN2011102202803A patent/CN102254891A/en active Pending
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| JPS60142595A (en) * | 1983-12-29 | 1985-07-27 | ソニー株式会社 | Method of connecting electronic part |
| JP2000138243A (en) * | 1998-10-30 | 2000-05-16 | Optrex Corp | Semiconductor mounting structure |
| US6287894B1 (en) * | 1999-10-04 | 2001-09-11 | Andersen Laboratories, Inc. | Acoustic device packaged at wafer level |
| CN101303984A (en) * | 2001-06-07 | 2008-11-12 | 株式会社瑞萨科技 | Method of manufacturing semiconductor device |
| US20040177921A1 (en) * | 2001-06-29 | 2004-09-16 | Akira Yamauchi | Joining method using anisotropic conductive adhesive |
| US20030017327A1 (en) * | 2001-07-19 | 2003-01-23 | Korea Advanced Institute Of Science And Technology | High adhesion triple layered anisotropic conductive adhesive film |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258820A (en) * | 2013-04-09 | 2013-08-21 | 北京兆易创新科技股份有限公司 | Reinforced SPI port Flash chip and chip packing method |
| WO2014166172A1 (en) * | 2013-04-09 | 2014-10-16 | 北京兆易创新科技股份有限公司 | Spi interface enhanced flash chip and chip packaging method |
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| US9836236B2 (en) | 2013-04-09 | 2017-12-05 | Gigadevice Semiconductor (Beijing) Inc. | SPI interface enhanced flash chip and chip packaging method |
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Application publication date: 20111123 |