CN102254531A - Liquid crystal display driving circuit - Google Patents
Liquid crystal display driving circuit Download PDFInfo
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- CN102254531A CN102254531A CN 201110199576 CN201110199576A CN102254531A CN 102254531 A CN102254531 A CN 102254531A CN 201110199576 CN201110199576 CN 201110199576 CN 201110199576 A CN201110199576 A CN 201110199576A CN 102254531 A CN102254531 A CN 102254531A
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Abstract
The invention discloses a liquid crystal display driving circuit for reducing the area of a pull-down thin film transistor so as to facilitate circuit layout. The discharge time of a node, namely, a connecting point of a first capacitor and a gate electrode of a second transistor, is prolonged by modulating the sizes of a fifth transistor and a sixth transistor, so that shutdown of the second transistor is delayed, and an output node connected with the second pole of the second transistor discharges current.
Description
Technical field
The present invention relates to a kind of liquid crystal display drive circuit, relate in particular to a kind of minimizing pull-down (Pull-down) thin film transistor (TFT) area, so that the circuit framework of circuit layout.
Background technology
In recent years, for reducing the cost of panel, the gate drive circuit of active LCD adopts the thin-film transistor technologies design to become the trend of main flow gradually.Yet, the drift that the amorphous silicon film transistor element can produce critical voltage because long use or high forward bias apply, cause thin film transistor (TFT) (Thin-Film Transistor, hereinafter to be referred as TFT) current driving capability significantly reduce, make the output waveform distortion of driving circuit, and then have influence on the degree of stability of driving circuit, and cause the display quality of picture to descend.
In addition, because the signal source that gate drive circuit provided is periodic alternating voltage signal, therefore, when voltage signal is changed, if output node is the state of suspension joint (floating), then be easy to generate capacitance coupling effect (capacitor coupling effect), make drive wire institute output waveform that fluctuation take place and allow image display quality descend, even cause the situation of misoperation to take place.
In view of the tft placement area of classic method bigger, for the LCD of light and handy formula, no unnecessary space can layout, in addition, traditional output node noise is more, also causes image quality to descend, moreover existing circuit is done sth. in advance aging because of frequent certain several thin film transistor (TFT) that drive, cause the life-span of driving circuit integral body to shorten, it is soluble that above-mentioned problem is all the technology of the present invention content.
Summary of the invention
Based on the shortcoming that solves the above prior art, the invention provides a kind of liquid crystal display drive circuit, fundamental purpose is for reducing pull-down (Pull-down) thin film transistor (TFT) area, so that circuit layout, this node of the tie point of the gate of first electric capacity and transistor seconds, can be by modulation the 5th transistor AND gate the 6th transistorized size to prolong discharge time, make the transistor seconds late release, this output node earial drainage that connects with second utmost point that helps this transistor seconds.
Another purpose of the present invention is to reduce the output node noise, and when the second clock pulse signal transferred noble potential to by electronegative potential, the 3rd transistor AND gate the 5th transistor can periodically be opened node one earial drainage path, with the wave phenomenon that prevents to be produced because of suspension joint.
Another object of the present invention is to slow down the 3rd transistor and the 5th transistorized drift voltage to prolong the bulk life time of driving circuit.
For reaching above-mentioned purpose, this is a kind of liquid crystal display drive circuit, comprising:
A plurality of shift registors of serial connection, and each shift registor more comprises:
The first transistor comprises first utmost point, second utmost point and gate, and wherein first utmost point of this first transistor couples mutually with the gate of this first transistor;
Transistor seconds, comprise first utmost point, second utmost point and gate, wherein the gate of this transistor seconds couples second utmost point of this first transistor, first utmost point of this transistor seconds couples the second clock pulse signal, and second utmost point of this transistor seconds connects output node, be connected with one first electric capacity between second utmost point of the gate of this transistor seconds and this transistor seconds, and the tie point of the gate of this first electric capacity and transistor seconds is a node;
The 3rd transistor comprises first utmost point, second utmost point and gate, and wherein the 3rd transistorized first utmost point couples second utmost point of this transistor seconds, and the 3rd transistorized second utmost point is coupled to earth point;
The 4th transistor, comprise first utmost point, second utmost point and gate, wherein the 4th transistorized second utmost point couples the 3rd transistorized gate, the 4th transistorized first utmost point couples the 3rd clock pulse signal, and the 4th transistorized second utmost point is coupled with one second electric capacity;
The 5th transistor, comprise first utmost point, second utmost point and gate, wherein the 5th transistorized gate couples the 4th transistorized second utmost point, the 5th transistorized first utmost point couples second utmost point of this first transistor, and the 5th transistorized second utmost point couples this earth point;
The 6th transistor comprises first utmost point, second utmost point and gate, and wherein the 6th transistorized first utmost point couples mutually with the 6th transistorized gate, the 6th transistorized second utmost point coupling the 5th transistorized gate;
The 7th transistor comprises first utmost point, second utmost point and gate, and the 7th transistorized gate couples first clock pulse signal, the 7th transistorized first utmost point coupling the 5th transistorized gate, the 7th transistorized second utmost point couples this earth point; And
The 8th transistor comprises first utmost point, second utmost point and gate, and the 8th transistorized gate couples this second clock pulse signal, first utmost point of the 8th transistorized first this first transistor of utmost point coupling, the 8th transistorized second utmost point couples this earth point.
First utmost point of this first transistor more receives the output signal of being sent by previous shift registor.
The 6th transistorized gate more receives by a back output signal that shift registor is sent.
This node of the tie point of the gate of this first electric capacity and transistor seconds, can be by modulation the 5th transistor AND gate the 6th transistor size to prolong discharge time, make the transistor seconds late release, this output node earial drainage that connects with second utmost point that helps this transistor seconds.
When this second clock pulse signal went to noble potential by electronegative potential, the 3rd transistor AND gate the 5th transistor can periodically be opened, so that this node and this output node earial drainage.
The size of this modulation second electric capacity can be slowed down the 3rd transistor and the 5th transistorized drift voltage.
This shift scratch circuit is arranged on the glass substrate.
Those transistors are amorphous silicon film transistor.
Those transistors are nmos pass transistor.
For structure purpose of the present invention and effect are had further understanding, cooperate illustrated example to be described in detail as follows.
Description of drawings
Fig. 1 is the control circuit form and function block schematic diagram of LCD of the present invention;
Fig. 2 A, Fig. 2 B are respectively the comparatively detailed circuit framework and the waveform signal synoptic diagram of driving circuit of the present invention;
Fig. 3 A～Fig. 8 B is that illustration is implemented in the action of Fig. 2 A and Fig. 2 B circuit;
Fig. 9 A, Fig. 9 B are the waveform influence synoptic diagram of the 5th transistor after fall time.
Embodiment
Below with reference to the accompanying drawings to describe the present invention for reaching employed technological means of purpose and effect, and only be aid illustration with the cited embodiment of accompanying drawing, technological means of the present invention is not limited to cited accompanying drawing.
Fig. 1 is the inside structure of LCD 1, include liquid crystal display panel of thin film transistor 11, a data driving circuit 12, one drive circuit 13 and time schedule controller 14, wherein time schedule controller 14 is in order to receive a plurality of shift registors 15 that a control signal and driving circuit 13 comprise serial connection.Is traditional electronic installation about liquid crystal display panel of thin film transistor 11, data driving circuit 12 with time schedule controller 14, gives unnecessary details so do not do one at this.
Fig. 2 A, Fig. 2 B are respectively the comparatively detail circuits framework and the waveform signal synoptic diagram of displacement working storage 15 of the present invention, it comprises: the first transistor T1, it comprises first utmost point, second utmost point and gate, and wherein first utmost point of this first transistor T1 couples mutually with the gate of this first transistor T1; Transistor seconds T2, comprise first utmost point, second utmost point and gate, wherein the gate of this transistor seconds T2 couples second utmost point of this first transistor T1, first utmost point of this transistor seconds T2 couples a second clock pulse signal, and second utmost point of transistor seconds T2 connects an output node, is connected with one first capacitor C 1 between second utmost point of the gate of this transistor seconds T2 and this transistor seconds T2, and the tie point of the gate of this first capacitor C 1 and transistor seconds T2 is a node Q[n]; The 3rd transistor T 3 comprises first utmost point, second utmost point and gate, and wherein first utmost point of the 3rd transistor T 3 couples second utmost point of this transistor seconds T2, and second utmost point of the 3rd transistor T 3 is coupled to an earth point; The 4th transistor T 4, comprise first utmost point, second utmost point and gate, wherein second utmost point of the 4th transistor T 4 couples the gate of the 3rd transistor T 3, first utmost point of the 4th transistor T 4 couples one the 3rd clock pulse signal CK3, and second utmost point of the 4th transistor T 4 is coupled with one second capacitor C 2; The 5th transistor T 5, comprise first utmost point, second utmost point and gate, wherein the gate of the 5th transistor T 5 couples second utmost point of the 4th transistor T 4, first utmost point of the 5th transistor T 5 couples second utmost point of this first transistor T1, and second utmost point of the 5th transistor T 5 couples this earth point Vss; The 6th transistor T 6 comprises first utmost point, second utmost point and gate, and wherein first utmost point of the 6th transistor T 6 couples mutually with the gate of the 6th transistor T 6, the gate of second utmost point coupling the 5th transistor T 5 of the 6th transistor T 6; The 7th transistor T 7, comprise first utmost point, second utmost point and gate, the gate of the 7th transistor T 7 couple one first clock pulse signal CK1, the gate of first utmost point coupling the 5th transistor T 5 of the 7th transistor T 7, second utmost point of the 7th transistor T 7 couples this earth point Vss; The 8th transistor T 8, comprise first utmost point, second utmost point and gate, the gate of the 8th transistor T 8 couple this second clock pulse signal CK2, first utmost point of first this first transistor of utmost point coupling T1 of the 8th transistor T 8, second utmost point of the 8th transistor T 8 couples this earth point Vss.
First utmost point of above-mentioned this first transistor T1 more receives an output signal OUT (n-1) who is sent by previous shift registor; The gate of the 6th transistor T 6 more receives an output signal OUT (n+1) who is sent by a back shift registor; This node Q[n of the tie point of the gate of this first capacitor C 1 and transistor seconds T2], can be by modulation the 5th transistor T 5 and the 6th transistor T 6 sizes to prolong discharge time, make transistor seconds T2 late release, the output node Q[n that connects with second utmost point that helps this transistor seconds T2] earial drainage; When this second clock pulse signal CK2 went to noble potential by electronegative potential, the 3rd transistor T 3 can periodically be opened with the 5th transistor T 5, so that this node Q[n] and this output node OUT (n) earial drainage; When this second clock pulse signal CK2 went to noble potential by electronegative potential, the 3rd transistor T 3 can periodically be opened with the 5th transistor T 5, so that this node Q[n] and this output node OUT (n) earial drainage; The drift voltage that the size of this modulation second electric capacity T2 can be slowed down the 3rd transistor T 3 and the 5th transistor T 5; This shift scratch circuit is arranged on the glass substrate (not shown); Those transistors are amorphous silicon film transistor; And those transistors are nmos pass transistor.
See also shown in Fig. 3 A, the strip point net that please contrasts Fig. 3 B simultaneously is the state that each parameter shows, wherein the first clock pulse CK1 is a noble potential, the second clock pulse CK2, the 3rd clock pulse CK3 are electronegative potential, previous stage output noble potential VH pours into Q point at the corresponding levels and charges to noble potential via the first transistor T1, transistor seconds T2 opened OUT was stabilized in electronegative potential VL this moment, simultaneously the state of the 4th transistor T 4 for opening.The 7th transistor T 7 is an opening with the 3rd transistor T 3 and the 5th transistor T 5 gate end points earial drainages to electronegative potential, and it is closed, and the 6th transistor T 6 and the 8th transistor T 8 also are in closed condition simultaneously.
See also shown in Fig. 4 A, the strip point net that please contrasts Fig. 4 B simultaneously is the state that each parameter shows, wherein the second clock pulse CK2 is a noble potential, the first clock pulse CK1, the 3rd clock pulse CK3 are electronegative potential, the second clock pulse CK2 begins to begin output node is charged to noble potential VH via transistor seconds T2, and the Q point also promotes current potential to increase the current driving ability of transistor seconds T2 because of first capacitor C, 1 capacitance coupling effect simultaneously.The 8th transistor T 8 is opened previous stage is exported earial drainage to current potential VL.Though the gate end points of the 3rd transistor T 3, the 5th transistor T 5 can see through second capacitor C 2 and second clock pulse CK2 coupling (Coupling) promotes a voltage, but because of the 4th transistor T 4 still is the state of opening in this stage, therefore can guarantee that the 3rd transistor T 3 and the 5th transistor T 5 close fully, can not open by mistake and open, the first transistor T1, the 4th transistor T 4, the 6th transistor T 6 and the 7th transistor T 7 also are in closed condition simultaneously.
See also shown in Fig. 5 A, the strip point net that please contrasts Fig. 5 B simultaneously is the state that each parameter shows, wherein the 3rd clock pulse CK3 is a noble potential, the first clock pulse CK1, the second clock pulse CK2 are electronegative potential, and next stage output noble potential VH reaches the gate end points of the 3rd transistor T 3 and the 5th transistor T 5 via the 6th transistor T 6.Because the relation of size design, make that the driving force of the 5th transistor T 5 is lower and cause the delay of Q point earial drainage, so transistor seconds T2 can help the output node earial drainage.The 4th transistor T 4 is also kept opening slowly because of Q point earial drainage, the gate end points of input noble potential VH to the three transistor Ts 3 and the 5th transistor T 5, and the first transistor T1, the 7th transistor T 7 and the 8th transistor T 8 also are in closed condition simultaneously.
See also shown in Fig. 6 A, the strip point net that please contrasts Fig. 6 B simultaneously is the state that each parameter shows, wherein when the 5th transistor T 5 fully with Q point earial drainage to electronegative potential VL, transistor seconds T2 and the 4th transistor T 4 promptly can be closed at once, the first transistor T1, the 7th transistor T 7 and the 8th transistor T 8 also are in closed condition simultaneously, finish the main operation steps of gate drive circuit.This moment, the 3rd transistor T 3 and the 5th transistor T 5 still were the state of opening.
See also shown in Fig. 7 A, the strip point net that please contrasts Fig. 7 B simultaneously is the state that each parameter shows, wherein after output finishes, for making node Q[n] and output signal (OUT (n), OUT (n+1), OUT (n-1)) can stable maintenance at electronegative potential VL, the 3rd transistor T 3 and 5 meetings of the 5th transistor T are via second capacitor C 2 and the periodic unlatching of the second clock pulse CK2 and stable earial drainage path is provided, and prevent from because of the capacitance coupling effect that stray capacitance (gd1, gd3, gs3, gd5, gs5, gs6) causes output to be caused misoperation.The voltage that puts on the 3rd transistor T 3 and the 5th transistor T 5 gate terminal simultaneously can be done change via modulation second capacitor C 2, can reduce its VTH drift by this, prolong the circuit whole service life, the first transistor T1, transistor seconds T2, the 4th transistor T 4, the 6th transistor T 7, the 7th transistor T 7 and the 8th transistor T 8 also are in closed condition simultaneously.
See also shown in Fig. 8 A, the strip point net that please contrasts Fig. 8 B simultaneously is the state that each parameter shows, wherein for prolonging node Q[n] the earial drainage time, the Size design of the 5th transistor T 5 is less.
See also shown in Fig. 9 A, Fig. 9 B, be the waveform influence synoptic diagram of the 5th transistor after fall time, wherein Fig. 9 A shows that the 5th transistorized critical voltage is Δ Vth_T5=0V, and be TFALL=4.9 μ s fall time, but,, Fig. 9 B rises to Δ Vth_T5=10V though showing the 5th transistorized critical voltage along with the 5th transistorized critical drift voltage rises; But be TFALL=4.6 μ s fall time, suffices to show that the present invention has improved the 5th transistorized critical drift voltage.
Disclose by above-mentioned Fig. 1 to Fig. 9 B, can understand the present invention and be a kind of liquid crystal display drive circuit, major technique is characterized as and reduces pull-down (Pull-down) thin film transistor (TFT) area, so that circuit layout, this node of the tie point of the gate of first electric capacity and transistor seconds, can be by modulation the 5th transistor AND gate the 6th transistor size to prolong discharge time, make the transistor seconds late release, this output node earial drainage that connects with second utmost point that helps this transistor seconds; Can reduce the output node noise in addition, when the second clock pulse signal transferred noble potential to by electronegative potential, the 3rd transistor AND gate the 5th transistor can periodically be opened node earial drainage path, with the wave phenomenon that prevents to be produced because of suspension joint; Moreover can slow down the 3rd transistor and the 5th transistorized drift voltage to prolong the bulk life time of driving circuit, in the market of LCD, have high industry applications, so the proposition patented claim is to seek the protection of patent right.
The above only is preferred embodiment of the present invention, can not with the qualification the scope of protection of the invention.In every case the equalization of being done according to the present patent application claim changes and modifies, and all should still belong in the scope that patent of the present invention contains.
Claims (9)
1. liquid crystal display drive circuit comprises:
A plurality of shift registors of serial connection is characterized in that each shift registor more comprises:
The first transistor comprises first utmost point, second utmost point and gate, and wherein first utmost point of this first transistor couples mutually with the gate of this first transistor;
Transistor seconds, comprise first utmost point, second utmost point and gate, wherein the gate of this transistor seconds couples second utmost point of this first transistor, first utmost point of this transistor seconds couples the second clock pulse signal, and second utmost point of this transistor seconds connects output node, be connected with one first electric capacity between second utmost point of the gate of this transistor seconds and this transistor seconds, and the tie point of the gate of this first electric capacity and transistor seconds is a node;
The 3rd transistor comprises first utmost point, second utmost point and gate, and wherein the 3rd transistorized first utmost point couples second utmost point of this transistor seconds, and the 3rd transistorized second utmost point is coupled to earth point;
The 4th transistor, comprise first utmost point, second utmost point and gate, wherein the 4th transistorized second utmost point couples the 3rd transistorized gate, the 4th transistorized first utmost point couples the 3rd clock pulse signal, and the 4th transistorized second utmost point is coupled with one second electric capacity;
The 5th transistor, comprise first utmost point, second utmost point and gate, wherein the 5th transistorized gate couples the 4th transistorized second utmost point, the 5th transistorized first utmost point couples second utmost point of this first transistor, and the 5th transistorized second utmost point couples this earth point;
The 6th transistor comprises first utmost point, second utmost point and gate, and wherein the 6th transistorized first utmost point couples mutually with the 6th transistorized gate, the 6th transistorized second utmost point coupling the 5th transistorized gate;
The 7th transistor comprises first utmost point, second utmost point and gate, and the 7th transistorized gate couples first clock pulse signal, the 7th transistorized first utmost point coupling the 5th transistorized gate, the 7th transistorized second utmost point couples this earth point; And
The 8th transistor comprises first utmost point, second utmost point and gate, and the 8th transistorized gate couples this second clock pulse signal, first utmost point of the 8th transistorized first this first transistor of utmost point coupling, the 8th transistorized second utmost point couples this earth point.
2. liquid crystal display drive circuit as claimed in claim 1 is characterized in that, first utmost point of this first transistor more receives the output signal of being sent by previous shift registor.
3. liquid crystal display drive circuit as claimed in claim 1 is characterized in that, the 6th transistorized gate more receives by a back output signal that shift registor is sent.
4. liquid crystal display drive circuit as claimed in claim 1, it is characterized in that, this node of the tie point of the gate of this first electric capacity and this transistor seconds, can be by modulation the 5th transistor AND gate the 6th transistor size to prolong discharge time, make the transistor seconds late release, this output node earial drainage that connects with second utmost point that helps this transistor seconds.
5. liquid crystal display drive circuit as claimed in claim 1 is characterized in that, when this second clock pulse signal went to noble potential by electronegative potential, the 3rd transistor AND gate the 5th transistor can periodically be opened, so that this node and this output node earial drainage.
6. liquid crystal display drive circuit as claimed in claim 1 is characterized in that, the size of this modulation second electric capacity can be slowed down the 3rd transistor and the 5th transistorized drift voltage.
7. liquid crystal display drive circuit as claimed in claim 1 is characterized in that this shift scratch circuit is arranged on the glass substrate.
8. liquid crystal display drive circuit as claimed in claim 1 is characterized in that, those transistors are amorphous silicon film transistor.
9. liquid crystal display drive circuit as claimed in claim 1 is characterized in that, those transistors are nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110199576 CN102254531B (en) | 2011-07-03 | 2011-07-03 | Liquid crystal display driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110199576 CN102254531B (en) | 2011-07-03 | 2011-07-03 | Liquid crystal display driving circuit |
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| CN102254531A true CN102254531A (en) | 2011-11-23 |
| CN102254531B CN102254531B (en) | 2012-12-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201110199576 Expired - Fee Related CN102254531B (en) | 2011-07-03 | 2011-07-03 | Liquid crystal display driving circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578437A (en) * | 2012-07-31 | 2014-02-12 | 群康科技(深圳)有限公司 | Voltage drop-down circuit structure of grid drive circuit and display device thereof |
| CN103871348A (en) * | 2014-03-26 | 2014-06-18 | 广州新视界光电科技有限公司 | Line integrated circuit |
| TWI466091B (en) * | 2012-02-15 | 2014-12-21 | Innocom Tech Shenzhen Co Ltd | Display panels, pixel driving circuits and pixel driving methods |
| CN106940989A (en) * | 2016-01-04 | 2017-07-11 | 三星显示有限公司 | Display device |
| CN108694921A (en) * | 2017-03-29 | 2018-10-23 | 三星显示有限公司 | Display device |
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| JP2007212559A (en) * | 2006-02-07 | 2007-08-23 | Hitachi Displays Ltd | Display device |
| JP2007249106A (en) * | 2006-03-20 | 2007-09-27 | Mitsubishi Electric Corp | Image display device |
| CN101211665A (en) * | 2006-12-29 | 2008-07-02 | 群康科技(深圳)有限公司 | Shift registers and LCD device |
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2011
- 2011-07-03 CN CN 201110199576 patent/CN102254531B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007212559A (en) * | 2006-02-07 | 2007-08-23 | Hitachi Displays Ltd | Display device |
| JP2007249106A (en) * | 2006-03-20 | 2007-09-27 | Mitsubishi Electric Corp | Image display device |
| CN101211665A (en) * | 2006-12-29 | 2008-07-02 | 群康科技(深圳)有限公司 | Shift registers and LCD device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI466091B (en) * | 2012-02-15 | 2014-12-21 | Innocom Tech Shenzhen Co Ltd | Display panels, pixel driving circuits and pixel driving methods |
| US9269298B2 (en) | 2012-02-15 | 2016-02-23 | Innolux Corporation | Pixel driving circuits, pixel driving methods, display panels and electronic devices |
| CN103578437A (en) * | 2012-07-31 | 2014-02-12 | 群康科技(深圳)有限公司 | Voltage drop-down circuit structure of grid drive circuit and display device thereof |
| CN103871348A (en) * | 2014-03-26 | 2014-06-18 | 广州新视界光电科技有限公司 | Line integrated circuit |
| CN103871348B (en) * | 2014-03-26 | 2016-08-17 | 广州新视界光电科技有限公司 | A kind of line integrated circuit |
| CN106940989A (en) * | 2016-01-04 | 2017-07-11 | 三星显示有限公司 | Display device |
| CN106940989B (en) * | 2016-01-04 | 2021-01-22 | 三星显示有限公司 | Display device |
| CN108694921A (en) * | 2017-03-29 | 2018-10-23 | 三星显示有限公司 | Display device |
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| CN102254531B (en) | 2012-12-12 |
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