CN102253859A - Embedded device system deadlock debugging device and method - Google Patents
Embedded device system deadlock debugging device and method Download PDFInfo
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- CN102253859A CN102253859A CN2010101804134A CN201010180413A CN102253859A CN 102253859 A CN102253859 A CN 102253859A CN 2010101804134 A CN2010101804134 A CN 2010101804134A CN 201010180413 A CN201010180413 A CN 201010180413A CN 102253859 A CN102253859 A CN 102253859A
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Abstract
The invention discloses an embedded device system deadlock debugging device and method. an interrupt program is operated in an interrupt mode of generating key interrupt or chip level high interrupt after system deadlock occurs, an execution state of a system program is visually displayed by using an LCD screen in an interrupt processing program so that a user rapidly and effectively directly searches an obj or map target file when system software is compiled for positioning a fault according to parameter data of a CPU register. The invention has the advantages that firstly, the deadlock state of an embedded system is effectively positioned, debugging efficiency is greatly increased; and secondly, the original operation environment during the deadlock of the system is not changed, and the performance of the normally-operating program can not be influenced.
Description
Technical field
The present invention relates to the embedded device field, relate in particular to a kind of embedded device system deadlock adjustment method.
Background technology
Along with developing rapidly of science and technology, embedded system device has been widely used in fields of society, and as military affairs, consumer electronics, teaching etc., the exploitation of embedded system debugging has become the important content that improves people's living standard.
Embedded system is a kind of computer system of microminiaturization, based on hardware, is that means realize the application function that the user needs with software.Embedded system is because some unknown causes can cause system's generation deadlock.Traditional debugging means for deadlock are: repeatedly debug, and continuous Debugging message result according to last time adds new Debugging message before each debugging, take the means guessed, constantly checking repeatedly and add Debugging message in the place that each suspection goes wrong, the ordinal relation that successively occurs according to these Debugging message situation of coming the software total system has been taken place deadlock positions then.Obviously, the method for this solution embedded system deadlock lacks the technological means of science, and not only debugging efficiency is low, and has destroyed the running environment of system, and more difficult bring for follow-up debugging.
Therefore, need a kind of embedded system deadlock adjustment method badly, can improve debugging efficiency significantly, and the original running environment can the retention system deadlock time, thereby the reason that influences deadlock can be found quickly and accurately.
Summary of the invention
The objective of the invention is to overcome the defective of prior art, propose a kind of embedded device system deadlock adjustment method, this method can improve debugging efficiency, and the original running environment can the retention system deadlock time.
The technical solution used in the present invention provides a kind of embedded device system deadlock debugging apparatus, comprises the system's detection module, interrupt module and the display module that are linked in sequence; Wherein:
Described system detection module is used for detecting in real time the running status of embedded system, and the output interrupt instruction is to interrupt module;
Described interrupt module is used for the instruction interrupt system operation of receiving system detection module, and reads the supplemental characteristic in the embedded system CPU register;
Described display module is used to receive the instruction of interrupt module, to show the supplemental characteristic in the embedded system storer.
In addition, the present invention also provides a kind of embedded device system deadlock adjustment method, may further comprise the steps:
A. system's detection module is described operating system according to the step that deadlock occurs, and operating system is detected in real time, if deadlock occurs, then enters step b, if no deadlock occurs, then continues to carry out this step;
B. interrupt module is carried out interrupt routine, reads the supplemental characteristic in the embedded system CPU register, and enters step c;
C. the supplemental characteristic in the CPU register that interrupt module is read shows on display module;
Obj that produces during d. according to the compiling of the supplemental characteristic in the register and system or map file destination are to fault location recently.
The invention has the beneficial effects as follows: at first the present invention can effectively locate the deadlock state of embedded system, has improved debugging efficiency greatly.Secondly, the original running environment when the present invention does not change system deadlock can not produce performance impact to the program of normal operation.
Description of drawings
Fig. 1 is an embedded device system deadlock debugging apparatus structural representation of the present invention;
Fig. 2 is an embedded device system deadlock adjustment method program flow diagram of the present invention.
Embodiment
Below, contrast accompanying drawing and preferred embodiment are elaborated to technical scheme of the present invention.
With reference to Fig. 1, embedded device system deadlock debugging apparatus comprises: the system's detection module 1 that is linked in sequence, interrupt module 2, display module 3.Wherein, system's detection module 1 is used for detecting in real time the running status of embedded system, and the output interrupt instruction is to interrupt module.Interrupt module 2 is used for the instruction interrupt system operation of receiving system detection module, and reads the supplemental characteristic in the embedded system CPU register.Display module 3 is used to receive the instruction of interrupt module, to show the supplemental characteristic in the embedded system CPU storer.
Described interrupt module 2 is drawn high the interrupt module of interrupt mode for having button interrupt mode or certain chip pin level.Described display module 3 is a LCD display.
Referring to Fig. 2, a kind of embedded device system deadlock adjustment method may further comprise the steps:
A. system's detection module is described operating system according to the step that deadlock occurs, and operating system is detected in real time, if deadlock occurs, then enters step b, if no deadlock occurs, then continues to carry out this step;
B. interrupt module is carried out interrupt routine, reads the supplemental characteristic in the embedded system CPU register, and enters step c;
C. the supplemental characteristic in the CPU register that interrupt module is read shows on display module;
Obj that produces during d. according to the compiling of the supplemental characteristic in the register and system or map file destination are to fault location recently.
The interrupt mode of described interrupt module 2 is that button interrupts or certain chip pin level is drawn high interruption.Described display module 3 is a LCD display.
Described interrupt module can also comprise the interruption of other modes, as the mode that drags down the chip pin level produces interruption etc.Display module can have the display device of Presentation Function for LED display, CRT display screen or other.
When the deadlock commissioning staff uses the present invention that analysis is debugged by the deadlock system, CPU register parameters data according to the LCD demonstration, file destination when directly searching the system software compiling just can navigate to the position that system's operation is blocked, and described file destination is files such as obj or map.
The invention discloses a kind of embedded device system deadlock debugging apparatus and method, the back produces the button interruption or the chip level is drawn high the interrupt mode of interruption, the outage program by taking place at system deadlock.CPU register parameters data in interrupt handling routine during with the system program executing state show intuitively with lcd screen, allow the user fast and effectively according to CPU register parameters data, obj or map file destination when directly searching the system software compiling come fault location.The invention has the beneficial effects as follows: at first, can effectively locate the deadlock state of embedded system, and raising greatly debugging efficiency.Secondly, the original running environment when not changing system deadlock can not produce performance impact to the program of normal operation.
Though abovely content of the present invention is explained in conjunction with embodiment; but be to be understood that; those skilled in the art is under the prerequisite of principle of the present invention and connotation; can make various distortion or modification to embodiments of the present invention, these distortion and modification all should fall into protection scope of the present invention.
Claims (6)
1. an embedded device system deadlock debugging apparatus comprises the system's detection module, interrupt module and the display module that are linked in sequence, it is characterized in that:
Described system detection module is used for detecting in real time the running status of embedded system, and the output interrupt instruction is to interrupt module;
Described interrupt module is used for the instruction interrupt system operation of receiving system detection module, and reads the supplemental characteristic in the embedded system CPU register;
Described display module is used to receive the instruction of interrupt module, to show the supplemental characteristic in the embedded system CPU storer.
2. embedded device system deadlock debugging apparatus as claimed in claim 1 is characterized in that: described interrupt module is to have the interrupt module that button interrupt mode or certain chip pin level are drawn high interrupt mode.
3. embedded device system deadlock debugging apparatus as claimed in claim 1 is characterized in that: described display module is a LCD display.
4. embedded device system deadlock adjustment method is characterized in that may further comprise the steps:
A. system's detection module is described operating system according to the step that deadlock occurs, and operating system is detected in real time, if deadlock occurs, then enters step b, if no deadlock occurs, then continues to carry out this step;
B. interrupt module is carried out interrupt routine, reads the supplemental characteristic in the embedded system CPU register, and enters step c;
C. the supplemental characteristic in the CPU register that interrupt module is read shows on display module;
Obj that produces during d. according to the compiling of the supplemental characteristic in the register and system or map file destination are to fault location recently.
5. embedded device system deadlock adjustment method as claimed in claim 4 is characterized in that: the interrupt mode of described interrupt module is that button interrupts or the certain chip pin level is drawn high interruption.
6. embedded device system deadlock adjustment method as claimed in claim 4 is characterized in that: described display module is a LCD display.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101804134A CN102253859A (en) | 2010-05-21 | 2010-05-21 | Embedded device system deadlock debugging device and method |
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| CN2010101804134A CN102253859A (en) | 2010-05-21 | 2010-05-21 | Embedded device system deadlock debugging device and method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902423A (en) * | 2012-12-26 | 2014-07-02 | 联芯科技有限公司 | Method and system for debugging crash of central processor |
| CN106126211A (en) * | 2016-06-17 | 2016-11-16 | 山东超越数控电子有限公司 | A kind of MCU In-circuit programming system supporting debugging interface |
| CN106339286A (en) * | 2016-08-24 | 2017-01-18 | 广州市芯德电子技术有限公司 | Method for implementing black box debugging of embedded system |
| CN107885650A (en) * | 2016-09-30 | 2018-04-06 | 联芯科技有限公司 | A kind of program debugging method and system |
| CN108062274A (en) * | 2016-11-09 | 2018-05-22 | 厦门雅迅网络股份有限公司 | A kind of adjustment method for starting code for embedded system compilation |
| US10025741B2 (en) | 2016-01-13 | 2018-07-17 | Samsung Electronics Co., Ltd. | System-on-chip, mobile terminal, and method for operating the system-on-chip |
| CN109766273A (en) * | 2018-12-27 | 2019-05-17 | 百富计算机技术（深圳）有限公司 | Localization method, device, computer equipment and the storage medium of endless loop |
| CN112256507A (en) * | 2020-10-22 | 2021-01-22 | 地平线(上海)人工智能技术有限公司 | Chip fault diagnosis method and device, readable storage medium and electronic equipment |
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2010
- 2010-05-21 CN CN2010101804134A patent/CN102253859A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902423A (en) * | 2012-12-26 | 2014-07-02 | 联芯科技有限公司 | Method and system for debugging crash of central processor |
| US10025741B2 (en) | 2016-01-13 | 2018-07-17 | Samsung Electronics Co., Ltd. | System-on-chip, mobile terminal, and method for operating the system-on-chip |
| US10592454B2 (en) | 2016-01-13 | 2020-03-17 | Samsung Electronics Co., Ltd. | System-on-chip, mobile terminal, and method for operating the system-on-chip |
| CN106126211A (en) * | 2016-06-17 | 2016-11-16 | 山东超越数控电子有限公司 | A kind of MCU In-circuit programming system supporting debugging interface |
| CN106339286A (en) * | 2016-08-24 | 2017-01-18 | 广州市芯德电子技术有限公司 | Method for implementing black box debugging of embedded system |
| CN106339286B (en) * | 2016-08-24 | 2019-11-22 | 广州芯德通信科技股份有限公司 | A kind of implementation method of embedded system flight data recorder debugging |
| CN107885650A (en) * | 2016-09-30 | 2018-04-06 | 联芯科技有限公司 | A kind of program debugging method and system |
| CN108062274A (en) * | 2016-11-09 | 2018-05-22 | 厦门雅迅网络股份有限公司 | A kind of adjustment method for starting code for embedded system compilation |
| CN109766273A (en) * | 2018-12-27 | 2019-05-17 | 百富计算机技术（深圳）有限公司 | Localization method, device, computer equipment and the storage medium of endless loop |
| CN112256507A (en) * | 2020-10-22 | 2021-01-22 | 地平线(上海)人工智能技术有限公司 | Chip fault diagnosis method and device, readable storage medium and electronic equipment |
| CN112256507B (en) * | 2020-10-22 | 2023-10-27 | 地平线(上海)人工智能技术有限公司 | Chip fault diagnosis method and device, readable storage medium and electronic equipment |
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Application publication date: 20111123 |