CN102244590B - Status verification method in protocol conformance test - Google Patents

Status verification method in protocol conformance test Download PDF

Info

Publication number
CN102244590B
CN102244590B CN201010167584.3A CN201010167584A CN102244590B CN 102244590 B CN102244590 B CN 102244590B CN 201010167584 A CN201010167584 A CN 201010167584A CN 102244590 B CN102244590 B CN 102244590B
Authority
CN
China
Prior art keywords
state
tested
candidate
checking
list entries
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010167584.3A
Other languages
Chinese (zh)
Other versions
CN102244590A (en
Inventor
杨美红
张新常
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Computer Science Center
Original Assignee
Shandong Computer Science Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong Computer Science Center filed Critical Shandong Computer Science Center
Priority to CN201010167584.3A priority Critical patent/CN102244590B/en
Publication of CN102244590A publication Critical patent/CN102244590A/en
Application granted granted Critical
Publication of CN102244590B publication Critical patent/CN102244590B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention discloses a status verification method in a protocol conformance test. Based on an FSM (finite state machine)/EFSM (extended finite state machine) model, the method comprises the following steps: firstly verifying whether implementation under test (IUT) conforms to a correct input condition; constructing a diagnosis input sequence and a candidate status set which correspond to a status to be verified; and verifying whether the tested status U in the IUT is the status S to be verified or whether the tested status is a certain status in a candidate status set corresponding to the status S to be verified. The status verification method has the advantages of strong verification capability and high efficiency.

Description

A kind of state verification method in testing protocol consistency
Technical field
The present invention relates to a kind of state verification method in testing protocol consistency, belong to the error diagnosis field in cycle tests generation and the testing protocol consistency based on FSM/EFSM model, wherein FSM (Finite State Machine) is finite-state automata, and EFSM (Extended FiniteState Machine) is extended finite state automaton.
Background technology
As pointed in ISO/IEC 9646 (Open System Interconnection--protocol conformance test method and framework), the main target of testing protocol consistency is whether the tested agreement of checking realizes consistent with corresponding protocol specification.Agreement is one group of regulation and behavior constraint that two or more communication entities connect each other and communicate by letter, and it has guaranteed between communication entity that pattern communicates according to the rules.Therefore, testing protocol consistency in occupation of extremely important status, is that agreement realizes indispensable part before actual deployment in network in protocol engineering.
The ISO of International Standards Organization has formulated a set of international standard-ISO/ work EC 9646, for testing protocol consistency provides basic skills and framework, for abstract test suite has been worked out design procedure and describing method, and provides guidance for the realization of test macro.ISO/IEC 9646 has described a general methodology, claims and has realized the product of a certain osi protocol and the consistency of respective protocol standard in order to test one.But ISO/IEC 9646 standards do not relate to formal cycle tests and generate and relevant regulations, do not relate to concrete error diagnosis technology yet.In testing protocol consistency, cycle tests is one group of test activity set with certain ordinal relation, and it has indicated tests required particular content and step.It is the core content of error detector process that cycle tests generates, and has directly determined efficiency and the quality of error detector.Formal cycle tests generates and can improve the wrong covering power of test and certain automatic test ability is provided, and is one of core technology in uniformity test.
In formalization cycle tests generation technique, it is the basic steps that dependence test sequence generates that protocol specification is carried out to formalized description.State automata model is a kind of protocol description method of comparative maturity, and the state automata model being most widely used is at present finite-state automata (FSM) model and extended finite state automaton (EFSM) model.In FSM model, s is used in state transition (or claiming limit) i× x → s j× y represents, its implication is: in system in state s itime, if system is applied to an input x (input can be understood as the excitation to system, can represent different inputs by incoming symbol), the system s that gets the hang of jand output symbol y (output can be understood as the response of system, can represent different output with output symbol).Wherein, state s ibe called head (or initial) state of this state transition, state s jbe called tail (or termination) state of this state transition.In addition,, in above-mentioned mark, also can use t (s i, x) be illustrated in state s ithe state that lower incoming symbol x enters (is s j).In the present invention, the element in state transition except state is called as state transition tag element, and (in illustraton of model) these element compositions are marked at the label on limit, for example: the state tag of FSM model is " incoming symbol/output symbol "; In EFSM model, the label of state transition is " operation of incoming symbol/output symbol/variable ".
At present, the cycle tests generation technique based on FSM/EFSM model has obtained long-term research and development, and is widely used.In the existing method for creating test sequence based on FSM model, relatively typical method comprises UIO (Unique Input/Output) method, W method, Wp method, SC method, DS (Distinguishing Sequence) method, C method and T method etc.The main target of these methods is the cycle testss that generate high wrong coverage rate, to verify whether system under test (SUT) meets corresponding standard.
DS method relates to two stages, i.e. state verification stage and state transition test phase.In the state verification stage, use distinguishing sequence to identify state.Distinguishing sequence is defined as: establish X 0a list entries (being incoming symbol string), if by X 0while being applied to different states, obtain different output sequence (output symbol string), claim X 0for distinguishing sequence.C method is also referred to as characteristic sequence method, and it identifies state by feature set.Feature set is made up of list entries, can be expressed as C={C 1, C 2..., C s, and meet: in the time that the cycle tests in C is applied to any two different conditions in standard FSM, the output sequence obtaining is all not identical.Each element (cycle tests) in C is called as characteristic sequence.In the time that C only comprises an element, the unique characteristic sequence comprising is exactly distinguishing sequence.In UIO method, to suppose and exist an I/O sequence can identify each state, this sequence is called uio sequence.Formally, state s iuio sequence (be designated as UIO i) be the I/O sequence with minimum length that an energy is distinguished this state from other state.W method identifies state by feature set, and feature set is associated with output symbol.Wp method is the improvement to W method, and it utilizes a subset of feature set in W method to go to carry out state verification, therefore the method can reduce the length of cycle tests.In Wp method, different conditions uses different subsets to carry out state verification.
The main target of the method for creating test sequence based on FSM model is whether test system under test (SUT) meets corresponding standard, is a kind of technological means of verifying global consistency.In method for creating test sequence at some based on FSM model (method as described above), relate to the status indicator (or claiming checking) to state automata, but this status indicator is for the described FSM model of protocol specification (being called standard FSM).There is mistake in agreement realizes time, above-mentioned status indicator method cannot be verified to tested state (judging whether tested state is the state of certain appointment in standard FSM), thereby the diagnosis that leads to errors is difficult to effectively carry out.Output symbol mistake (being that certain response that agreement realizes is carried out not according to standard) and transcription error (being that the state that certain state transition of agreement realization enters is not the corresponding states in standard FSM) are two kinds of main causes that cause above-mentioned situation, as shown in Figure of description 1 (a), " a/b, c/d " is state s 1uio sequence, but under the erroneous condition shown in Fig. 1 (b), this sequence is no longer distinguished state s 1, cannot judge whether certain tested state is state s by this sequence 1.In the error diagnosis process based on EFSM model, be there are equally to the problems referred to above in the checking of designated state.
In general, in the testing protocol consistency based on FSM/EFSM model, error diagnosis is a link that research is weaker.At present, in the situation that there is uncertain mistake, the state there is no during agreement is realized carries out the accurately method of checking.
Summary of the invention
Because utilizing the protocol conformance test method based on FSM/EFSM model to find that agreement realization exists after mistake, due to transcription error or/and the quantity of output error and position cannot determine, the problem that is difficult to designated state to judge in error diagnosis process, the invention provides the state verification method in a kind of testing protocol consistency (based on FSM/EFSM model), take designated state during agreement is realized whether as certain state of standard FSM/EFSM model is verified.
The present invention is by the following technical solutions:
This invention is the state verification method in testing protocol consistency, and the method adopts following steps based on FSM/EFSM model and its:
1) checking is prepared: a tested state u and intend the state s of checking in standard FSM/EFSM model corresponding to a given tested realization, this tested realization, this tested realization;
2) if described tested realization meets the correct conditioned disjunction of input for providing diagnostic message to suppose the correct condition establishment of input, standard FSM/EFSM model is stored with the data structure of being scheduled to.Otherwise, method ends;
3) obtain and intend the corresponding diagnosis list entries of proofing state s and candidate state set based on standard FSM/EFSM model, and the diagnosis list entries of acquisition and candidate state set are stored in order to other the tested state in the described tested realization of checking;
4) if step 3) described in number of elements in candidate state set exceed candidate's threshold value, abandon proceeding this method; Otherwise, enter next step;
5) according to step 3) in the corresponding diagnosis list entries of state s of the plan checking found tested state u is tested, observe corresponding test result, obtain state verification conclusion, that is: in tested realization, whether tested state u is the state s that intends checking, or whether this tested state is the some states in the corresponding candidate state set of state s of intending verifying.
In testing protocol consistency process, the main target of error diagnosis is the position that misjudgment occurs, and therefore needs the state during agreement is realized to identify.According to technical solution of the present invention state verification method, can not consider whether mistake of output symbol, be difficult to the effectively problem of identification thereby overcome or alleviated the state causing due to output symbol mistake, improved to a certain extent the stationkeeping ability of error diagnosis.The state verification ability of this method can be analyzed before test, thereby has avoided unnecessary test.In addition, the concrete state verification ability of method is relevant with corresponding standard FSM/EFSM model, is somewhat dependent upon the degree completely (being the ratio of standard incoming symbol quantity with whole incoming symbol quantity of state in model) of model specification incoming symbol definition.Generally, if the degree completely of the standard incoming symbol of certain state is less, the candidate state collection of this state is less, and the state verification ability of the method is stronger.Typically, particularly, in communication protocol, the average definition of standard incoming symbol is spent less, proposed by the invention method completely and is had high condition identification ability.For example, in (the model source: Yujun Zhang and Zhongcheng Li of the model shown in Fig. 2, Hierarchical Protocol Description and Test Genration Method forMobile IPv6 Testing) in, the average definition of standard incoming symbol is spent lower completely.Under worst case, (suppose that all states can turn to free position), only s of this model 6and s 7the corresponding candidate state collection of diagnosis list entries size be 2, the size of other candidate state collection is 1, this example has very strong state verification ability.
Said method, the correct condition of described input is preferably carried out the test of standard incoming symbol for tested realization and is met in the unit testing being associated.
Said method, standard FSM/EFSM model is with matrix structure or link-list structure storage, and if adopt matrix structure storage, must differentiation state transition tag element; If adopt adjacency list structure storage, node elements is corresponding with the element of state transition label.
Said method, the storage element type of matrix structure is character string forms, the state transition tag element of being distinguished comprises that any incoming symbol, output meet and variable assignments operation, and adopts escape symbolic notation to be distinguished state transition tag element; This escape symbolic notation adopts “ " represent list separator, if tag element comprises “ " symbol, and use “ " symbolic substitution; In the time that above-mentioned method for expressing is carried out to semantic interpretation, single appearance " " symbol is separator, continuous two of occurring of order " " symbol for symbol " " symbolic substitution is returned.
Said method, described step 3) in first obtain the list entries carried out based on standard FSM/EFSM model that originates in the corresponding state s that intends checking, and then choose the list entries carried out that other state maximum possible in corresponding state and model can be made a distinction as diagnosing list entries; And the set of getting the undistinguishable state composition of diagnosis list entries is as the corresponding candidate state set of state s of intending checking.
Preferably, described candidate's threshold value is made as less value, as 2 or 3.
Preferably, in the time intending the size of the corresponding candidate state set of state s of checking and be 1, can be without interruptedly carrying out on tested state u if the corresponding diagnosis list entries of state s of intending verifying is applied to, tested state u is the state s that intends checking, otherwise tested state u is not the state s that intends checking; In the time that the size of the candidate state set of state s is greater than 1, can be without interruptedly carrying out on tested state u if the corresponding diagnosis list entries of state s of intending verifying is applied to, tested state u is a state in the corresponding candidate state set of state s of intending verifying, otherwise tested state u is not in the candidate state set of state s of intending checking.
Accompanying drawing explanation
Below in conjunction with Figure of description, technical scheme of the present invention is further elaborated, wherein:
Fig. 1 is FSM error instance figure, and wherein figure (a) is standard FSM model, and figure (b) is that wrong FSM realizes.
Fig. 2 is MIPv6 mobile node state transition graph.
Fig. 3 is the state verification method flow diagram in the testing protocol consistency based on technical solution of the present invention, and wherein figure (a) is condition express method block diagram, and figure (b) is state representation entity relationship.
Fig. 4 is the adjacency list storage node composition of FSM/EFSM, wherein figure (a) is state automata model adjacency list overall construction drawing, figure (b) is FSM model adjacency list node structure figure, and figure (c) is EFSM model adjacency list node structure figure.
Fig. 5 is state s iinput forwarding tree structure schematic diagram.
Embodiment
The present invention relates to some new concepts, comprise diagnosis list entries, the candidate state set of state and input correct condition, first these concepts are described below.
If an incoming symbol has clear and definite definition (being that state s can accept this incoming symbol) to certain state s in given standard, claim that this symbol is the standard incoming symbol of state s.When input an incoming symbol under certain state s time, may there is following situation in output: 1. the normal symbol of output; 2. without any output, but this situation should have normal output in standard FSM/EFSM model; 3. report output error.The output of above-mentioned latter two situation is referred to as improper output.
If input the non-standard incoming symbol of this state under designated state, claim to produce an output and interrupt.Claim described output while interrupting generation, to be output as interrupt output.If a list entries α does not exist output disruption while being applied in state s (referring to start to input successively the incoming symbol α from state s), this sequence is called as the list entries carried out that originates in state s.Attention: can carry out list entries for standard FSM/EFSM model definition.If originating in the list entries carried out of state s is not executable to other state t, claim that state s and t are differentiable.
Formally, under certain state s, input certain standard incoming symbol (while being designated as a), the state set that may enter be designated as C (s, a).The further created symbol C ' of the present invention (S, i).Formally, establish S set={ e 1, e 2..., e t, C ' (S, i)=C (e 1, i) ∪ ∪ C (e 2, i) ∪ ... ∪ C (e t, i).If " i 0, i 1..., i k" represent a list entries, when this sequence is applied in to state s 0when upper, the sequence that gets the hang of is " s 1, s 2..., s k", meet:
(1)s 1∈C(s,i 0);
(2)s m∈C′(C′(C′...(C′(C(s,i 0),i 1)...),i m-2),i m-1),1<m≤k。
If certain can be carried out list entries and state s can be separated with other state area to greatest extent, claim this can carry out list entries for diagnosis list entries, claim that the set of undistinguishable other state and this state composition is (or s) the corresponding candidate state set of state of this diagnosis list entries.For simplifying conveniently, this programme is called diagnosis list entries DI (Distinguishing Input) sequence sometimes.
In the existing method for creating test sequence based on FSM/EFSM model, most methods reasonably suppose that the corresponding states in realization can accept all standard incoming symbols.The present invention further reasonably supposes the corresponding states energy in realizing and only can accept all standard incoming symbols, and claims this to be assumed to the correct supposition of input.Accordingly, inputting correct condition refers to the corresponding states energy of standard FSM/EFSM model in realization and only can accept all standard incoming symbols.Inputting correct condition can be met by input being carried out to simple dependence test in the relevant unit testing of state.In common test practice, this test tends to carry out or part is carried out, and this programme only explicitly calls for it, its concrete operations is not described in detail.
With reference to the state verification method in the testing protocol consistency shown in Figure of description 3, the method adopts following steps based on FSM/EFSM model and its:
1) checking is prepared: a given tested realization, standard FSM/EFSM corresponding to this tested realization
Tested state u and intend the state s of checking in model, this tested realization;
2) if described tested realization meets the correct conditioned disjunction of input for providing diagnostic message to suppose the correct condition establishment of input, standard FSM/EFSM model is stored with the data structure of being scheduled to.Otherwise, method ends;
3) obtain and intend the corresponding diagnosis list entries of proofing state s and candidate state set based on standard FSM/EFSM model, and the diagnosis list entries of acquisition and candidate state set are stored in order to other the tested state in the described tested realization of checking;
4) if step 3) described in number of elements in candidate state set exceed candidate's threshold value, abandon proceeding this method; Otherwise, enter next step;
5) according to step 3) in the corresponding diagnosis list entries of state s of the plan checking found tested state u is tested, observe corresponding test result, obtain state verification conclusion, that is: in tested realization, whether tested state u is the state s that intends checking, or whether this tested state is the some states in the corresponding candidate state set of state s of intending verifying.
In Figure of description 3, provide the adjacency list storage node composition of FSM/EFSM model.In Fig. 3, suppose that state automata model has k state, be wherein s 0initial state, has the individual state transition of n (i) with state s i(0≤i≤k) is start node, symbol s i, lrepresent from state s ithe shape of tail state of l the state transition of setting out.
As described above, inputting correct condition can meet by following simple restriction: in the unit testing being associated, carry out the test of standard incoming symbol for tested realization, and testing out the input correction work of being correlated with when correct condition that do not meet, software (or system) is not met to the correct condition part of input and correct or perfect, make it meet the correct condition of input.If defer to above-mentioned restriction in dependence test, tested realization meets the correct condition of input.If being provided, a kind of false judgment supposes that the correct condition of input meets, and also carries out follow-up condition diagnosing process.Those skilled in the art can select according to actual needs.
Standard FSM/EFSM is with matrix structure or link-list structure storage, and if adopt matrix structure storage, must differentiation state transition tag element; If adopt adjacency list structure storage, node elements is corresponding with the element of state transition label.
Preferably, if adopting matrix structure stores, element type is character string forms, the state transition tag element of being distinguished at least comprises that any incoming symbol, output meet and variable assignments operation, and adopts escape symbolic notation state transition tag element to be distinguished to meet the needs of data retrieval; This escape symbolic notation adopts “ " represent list separator, if tag element comprises “ " symbol, and use “ " symbolic substitution; In the time that above-mentioned representation is carried out to semantic interpretation, single appearance " " symbol is separator, continuous two of occurring of order " " symbol with one " " symbolic substitution returns.
For meeting the requirement of method, first the obtaining of described diagnosis list entries comprises obtains the list entries carried out based on standard FSM/EFSM model that originates in corresponding states s, and then chooses the list entries carried out that other state maximum possible in corresponding state and model can be made a distinction as diagnosis list entries; And the set of getting the undistinguishable state composition of diagnosis list entries is the corresponding candidate state set of s.
Further, a kind of preferred mode, in order to obtain diagnosing list entries, introduces input and comprises collection and two concepts of input transition tree, is introduced respectively below.All standard incoming symbols set of this state of standard incoming symbol set expression of designated state.In given state automaton model, the standard incoming symbol set of different conditions may be different, also may be identical.If the standard incoming symbol set of two states is identical, claim that these two states are that input is of equal value.Further, (input being made as s) comprises collection to introducing state, is designated as S i +(s), meet:
Figure GSA00000116442900081
wherein, I (s) represents the standard incoming symbol set of state s, comprises the set of all standard incoming symbols of state s.
In order to explain and build the DI sequence of state, this programme is introduced a kind of special tree structure---input transition tree.Each transition tree is corresponding with definite state institute, has described the state that a certain state transition under the correct supposition of input may enter.In transition tree, each node (being made as N) is all positioned at certain level (being designated as lev (N)), is defined as follows:
Figure GSA00000116442900082
Wherein, p (N) represents the father node of node N.In transition tree, node (except root node) represents a state, and uses this status indication, claims that the state of mark is node state.Therefore, the flag state of the different nodes in forwarding tree may be identical.In input transition tree, the node that node state is identical can be distinguished by tree hierachy.
For state s, its input transition tree organization definition is as follows:
(1) root vertex is a dummy node;
(2) child of root vertex is that status indication is S i +(s) node of each state in (comprise the node itself that is labeled as state s, and claim that this node is identification nodes);
(3) establish the state of certain downstream node institute mark that x is identification nodes in i layer, a is any standard incoming symbol of this state, for C (x, a) the each state in (is made as e), a newly-built node that status indication is e, and with symbol a to corresponding tree limit mark in addition.
In above-mentioned definition, S i +(s) in set, be called mark reference node except the node being labeled as s.In addition, the subtree that in transition tree, identification nodes is root is called mark subtree.Fig. 5 has provided the structural representation of input transition tree.In the figure, s i, jrepresent S i +(s i) in set except s ij outer state, I i, jexpression state s ij standard incoming symbol, c (i) represents from state s istandard incoming symbol quantity.Fig. 5 has only provided the structure of three levels, and further structure can be expanded by said method.The structure of forwarding tree is referring to the algorithm 1 shown between two dotted lines below.
Next the method for being derived DI sequence by input transition tree is described.Be similar to uio sequence, (the s of T for the present invention i, α) and represent a list entries, this sequence can be by automaton from state t (s i, α) and take state s to i(mark t (s i, α) represent state s iapply the state arriving after list entries).If the state s being built by algorithm 1 ithe total x bar of mark subtree in corresponding forwarding tree is from s ito the path of leaf node, on each paths, the cascade of incoming symbol is designated as respectively β 1, β 2..., β x.Diagnose list entries to be:
β 1T(s i,β 12T(s i,β 2)…β iT(s i,β i)…β x-1T(s i,β x-1x
Algorithm 1: build diagnosis list entries and candidate state collection
1:procedure FINDDI (M, s ithe M of) //is standard FSM/EFSM; s ifor the state of specifying.
2: create root vertex r;
Figure GSA00000116442900091
establishment is labeled as s unew node, this joint
Point is the child node of root; C candidate← S + iO(s i); Lev ← 1 //C candidatefor waiting
Select state set
3: if C candidateonly comprise s i, conti ← false; Otherwise, conti ← true;
4:while conti is true, and lev layer exists the not node do with invalid flag
The not node with the invalid flag institute mark of each in 5:for mark subtree in lev layer
State s do
6:for C (s, i 1) C (s, i 2) ∪ ... ∪ C (s, i k) in each state e do//i 1,
I 2..., i kfor the standard incoming symbol of s
7: create the child of a s, its flag state is e, and limit mark enters shape
The corresponding incoming symbol of state e (is designated as i);
The reference node of any reference node c do//s that 8:for s is corresponding refers to nonstandard
Know certain node in subtree, the incoming symbol sequence the path from root to this node with from
Root is identical to the incoming symbol sequence on the path of s.
9:if C (c, i) is not empty then
10: newly-built | C (c, i) | individual node, the state in mark C (c, i) respectively,
Limit is labeled as i;
11: else
12: by mark reference node corresponding c from C candidatemiddle deletion;
13: endif
14: endfor
On the path of 15:if from tree root to e, there is the node then that is designated e
16: add invalid flag to this node that is designated e;
17: endif
18: endfor
19: endfor
20: if|C candidate|=1 then
21: conti←false;
22: endif
23:end while
24: generate diagnosis list entries according to the mark subtree generating
Be a default integer about the corresponding threshold value of described candidate state set, candidate state set scale is larger, and the accuracy rate of checking is lower, and therefore, described candidate's threshold value is made as 2 or 3, to improve the accuracy of checking.
In the time intending the size of the corresponding candidate state set of state s of checking and be 1, can be without interruptedly carrying out on tested state u if the corresponding diagnosis list entries of state s of intending verifying is applied to, tested state u is the state s that intends checking, otherwise tested state u is not the state s that intends checking; In the time that the size of the candidate state set of state s is greater than 1, can be without interruptedly carrying out on tested state u if the corresponding diagnosis list entries of state s of intending verifying is applied to, tested state u is a state in the corresponding candidate state set of state s of intending verifying, otherwise tested state u is not in the corresponding candidate state set of state s of plan checking.

Claims (6)

1. the state verification method in testing protocol consistency, the method is based on FSM/EFSM model and adopt following steps:
1) checking is prepared: a tested state u in corresponding standard FSM/EFSM model, this tested realization of a given tested realization, this tested realization and intend the state s of checking;
2) if described tested realization meets the correct conditioned disjunction of input for providing diagnostic message to suppose the correct condition establishment of input, standard FSM/EFSM model is stored with the data structure of being scheduled to; Otherwise, method ends;
3) obtain and intend the corresponding diagnosis list entries of proofing state s and candidate state set based on standard FSM/EFSM model, and the diagnosis list entries of acquisition and candidate state set are stored in order to other the tested state in the described tested realization of checking;
4) if the number of elements in the set of candidate state described in step 3) exceedes candidate's threshold value, abandon proceeding this method; Otherwise, enter next step;
5) according to the corresponding diagnosis list entries of state s of the plan checking of finding in step 3), tested state u is tested, observe corresponding test result, in the time intending the size of the corresponding candidate state set of state s of checking and be 1, can be without interruptedly carrying out on tested state u if the corresponding diagnosis list entries of state s of intending verifying is applied to, tested state u is the state s that intends checking, otherwise tested state u is not the state s that intends checking; In the time that the size of the candidate state set of state s is greater than 1, can be without interruptedly carrying out on tested state u if the corresponding diagnosis list entries of state s of intending verifying is applied to, tested state u is a state in the corresponding candidate state set of state s of intending verifying, otherwise tested state u is not in the corresponding candidate state set of state s of plan checking;
Wherein, in described step 3), first obtain and originate in the corresponding corresponding list entries carried out based on standard FSM/EFSM model of state s of intending checking, and then choose the list entries carried out that other state maximum possible in corresponding state and model can be made a distinction as diagnosis list entries; And the set of getting the undistinguishable state composition of diagnosis list entries is as the corresponding candidate state set of state s of intending checking.
2. method according to claim 1, is characterized in that: the correct condition of described input is met by the state of tested realization being carried out to incoming symbol test in the unit testing being associated.
3. method according to claim 1, is characterized in that: standard FSM/EFSM model is with matrix structure or link-list structure storage, and if adopt matrix structure storage, must the each state transition tag element of differentiation; If adopt adjacency list structure storage, node elements is corresponding with the element of state transition label.
4. method according to claim 3, it is characterized in that: the storage element type of matrix structure is character string forms, the state transition tag element of being distinguished comprises that incoming symbol, output meet and variable assignments operation, and adopts escape symbolic notation to be distinguished state transition tag element; This escape symbolic notation adopts “ " represent list separator, if tag element comprises “ " symbol, and use “ " symbolic substitution; In the time that above-mentioned method for expressing is carried out to semantic interpretation, single appearance " " symbol is separator, continuous two of occurring of order " " symbol with one " " symbolic substitution returns.
5. method according to claim 1, is characterized in that: diagnosis list entries is by obtaining the traversal in false transitions space.
6. method according to claim 1, is characterized in that: described candidate's threshold value is made as 2 or 3.
CN201010167584.3A 2010-05-10 2010-05-10 Status verification method in protocol conformance test Active CN102244590B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201010167584.3A CN102244590B (en) 2010-05-10 2010-05-10 Status verification method in protocol conformance test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010167584.3A CN102244590B (en) 2010-05-10 2010-05-10 Status verification method in protocol conformance test

Publications (2)

Publication Number Publication Date
CN102244590A CN102244590A (en) 2011-11-16
CN102244590B true CN102244590B (en) 2014-05-14

Family

ID=44962445

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010167584.3A Active CN102244590B (en) 2010-05-10 2010-05-10 Status verification method in protocol conformance test

Country Status (1)

Country Link
CN (1) CN102244590B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111240883B (en) * 2020-01-16 2023-08-29 北京工业大学 System diagnosis method, device, equipment and storage medium based on finite state machine

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1484783A (en) * 2000-09-26 2004-03-24 皇家菲利浦电子有限公司 Security monitor of system runs software simulator in parallel
CN1749769A (en) * 2004-05-21 2006-03-22 富士通株式会社 Invariant detects

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1484783A (en) * 2000-09-26 2004-03-24 皇家菲利浦电子有限公司 Security monitor of system runs software simulator in parallel
CN1749769A (en) * 2004-05-21 2006-03-22 富士通株式会社 Invariant detects

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
倪群等.用于协议一致性测试序列生成的状态规范化算法.《通信学报》.1997,第18卷(第2期),全文.
基于FSM的协议一致性测试序列生成算法研究;陈涛等;《计算机工程与应用》;20100228;全文 *
用于协议一致性测试序列生成的状态规范化算法;倪群等;《通信学报》;19970228;第18卷(第2期);全文 *
陈涛等.基于FSM的协议一致性测试序列生成算法研究.《计算机工程与应用》.2010,全文.

Also Published As

Publication number Publication date
CN102244590A (en) 2011-11-16

Similar Documents

Publication Publication Date Title
CN109491905A (en) Head end test method, apparatus and electronic equipment
JPWO2010067472A1 (en) Test apparatus and test method
CN109714221B (en) Method, device and system for determining network data packet
CN113572726B (en) Multimode network control-data plane consistency verification method and device
US20200401504A1 (en) Methods, systems, and computer readable media for configuring a test system using source code of a device being tested
CN110958157A (en) Network testing method, system, storage medium and electronic equipment
US20210318947A1 (en) Methods and apparatuses for generating smart contract test case
Yao et al. Formal modeling and systematic black-box testing of sdn data plane
CN109391526A (en) A kind of detection method and device of network loop
CN107294814A (en) The method of testing and device of a kind of network-on-chip
CN102244590B (en) Status verification method in protocol conformance test
CN111526094B (en) RSTP state machine scheduling method and system
US11665165B2 (en) Whitelist generator, whitelist evaluator, whitelist generator/evaluator, whitelist generation method, whitelist evaluation method, and whitelist generation/evaluation method
US9367821B2 (en) System and method for profiling requests in service systems
CN103457957B (en) A kind of network penetration test macro and method with adaptation function
CN115934513A (en) Demand analysis and test design adaptation method, device, equipment and medium
CN102843269B (en) A kind of method and system for simulating microcode business processing flow
CN115576831A (en) Test case recommendation method, device, equipment and storage medium
CN113645052B (en) Firmware debugging method and related equipment
CN106470083A (en) A kind of synchronizing network detection method and device
CN109684212A (en) A kind of visual logic test method, device, equipment and readable storage medium storing program for executing
Podlovchenko et al. Equivalence problem solvability in gateway program models
US11743066B2 (en) Reachability verification method and apparatus
CN110225025A (en) A kind of acquisition methods and device of abnormal network data behavior model
CN110377463A (en) Interface test method, device, terminal and computer readable storage medium

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant