CN102244381A - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
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- CN102244381A CN102244381A CN2011101921486A CN201110192148A CN102244381A CN 102244381 A CN102244381 A CN 102244381A CN 2011101921486 A CN2011101921486 A CN 2011101921486A CN 201110192148 A CN201110192148 A CN 201110192148A CN 102244381 A CN102244381 A CN 102244381A
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Abstract
The invention provides an electrostatic discharge protection circuit, which is applied to an LCD (liquid crystal display), wherein the LCD is provided with a signal line and a shared wire. The electrostatic discharge protection circuit comprises a first diode, a first field-effect transistor, a second diode, a third diode, a second field-effect transistor and a fourth diode, wherein a positive pole of the first diode is coupled with the signal line; the first field-effect transistor is provided with a first electrode, a second electrode and a first control electrode, the first electrode is coupled with a negative pole of the first diode, and the first control electrode is coupled with the signal line; a positive pole of the second diode is coupled with the second electrode and a negative electrode of the second diode is coupled with the shared wire; a negative electrode of the third diode is coupled with the signal line and a positive electrode of the third diode is coupled with the second electrode; the second field-effect transistor is provided with a third electrode, a fourth electrode and a second control electrode, the third electrode is coupled with the negative pole of the first diode, the fourth electrode is coupled with a positive pole of the third diode, and the second control electrode is coupled with the shared wire; and a negative pole of the fourth diode is coupled with the negative pole of the first diode and a positive pole of the fourth diode is coupled with the shared wire.
Description
Technical field
The invention relates to a kind of ESD protection circuit, and particularly relevant for a kind of ESD protection circuit that is used for LCD.
Background technology
Social now multimedia technology is quite flourishing, is indebted to the progress of semiconductor element or display unit mostly.With regard to display, have that high image quality, space utilization efficient are good, the LCD of low consumpting power, advantageous characteristic such as radiationless becomes the main flow in market gradually.General in the manufacture process of LCD, operating personnel, board or detecting instrument all may have static, and above-mentioned electrified body (operating personnel, board or detecting instrument) might cause element and circuit in the display panels destroyed by static discharge when touching display panels.
(Electrostatic Discharge is a kind of buildup of static electricity ESD) to the static discharge of knowing, a kind of phenomenon that electrostatic charge shifts between different objects.Time when static discharge takes place is very short; second (nano-second) grade for how, and in the so short time, can produce very high electric current, usually can be high to several amperes (amper); the high like this electric current semiconductor integrated circuit of in a single day flowing through can make its damage usually.
Therefore in semiconductor circuit, the ESD protection circuit between power line must provide the path that can discharge when producing high-pressure electrostatic, semiconductor integrated circuit can not damaged.And traditional LCD is between every scan line (gate line) and shared distribution (common line) and every data wire (data line) has an ESD protection circuit with shared wiring closet, can not damaged by high-pressure electrostatic with the transistor of protecting each pixel.Please refer to Fig. 1, it has illustrated the existing circuit diagram that is used for the ESD protection circuit of LCD.ESD protection circuit 100 is coupled to scan line (gate line) and shared wiring closet, and it is made up of 6 back to back diodes (diode), is respectively D (1)～D (6).And be in series by back to back diode D (1)～D (3) and form article one discharge path R1 and back to back diode D (4)～D (6) and be in series and form second discharge path R2.When scan line produces static, just can electrostatic induced current be discharged on the shared distribution by discharge path R2, perhaps when shared distribution produced static, R1 was discharged to electrostatic induced current on the scan line by discharge path.
But in the design of this kind ESD protection circuit 100; a plurality of back to back diodes of promptly connecting; the area shared owing to the passage (channel width) of back to back diode D (1)～D (6) is too big, and the area of the circuit layout (layout) of its whole ESD protection circuit 100 is increased.So, just can increase the area of display panels, and then be not easy to dwindle the size of LCD.
Summary of the invention
In order to solve the problems of the technologies described above, an aspect of of the present present invention has proposed a kind of ESD protection circuit, is used for a LCD, and LCD has a signal line and a shared distribution, ESD protection circuit comprises: one first diode, and its positive pole is coupled to signal line; One first field effect transistor has one first electrode, one second electrode and one first control electrode, and first electrode is coupled to the negative pole of first diode, and first control electrode is coupled to signal line; One second diode, its positive pole is coupled to second electrode, and negative pole is coupled to shared distribution; One the 3rd diode, its negative pole is coupled to signal line, and its positive pole is coupled to second electrode; One second field effect transistor has a third electrode, one the 4th electrode and one second control electrode, and third electrode is coupled to the negative pole of first diode, and the 4th electrode is coupled to the positive pole of the 3rd diode, and second control electrode is coupled to shared distribution; And one the 4th diode, its negative pole is coupled to the negative pole of first diode, and its positive pole is coupled to shared distribution; Wherein, when one first electrostatic charge results from the signal line, the pairing voltage of first electrostatic charge makes first diode, first field effect transistor and second diode current flow, makes the electrostatic charge of winning see through first diode, first field effect transistor and second diode discharge to shared distribution; When one second electrostatic charge results from the shared distribution, the pairing voltage of second electrostatic charge makes the 3rd diode, second field effect transistor and the 4th diode current flow, makes second electrostatic charge see through the 3rd diode, second field effect transistor and the 4th diode discharge to signal line.
Another aspect of the present invention has proposed a kind of ESD protection circuit again, be used for a LCD, LCD has a signal line and a shared distribution, it is characterized in that, ESD protection circuit comprises: one first diode, and its positive pole is coupled to signal line; One first field effect transistor has one first electrode, one second electrode and one first control electrode, and first electrode and first control electrode are coupled to the negative pole of first diode; One second diode, its positive pole is coupled to second electrode, and negative pole is coupled to shared distribution; One the 3rd diode, its negative pole is coupled to signal line, and its positive pole is coupled to second electrode; One second field effect transistor has a third electrode, one the 4th electrode and one second control electrode, and the third electrode and second control electrode are coupled to the negative pole of first diode, and the 4th electrode is coupled to the positive pole of the 3rd diode; And one the 4th diode, its negative pole is coupled to the negative pole of first diode, and its positive pole is coupled to shared distribution; Wherein, when one first electrostatic charge results from the signal line, the pairing voltage of first electrostatic charge makes first diode, first field effect transistor and second diode current flow, makes the electrostatic charge of winning see through first diode, first field effect transistor and second diode discharge to shared distribution; When one second electrostatic charge results from the shared distribution, the pairing voltage of second electrostatic charge makes the 3rd diode, second field effect transistor and the 4th diode current flow, makes second electrostatic charge see through the 3rd diode, second field effect transistor and the 4th diode discharge to signal line.
Preferably, above-mentioned first field effect transistor/second field effect transistor is a N channel field-effect pipe.
Preferably, above-mentioned N channel field-effect pipe is N channel metal-oxide-semiconductor field.
Preferably, above-mentioned first field effect transistor/second field effect transistor is the P-channel field-effect transistor (PEFT) pipe.
Preferably, above-mentioned P-channel field-effect transistor (PEFT) pipe is P channel metal-oxide-semiconductor field.
Preferably, above-mentioned signal line is a scan line.
Preferably, above-mentioned signal line is a data wire.
Preferably, above-mentioned first field effect transistor and above-mentioned second field effect transistor are same structure.
Preferably, above-mentioned first diode, above-mentioned second diode, above-mentioned the 3rd diode and above-mentioned the 4th diode are same structure.
As from the foregoing; ESD protection circuit proposed by the invention; its discharge capability can be suitable with the discharge capability of existing ESD protection circuit; but because do not adopt the framework of a plurality of diodes of series connection in its circuit; to the area of the circuit layout of whole ESD protection circuit be reduced, thereby reduced the area of display panels.
Description of drawings
Fig. 1 has illustrated the existing circuit diagram that is used for the ESD protection circuit of LCD;
Fig. 2 has illustrated the circuit diagram of the ESD protection circuit of one embodiment of the present invention;
Fig. 3 has illustrated the circuit diagram of the ESD protection circuit of another execution mode of the present invention.
Embodiment
Below will and describe clear explaination embodiments of the present invention in detail with accompanying drawing, for the purpose of simplifying accompanying drawing, some known habitual structures and assembly will illustrate in the mode of simple signal in the accompanying drawings.
With reference to Fig. 2, Fig. 2 has illustrated the circuit diagram of the ESD protection circuit of one embodiment of the present invention.In the present embodiment; ESD protection circuit 200; be used for LCD; particularly; be used for Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD), LCD has a signal line and a shared distribution; this signal line can be a scan line, also can be data wire.
As shown in Figure 2, ESD protection circuit 200 comprises: one first diode D1, one first field effect transistor Q1, one second diode D2, one the 3rd diode D3, one second field effect transistor Q2 and one the 4th diode D4.
As shown in Figure 2, the positive pole of the first diode D1 is coupled to signal line; The first field effect transistor Q1, has one first electrode, one second electrode and one first control electrode, first electrode is coupled to the negative pole of the first diode D1, first control electrode is coupled to signal line, in the present embodiment, the first field effect transistor Q1 is a N channel field-effect pipe, preferably, be N channel metal-oxide-semiconductor field, and in the present embodiment, first electrode is a source electrode, second electrode is that the drain electrode and first control electrode are grid, but it should be noted that, first electrode also can be set to drain electrode, second electrode is set to source electrode, not as limit, also it should be noted that, in some other embodiment, the first field effect transistor Q1 can be the P-channel field-effect transistor (PEFT) pipe, preferably, is P channel metal-oxide-semiconductor field; The second diode D2, its positive pole is coupled to second electrode, and negative pole is coupled to shared distribution; The 3rd diode D3, its negative pole is coupled to signal line, and its positive pole is coupled to second electrode of the first field effect transistor Q1; The second field effect transistor Q2, itself and the first field effect transistor Q1 have analog structure, promptly, has a third electrode, one the 4th electrode and one second control electrode, third electrode is coupled to the negative pole of the first diode D1, the 4th electrode is coupled to the positive pole of the 3rd diode D3, second control electrode is coupled to shared distribution, in the present embodiment, the second field effect transistor Q2 is a N channel field-effect pipe, preferably, be N channel metal-oxide-semiconductor field, and in the present embodiment, third electrode is a source electrode, the 4th electrode is that the drain electrode and second control electrode are grid, but it should be noted that, first electrode also can be set to drain electrode, second electrode is set to source electrode, not as limit, also it should be noted that, when in some other embodiment, when the first field effect transistor Q1 is the P-channel field-effect transistor (PEFT) pipe, this second field effect transistor Q2 also can be the P-channel field-effect transistor (PEFT) pipe, preferably, is P channel metal-oxide-semiconductor field; The 4th diode D2, its negative pole is coupled to the negative pole of the first diode D1, and its positive pole is coupled to shared distribution.
In the present embodiment, when producing one first electrostatic charge q1 on the signal line, the pairing voltage of this electrostatic charge q1 is V1, and, when voltage V1 makes the first diode D1, the first field effect transistor Q1 and the second diode D2 conducting, so this moment, the first electrostatic charge q1 sees through the first diode D1, the first field effect transistor Q1 and the second diode D2 is discharged to shared distribution; In addition, when producing one second electrostatic charge q2 on the shared distribution, the pairing voltage of this electrostatic charge q2 is V2, and, when voltage V2 makes the 3rd diode D3, the second field effect transistor Q2 and the 4th diode D4 conducting, so this moment, the second electrostatic charge q2 will be discharged to signal line through the 3rd diode D3, the second field effect transistor Q2 and the 4th diode D4.
Concrete parameter below in conjunction with each element describes scheme proposed by the invention and superiority thereof.In the present embodiment, the first field effect transistor Q1 and the second field effect transistor Q2 are N channel metal-oxide-semiconductor field.Producing the pairing voltage V1 of the first electrostatic charge q1 on the signal line is 15V, if do not produce electrostatic charge on the shared distribution this moment, be V2=0, the pressure drop when diode D1, D2, D3 and D4 conducting is 5V, and V1 is less than the puncture voltage of diode, because signal line couples mutually with the first diode D1 positive pole, and couple mutually with the negative pole of the 3rd diode D3, and diode has the characteristic of oppositely ending, therefore, V1 will make the first diode D1 conducting, and the 3rd diode still is a cut-off state.When the first diode D1 conducting, V1 becomes 10V through behind the D1 so, promptly first electrode voltage of the first field effect transistor Q1 is 10V, and first control electrode of the first field effect transistor Q1 is 15V, then form positive bias for the first field effect transistor Q1 this moment, because in the present embodiment, the first field effect transistor Q1 is N channel metal-oxide-semiconductor field, and according to its characteristic, this moment, the first field effect transistor Q1 was with conducting, V1 will produce pressure drop on the first field effect transistor Q1 after producing pressure drop on the first diode D1 so, this pressure drop can be variable, such as, be 4V, but not as limit, V1 becomes 6V through behind the Q1 so.After the first field effect transistor Q1 conducting, its second electrode place voltage is 6V, will make the second diode D2 conducting so.And for the second field effect transistor Q2,, therefore do not form positive bias, the therefore second not conducting of field effect transistor for the second field effect transistor Q2 because of second voltage of controlling the utmost point is that 0V, third electrode are that 10V and the 4th electrode are 6V.For the 4th diode D4, because of the negative pole of its negative pole with the first diode D1 couples mutually, according to its characteristic, the 4th not conducting of diode D4.As from the foregoing, when the signal line place forms certain electrostatic charge q1, at this moment, the first diode D1, the first field effect transistor Q1 and the second diode D2 conducting, that is, the electrostatic charge that produces of signal line place can see through the first diode D1, the first field effect transistor Q1 and the second diode D2 is discharged to shared distribution.In the present embodiment, only produce electrostatic charge with the signal line place, shared distribution place does not produce electrostatic charge, and in some other embodiment, if, shared distribution place produces electrostatic charge, and the signal line place does not produce electrostatic charge, produce the pairing voltage V2 of the second electrostatic charge q2 on the so shared distribution and will make the 4th diode D4, the second field effect transistor Q2 and the 3rd diode D3 conducting, make the second electrostatic charge q2 be discharged to signal line through the 4th diode D4, the second field effect transistor Q2 and the 3rd diode D3.In addition, in further embodiments,, can realize so discharging simultaneously when signal line place and shared distribution place all produce electrostatic charge.By as can be known aforementioned, in the present embodiment, its discharge capability is suitable with the discharge capability that existing ESD protection circuit (as Fig. 1) is reached through three diodes of connecting; but; in the present embodiment, do not adopt series connection a plurality of (as 3) diode, in the time of will making layout designs.
With reference to Fig. 3, Fig. 3 has illustrated the circuit diagram of the ESD protection circuit of another execution mode of the present invention.The ESD protection circuit 300 of the described execution mode of Fig. 3 is with ESD protection circuit 200 difference of execution mode shown in Figure 2; first control electrode of the first field effect transistor Q1 and the negative pole that is coupled to first diode after first electrode is connected again; and the second diode Q2 the 3rd control electrode and the negative pole that is coupled to first diode after first electrode is connected again, and second control electrode of the second diode Q2 and the negative pole that is coupled to the 4th diode D4 after third electrode is connected.In the present embodiment, through after the aforementioned connection, the effect of Q1 just is equivalent to diode D1 so, and its forward couples mutually with the negative pole of D1, and the effect of Q2 just is equivalent to D4, and its forward couples mutually with the negative pole of D4.According to the characteristic of preceding addressing diode, as can be known, when producing electric charge on the signal line, to make the first diode D1, the first field effect transistor Q1 and the second diode D2 conducting, that is, the electrostatic charge that produces of signal line place can see through the first diode D1, the first field effect transistor Q1 and the second diode D2 is discharged to shared distribution.Otherwise, when shared distribution place produces electrostatic charge, to make the 4th diode D4, the second field effect transistor Q2 and the 3rd diode D3 conducting so, that is, the electrostatic charge that makes shared distribution place produce sees through the 4th diode D4, the second field effect transistor Q2 and the 3rd diode D3 is discharged to signal line.
As from the foregoing; ESD protection circuit proposed by the invention; its discharge capability can be suitable with the discharge capability of existing ESD protection circuit; but because do not adopt the framework of a plurality of diodes of series connection in its circuit; to the area of the circuit layout of whole ESD protection circuit be reduced, thereby reduced the area of display panels.
Above, describe the specific embodiment of the present invention with reference to the accompanying drawings.But those skilled in the art can understand, and under situation without departing from the spirit and scope of the present invention, can also do various changes and replacement to the specific embodiment of the present invention.These changes and replace all drop in claims of the present invention institute restricted portion.
Claims (10)
1. an ESD protection circuit is used for a LCD, and described LCD has a signal line and a shared distribution, it is characterized in that described ESD protection circuit comprises:
One first diode, its positive pole is coupled to described signal line;
One first field effect transistor has one first electrode, one second electrode and one first control electrode, and described first electrode is coupled to the negative pole of described first diode, and described first control electrode is coupled to described signal line;
One second diode, its positive pole are coupled to described second electrode, and negative pole is coupled to described shared distribution;
One the 3rd diode, its negative pole is coupled to described signal line, and its positive pole is coupled to described second electrode;
One second field effect transistor, have a third electrode, one the 4th electrode and one second control electrode, described third electrode is coupled to the negative pole of described first diode, and described the 4th electrode is coupled to the positive pole of described the 3rd diode, and described second control electrode is coupled to described shared distribution; And
One the 4th diode, its negative pole is coupled to the negative pole of described first diode, and its positive pole is coupled to described shared distribution;
Wherein, when one first electrostatic charge results from the described signal line, the pairing voltage of described first electrostatic charge makes described first diode, described first field effect transistor and described second diode current flow, makes described first electrostatic charge see through described first diode, described first field effect transistor and described second diode discharge to described shared distribution; When one second electrostatic charge results from the described shared distribution, the pairing voltage of described second electrostatic charge makes described the 3rd diode, described second field effect transistor and described the 4th diode current flow, makes described second electrostatic charge see through described the 3rd diode, described second field effect transistor and described the 4th diode discharge to described signal line.
2. an ESD protection circuit is used for a LCD, and described LCD has a signal line and a shared distribution, it is characterized in that described ESD protection circuit comprises:
One first diode, its positive pole is coupled to described signal line;
One first field effect transistor has one first electrode, one second electrode and one first control electrode, and described first electrode and described first control electrode are coupled to the negative pole of described first diode;
One second diode, its positive pole are coupled to described second electrode, and negative pole is coupled to described shared distribution;
One the 3rd diode, its negative pole is coupled to described signal line, and its positive pole is coupled to described second electrode;
One second field effect transistor has a third electrode, one the 4th electrode and one second control electrode, and described third electrode and described second control electrode are coupled to the negative pole of described first diode, and described the 4th electrode is coupled to the positive pole of described the 3rd diode; And
One the 4th diode, its negative pole is coupled to the negative pole of described first diode, and its positive pole is coupled to described shared distribution.
Wherein, when one first electrostatic charge results from the described signal line, the pairing voltage of described first electrostatic charge makes described first diode, described first field effect transistor and described second diode current flow, makes described first electrostatic charge see through described first diode, described first field effect transistor and described second diode discharge to described shared distribution; When one second electrostatic charge results from the described shared distribution, the pairing voltage of described second electrostatic charge makes described the 3rd diode, described second field effect transistor and described the 4th diode current flow, makes described second electrostatic charge see through described the 3rd diode, described second field effect transistor and described the 4th diode discharge to described signal line.
3. circuit according to claim 1 and 2 is characterized in that, described first field effect transistor/second field effect transistor is a N channel field-effect pipe.
4. circuit according to claim 3 is characterized in that, described N channel field-effect pipe is N channel metal-oxide-semiconductor field.
5. circuit according to claim 1 and 2 is characterized in that, described first field effect transistor/second field effect transistor is the P-channel field-effect transistor (PEFT) pipe.
6. circuit according to claim 5 is characterized in that, described P-channel field-effect transistor (PEFT) pipe is P channel metal-oxide-semiconductor field.
7. circuit according to claim 1 and 2 is characterized in that, described signal line is a scan line.
8. circuit according to claim 1 and 2 is characterized in that, described signal line is a data wire.
9. circuit according to claim 1 and 2 is characterized in that, described first field effect transistor and described second field effect transistor are same structure.
10. circuit according to claim 1 and 2 is characterized in that, described first diode, described second diode, described the 3rd diode and described the 4th diode are same structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101921486A CN102244381A (en) | 2011-07-05 | 2011-07-05 | Electrostatic discharge protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101921486A CN102244381A (en) | 2011-07-05 | 2011-07-05 | Electrostatic discharge protection circuit |
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| CN102244381A true CN102244381A (en) | 2011-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011101921486A Pending CN102244381A (en) | 2011-07-05 | 2011-07-05 | Electrostatic discharge protection circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015139362A1 (en) * | 2014-03-19 | 2015-09-24 | 深圳市华星光电技术有限公司 | Test circuit and display panel |
| CN108242446A (en) * | 2018-01-12 | 2018-07-03 | 京东方科技集团股份有限公司 | electrostatic protection structure, array substrate, display panel and display device |
| CN117937409A (en) * | 2024-03-20 | 2024-04-26 | 深圳市晶扬电子有限公司 | Compact bidirectional electrostatic protection circuit |
-
2011
- 2011-07-05 CN CN2011101921486A patent/CN102244381A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015139362A1 (en) * | 2014-03-19 | 2015-09-24 | 深圳市华星光电技术有限公司 | Test circuit and display panel |
| CN108242446A (en) * | 2018-01-12 | 2018-07-03 | 京东方科技集团股份有限公司 | electrostatic protection structure, array substrate, display panel and display device |
| CN108242446B (en) * | 2018-01-12 | 2021-01-26 | 京东方科技集团股份有限公司 | Electrostatic protection structure, array substrate, display panel and display device |
| CN117937409A (en) * | 2024-03-20 | 2024-04-26 | 深圳市晶扬电子有限公司 | Compact bidirectional electrostatic protection circuit |
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Application publication date: 20111116 |