CN102243526B - Double date rate internal memory controller and control method thereof - Google Patents
Double date rate internal memory controller and control method thereof Download PDFInfo
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- CN102243526B CN102243526B CN201010181221.5A CN201010181221A CN102243526B CN 102243526 B CN102243526 B CN 102243526B CN 201010181221 A CN201010181221 A CN 201010181221A CN 102243526 B CN102243526 B CN 102243526B
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Abstract
The invention discloses a double date rate internal memory controller and a control method thereof. The internal memory controller comprises an arbitrator, a master state machine, a refreshing management unit, a register and a power consumption management unit, wherein the master state machine feedbacks the state of a double data rate internal memory to the power consumption management; according to a note of the power consumption management, the double data rate internal memory is controlled to enter into or exit a precharging power failure state; and the power consumption management unit notices the master state machine to control the double data rate internal memory to enter into the precharging power failure state after the double data rate internal memory enters into an activated standby state and notices the master state machine to control the double data rate internal memory to exit the precharging power failure state when the arbitrator indicates that a read write command is received currently or the refreshing management unit indicates that a refreshing period is coming. By applying the controller and control method disclosed by the invention, consumption of software resource in power consumption control of the double data rate internal memory can be reduced, and a low power consumption state can rapidly exit when the read write operation is required to be carried out on the double data rate internal memory.
Description
Technical field
The present invention relates to Double Data Rate (DDR, Double Data Rate) internal memory, particularly a kind of Memory Controller Hub of DDR internal memory and control method thereof.
Background technology
DDR internal memory is a kind of memory devices of current widespread use, and central processing unit (CPU, Computer Process Unit) or other hardware-accelerated devices all need to realize by Memory Controller Hub to the read-write operation of DDR internal memory.
Fig. 1 is the structural representation of Memory Controller Hub in prior art, and this Memory Controller Hub comprises: moderator, register, host state machine, data first in first out (Data FIFO) and refresh administrative unit.
Moderator, when having a plurality of devices to initiate the read-write operation to DDR internal memory at synchronization, arbitrates out the read write command of limit priority and sends to host state machine; Data interaction repeating data in device and data first in first out.
System software controls by register configuration host state machine the opportunity that DDR internal memory enters self-refresh state.Register also carries out routine configuration to host state machine.
Refresh administrative unit, for configuring the refresh cycle, when the refresh cycle arrives, to host state machine, send refresh requests.
Host state machine, for according to the configuration of register, controls DDR internal memory and enters or exit self-refresh state; The read write command that moderator is sent is converted to the corresponding read write command of DDR memory interface and sends to DDR internal memory; Control data first in first out the data of moderator forwarding are sent to DDR internal memory, or the data that DDR internal memory is sent send to moderator; After receiving the refresh requests that refreshes administrative unit transmission, to DDR internal memory, send automatic refresh command, to control DDR internal memory, automatically refresh.
Read-write operation for DDR internal memory carries out in the following manner:
1) host state machine receive that moderator sends to after the read write command of DDR internal memory, need to first activate DDR internal memory.Activation comprises the steps: that host state machine sends activation command to DDR internal memory, comprises the heap that needs read operation (bank) and row (row) address of CPU or other hardware-accelerated device appointments in activation command; Inner at DDR internal memory, complete the decoding of described row address and produce row selected signal the data of this row in capacitance stores array are delivered to induction amplifier (SA, Sense Amplifier), after data rest on SA, DDR internal memory is in state of activation.
2) at DDR internal memory after state of activation, if read operation, host state machine is converted to the read command receiving and the corresponding read command of DDR memory interface, comprises the row that need read operation (column) address of CPU or other hardware-accelerated device appointments in this read command.Inner at DDR internal memory, to above-mentioned column address decoding and produce the data that selected signal is chosen SA the inside, then data are input to read latch, finally output on data line.Host state machine is controlled data first in first out the data on data line is sent to moderator, then is transmitted to CPU or other hardware-accelerated devices by moderator.After read operation completes, DDR internal memory is in activating holding state.
3) at DDR internal memory after state of activation, if write operation, host state machine is converted to the write order receiving and the corresponding write order of DDR memory interface, the column address that needs write operation that comprises CPU or other hardware-accelerated device appointments in this write order, then the first in first out of host state machine control data outputs to data to be written on data line.Inner at DDR internal memory, the data on data line are latched in input register, and then data are written to position corresponding to above-mentioned column address in SA, finally carry out precharge operation the data in SA are write to capacitance stores array the inside.After write operation completes, DDR internal memory is in activating holding state.
The dynamic power consumption that DDR internal memory is produced by read-write operation is difficult to reduce, and when not carrying out read-write operation, DDR internal memory may be in activating standby (active standby) state, precharge standby (precharge standby) state, activating power down (active power down) state, precharge power down (precharge power down) state and self-refresh (self refresh) state, and the power consumption under these states is called quiescent dissipation.Wherein, the power consumption activating under holding state and activation power-down state is larger, and the power consumption under precharge holding state is in medium level, and the power consumption under precharge power-down state and self-refresh state is less.
At present, in order to reduce the power consumption of DDR internal memory, if there is no for a long time read-write operation, major state chance is controlled DDR internal memory and is entered self-refresh state to reduce power consumption, at this moment DDR internal memory is equivalent to dormant state, data can not lost, but if again the data in DDR internal memory are read and write and needed the time of waiting for 200 clock period and an automatic refresh command just can exit self-refresh state.In addition, system software need to design special power managed process judgement and when can enter self-refresh state, when need to exit, and need to reconfigure host state machine by register, just can make host state machine enter or to exit self-refresh state controlling DDR internal memory opportunity accurately.Said system software judges that the required time is generally all more than millisecond rank, and in some portable system, every a regular time, just need to carry out read-write operation to DDR internal memory, this set time, conventionally also in millisecond rank, so not only needs software resource and response speed that consumption is larger very slow.
Summary of the invention
The invention provides a kind of Memory Controller Hub of DDR internal memory, can reduce the consumption of software resource aspect the control of DDR power consumption of internal memory, and when needs carry out read-write operation to DDR internal memory, exit fast low power consumpting state.
The invention provides a kind of control method of above-mentioned Memory Controller Hub, can reduce the consumption of software resource aspect the control of DDR power consumption of internal memory, and when needs carry out read-write operation to DDR internal memory, exit fast low power consumpting state.
Technical scheme of the present invention is achieved in that
A Memory Controller Hub for DDR internal memory, comprising: moderator, host state machine, refresh administrative unit and register, wherein register pair host state machine carries out routine configuration; Key is, also comprises power management unit in described Memory Controller Hub;
Described host state machine, to the state of power management unit feedback DDR internal memory; According to the notice of power management unit, control DDR internal memory and enter or exit precharge power-down state;
Described power management unit, at DDR internal memory, enter and activate after holding state, notice host state machine is controlled DDR internal memory and is entered precharge power-down state, and receive read write command or refresh the administrative unit indication refresh cycle while arriving moderator indication is current, notice host state machine is controlled DDR internal memory and is exited precharge power-down state.
A control method for above-mentioned Memory Controller Hub, key is, the method comprises:
A, power management unit receive the state of the DDR internal memory of host state machine feedback, judge whether DDR internal memory enters activation holding state, if execution step B, otherwise continue execution step A;
B, power management unit notice host state machine are controlled DDR internal memory and are entered precharge power-down state;
C, power management unit monitor when moderator indication is current to be received read write command or refresh administrative unit indication refresh cycle arrival, and indication host state machine is controlled DDR internal memory and exited precharge power-down state.
Visible, the Memory Controller Hub that the embodiment of the present invention provides and control method thereof, in inside, increased power management unit, this power management unit at DDR internal memory when activating holding state, notice host state machine is controlled DDR internal memory and is entered the lower duty of this power consumption of precharge power-down state, and externally input read write command or refresh cycle while arriving, notice host state machine is controlled DDR internal memory and is exited precharge power-down state.On the one hand, power management unit is as the hardware of Memory Controller Hub inside, without system software, special power managed process is set, also need to after each control DDR internal memory enters or exits low power consumpting state, reconfigure register, saved the consumption of system software on power managed; On the other hand, if while needing DDR internal memory to exit precharge power-down state because receiving new read write command, only need 3 clock period, if while needing DDR internal memory to exit pre-charge state because carry out self refresh operation, only need 1 clock period, substantially the read-write efficiency and the response time that do not affect Memory Controller Hub, response speed improves greatly.
Accompanying drawing explanation
Fig. 1 is the inner structure schematic diagram of Memory Controller Hub in prior art;
Fig. 2 is the structural representation of the Memory Controller Hub of DDR internal memory in the embodiment of the present invention;
Fig. 3 is the signal transmission schematic diagram of power management unit described in Fig. 2;
Fig. 4 is the sequential chart of CPU access DDR internal memory in this application example
Fig. 5 is the state transition graph of DDR internal memory in the embodiment of the present invention;
Fig. 6 is the control method process flow diagram of the Memory Controller Hub of DDR internal memory in the embodiment of the present invention.
Embodiment
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
The structural representation of the Memory Controller Hub of the DDR internal memory that Fig. 2 provides for the embodiment of the present invention, this Memory Controller Hub comprises: moderator, host state machine, refresh administrative unit and register, annexation between them and mutual with of the prior art identical, just system software no longer controls by register configuration host state machine the opportunity that DDR internal memory entered or exited low power consumpting state, register only carries out known conventional configuration to host state machine, refresh in addition administrative unit and be not directly connected with host state machine, repeat no more here.In Fig. 2, also show and will carry out to DDR internal memory CPU and the equipment such as direct memory access (DMA) (DMA), Video Codec and display of read-write operation.
In this Memory Controller Hub, also comprise power management unit.
Above-mentioned host state machine, for the state to power management unit feedback DDR internal memory; According to the notice of power management unit, control DDR internal memory and enter or exit precharge power-down state.
Above-mentioned power management unit, for entering at DDR internal memory, activate after holding state, notice host state machine is controlled DDR internal memory and is entered precharge power-down state, and receive read write command or refreshing the administrative unit indication refresh cycle while arriving moderator indication is current, notice host state machine is controlled DDR internal memory and is exited precharge power-down state.If power management unit notice host state machine control DDR internal memory exits precharge power-down state when refreshing administrative unit indication refresh cycle arrival, power management unit also can notify host state machine control DDR internal memory automatically to refresh.Further, when DDR internal memory is during in automatic Flushing status, if host state machine is received the read write command that moderator sends, after automatically having refreshed, activate DDR internal memory, if do not receive the read write command that moderator sends, again control DDR internal memory and enter precharge power-down state after automatically having refreshed.
Above-mentioned power management unit notice host state machine is controlled more than a kind of situation on opportunity that DDR internal memory enters precharge power-down state, and the embodiment of the present invention provides a kind of situation of determining this opportunity by timing.Register is power management unit configuration timing threshold value N, the concrete value of N can need to be determined according to practical application, power management unit starts timing when DDR internal memory enters activation holding state, notifies host state machine to control DDR internal memory and enter precharge power-down state when the clock period of timing surpasses timing threshold value N.
In the embodiment of the present invention, host state machine is controlled DDR internal memory and is entered or exit certain state, or control DDR internal memory and carry out certain operation, all by corresponding order, realize, for example, when host state machine control DDR internal memory enters precharge power-down state, can send precharge power-down state to DDR internal memory and enter order, when control DDR internal memory refreshes automatically, can send automatic refresh command to DDR internal memory.The format and content of these orders all belongs to the common practise of this area, repeats no more here.
Fig. 3 is the signal transmission schematic diagram of power management unit described in Fig. 2.
Power management unit is provided with command request input interface, configuration input interface, activates holding state input interface, state of activation input interface, the first refresh requests input interface, the first refresh requests output interface, the first precharge power-down state output interface and the second precharge power-down state output interface.
Mentioned order request input interface is connected by signal wire with the command request output interface of moderator, power management unit receives by this command request output interface command request (cmd request) signal that moderator sends, the current read write command that whether has outside input of this command request signal indication.
Above-mentioned configuration input interface is connected by signal wire with the configuration output interface of register, register configuration (register configure) signal that power management unit sends by this configuration input interface receiving register, carries the timing threshold value N of register configuration in this register configuration signal.
Above-mentioned activation holding state input interface is connected by signal wire with the activation holding state output interface of host state machine, power management unit activates holding state input interface by this and receives activation holding state (the active standby state) signal that host state machine sends, and whether this activates the current DDR internal memory of holding state signal designation in activating holding state.
Above-mentioned state of activation input interface is connected by signal wire with the state of activation output interface of host state machine, power management unit receives by this state of activation input interface state of activation (active state) signal that host state machine sends, and whether the current DDR internal memory of this state of activation signal designation is in state of activation.When DDR internal memory is during in state of activation, power management unit undo.
Above-mentioned the first refresh requests input interface is connected by signal wire with the second refresh requests output interface that refreshes administrative unit, power management unit is received and is refreshed automatic refresh requests (the Auto refresh request) signal that administrative unit sends by this first refresh requests input interface, and the prompting refresh cycle arrives.
Above-mentioned the first refresh requests output interface is connected by signal wire with the second refresh requests input interface of host state machine, power management unit sends refresh requests (refresh request) signal by this first refresh requests output interface to host state machine, and indication host state machine is controlled DDR internal memory and automatically refreshed.
Above-mentioned the first precharge power-down state output interface is connected by signal wire with the first precharge power-down state input interface of host state machine, power management unit sends precharge power-down state by this first precharge power-down state output interface to host state machine and enters (precharge power down enter) signal, and indication host state machine is controlled DDR internal memory and entered precharge power-down state.
Above-mentioned the second precharge power-down state output interface is connected by signal wire with the second precharge power-down state input interface of host state machine, power management unit sends precharge power-down state by this second precharge power-down state input interface to host state machine and exits (precharge power down exit) signal, and indication host state machine is controlled DDR internal memory and exited precharge power-down state.
Power management unit and register, moderator, refresh various signals mutual between administrative unit and host state machine and be level signal, make an appointment and make the clear and definite varying level of mutual both sides combine the content of representative, can realize previously described various indication.
Provide a concrete application example of the Memory Controller Hub that the embodiment of the present invention provides below.
In this application example, CPU access DDR internal memory carries out write operation.Fig. 4 is the sequential chart of CPU access DDR internal memory in this application example.Wherein CKE, RAS and CAS are the pins of steering logic in DDR internal memory, and DQS is the latch signal in write operation, and these are all common practise of this area, repeat no more here.
Constantly, DDR internal memory is in idle condition for T1.
Constantly, CPU sends write order and address to T2 in bus.
Constantly, CPU sends the data that will write to T3 in bus.
Constantly, Memory Controller Hub sends activation command to DDR internal memory to T4, and DDR internal memory enters state of activation.
Constantly, Memory Controller Hub sends write order to DDR internal memory to T6.
Constantly, Memory Controller Hub starts to write data to DDR internal memory T7.
Constantly, Memory Controller Hub sends precharge command and completes write operation T10, and this precharge command continues 3 clock period, and DDR internal memory is in activating holding state afterwards.
Constantly, the power management unit in Memory Controller Hub starts timing to T13, and when timing reaches while also not receiving new read write command in N clock period bus, notice host state machine is controlled DDR internal memory and entered precharge power-down state with saving power consumption.
Above-mentioned application example has only been enumerated the various state conversion process of Memory Controller Hub in write operation application, and more complicated applications can embody in the state transition graph shown in Fig. 5.
Power management unit in the Memory Controller Hub that the embodiment of the present invention provides, can be used programmable logic device (PLD) to realize, and the various functions of this power management unit can be programmed and be write programmable logic device (PLD).
The embodiment of the present invention also provides a kind of control method of described Memory Controller Hub above, the process flow diagram that Fig. 6 is this control method, and the method comprises the steps:
Step 11: power management unit receives the state of the DDR internal memory of host state machine feedback.
Step 12: judge whether DDR internal memory enters activation holding state, if execution step 13, otherwise continue execution step 12.
Step 13: power management unit notice host state machine is controlled DDR internal memory and entered precharge power-down state.
Step 14: power management unit monitors when moderator indication is current to be received read write command or refresh administrative unit indication refresh cycle arrival, and indication host state machine is controlled DDR internal memory and exited precharge power-down state.
In above-mentioned steps 13, power management unit notice host state machine control DDR internal memory may further include: when DDR internal memory enters activation holding state, start timing before entering precharge power-down state.When the clock period of timing is greater than the timing threshold value of register configuration, power management unit is carried out described notify status machine again and is controlled the operation that DDR internal memory enters precharge power-down state.
In above-mentioned steps 14, when power management unit monitors, refresh the administrative unit indication refresh cycle while arriving, can further indicate host state machine to control DDR internal memory and automatically refresh.Further, when DDR internal memory is during in automatic Flushing status, if host state machine is received the read write command that moderator sends, after automatically having refreshed, activate DDR internal memory, if do not receive the read write command that moderator sends, again control DDR internal memory and enter precharge power-down state after automatically having refreshed.
Identical with introducing in Memory Controller Hub, in said method, power management unit and register, moderator, refresh various mutual between administrative unit and host state machine, all by signal, transmit realization, concrete signal type repeats no more here, these signals are also all level signals, make an appointment and make the clear and definite varying level of mutual both sides combine the content of representative.
Can find out, the Memory Controller Hub apparatus control method that the embodiment of the present invention provides, in inside, increased power management unit, this power management unit at DDR internal memory when activating holding state, notice host state machine is controlled DDR internal memory and is entered the lower duty of this power consumption of precharge power-down state, and externally input read write command or refresh cycle while arriving, notice host state machine is controlled DDR internal memory and is exited precharge power-down state.On the one hand, power management unit is as the hardware of Memory Controller Hub inside, without system software, special power managed process is set, also need to after each control DDR internal memory enters or exits low power consumpting state, reconfigure register, saved the consumption of system software on power managed; On the other hand, if while needing DDR internal memory to exit precharge power-down state because receiving new read write command, only need 3 clock period, if while needing DDR internal memory to exit pre-charge state because carry out self refresh operation, only need 1 clock period, substantially the read-write efficiency and the response time that do not affect Memory Controller Hub, response speed improves greatly.
In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. a Memory Controller Hub for Double Data Rate internal memory, comprising: moderator, host state machine, refresh administrative unit and register, host state machine carries out routine configuration described in wherein said register pair; It is characterized in that, in described Memory Controller Hub, also comprise power management unit;
Described host state machine, to the state of power management unit feedback Double Data Rate internal memory; According to the notice of power management unit, control Double Data Rate internal memory and enter or exit precharge power-down state;
Described power management unit, at Double Data Rate internal memory, enter and activate after holding state, notice host state machine is controlled Double Data Rate internal memory and is entered precharge power-down state, and receive read write command or refresh the administrative unit indication refresh cycle while arriving moderator indication is current, notice host state machine is controlled Double Data Rate internal memory and is exited precharge power-down state.
2. Memory Controller Hub as claimed in claim 1, is characterized in that, the timing threshold value of described register configuration power management unit;
First described power management unit starts timing when Double Data Rate internal memory enters activation holding state, when the clock period of timing is greater than described timing threshold value, reinforms host state machine control Double Data Rate internal memory and enters precharge power-down state.
3. Memory Controller Hub as claimed in claim 1, is characterized in that, described power management unit, when refreshing administrative unit indication refresh cycle arrival, is further notified host state machine to control Double Data Rate internal memory and automatically refreshed.
4. the Memory Controller Hub as described in claim 1 or 3, it is characterized in that, when host state machine does not receive the read write command of moderator transmission in the automatic refresh process of Double Data Rate internal memory, further after automatically having refreshed, control Double Data Rate internal memory and enter precharge power-down state.
5. a control method for Memory Controller Hub as claimed in claim 1, is characterized in that, the method comprises:
A, power management unit receive the state of the Double Data Rate internal memory of host state machine feedback, judge whether Double Data Rate internal memory enters activation holding state, if execution step B, otherwise continue execution step A;
B, power management unit notice host state machine are controlled Double Data Rate internal memory and are entered precharge power-down state;
C, power management unit monitor when moderator indication is current to be received read write command or refresh administrative unit indication refresh cycle arrival, and indication host state machine is controlled Double Data Rate internal memory and exited precharge power-down state.
6. method as claimed in claim 5, it is characterized in that, in described step B, power management unit notice host state machine control Double Data Rate internal memory further comprises: when Double Data Rate internal memory enters activation holding state, start timing before entering precharge power-down state;
When the clock period of described timing is greater than the timing threshold value of register configuration, then carries out described notice host state machine and control the operation that Double Data Rate internal memory enters precharge power-down state.
7. method as claimed in claim 5, is characterized in that, in described step C, when power management unit monitors, refreshes the administrative unit indication refresh cycle while arriving, and further indicates host state machine to control Double Data Rate internal memory and automatically refreshes.
8. method as claimed in claim 7, it is characterized in that, after described step C, when host state machine does not receive the read write command of moderator transmission in the automatic refresh process of Double Data Rate internal memory, further control Double Data Rate internal memory and enter precharge power-down state.
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| JP7292872B2 (en) * | 2018-12-25 | 2023-06-19 | キヤノン株式会社 | Information processing device and information processing device control method |
| WO2020155074A1 (en) * | 2019-01-31 | 2020-08-06 | 华为技术有限公司 | Processing apparatus, method, and related device |
| CN112732603A (en) * | 2019-10-14 | 2021-04-30 | 广州飒特红外股份有限公司 | Multi-channel VDMA control method and application thereof |
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| US20040059954A1 (en) * | 2002-09-20 | 2004-03-25 | Rainer Hoehler | Automatic low power state entry |
| CN1588552A (en) * | 2004-09-16 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Control device and method for double speed dynamic random access storage with asynchronous buffer |
| CN101034306A (en) * | 2007-04-24 | 2007-09-12 | 北京中星微电子有限公司 | Control method for low-power consumption RAM and RAM control module |
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| US20040059954A1 (en) * | 2002-09-20 | 2004-03-25 | Rainer Hoehler | Automatic low power state entry |
| CN1588552A (en) * | 2004-09-16 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Control device and method for double speed dynamic random access storage with asynchronous buffer |
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