CN102238413B - High-reliability asynchronous serial interface (ASI) signal switching equipment and ASI signal failure delay judgment method - Google Patents
High-reliability asynchronous serial interface (ASI) signal switching equipment and ASI signal failure delay judgment method Download PDFInfo
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Abstract
The invention relates to high-reliability asynchronous serial interface (ASI) signal switching equipment and an ASI signal failure delay judgment method. The high-reliability ASI signal switching equipment provided by the invention aims to make the ASI signal input of a main path and a spare path can be output simultaneously by a bypass in a power failure or hardware failure and avoid the random switching of signal broadcast by ASI signal failure delay judgment in normal broadcast. The equipment comprises an ASI signal interruption delay unit, a synchronous byte error delay unit, a transmission error delay unit and a packet identifier (PID) code rate anomaly delay unit. ASI signals entering an ASI signal failure delay judgment module are processed by the four units to determine the existence and inexistence of a failure required to be switched. The equipment also comprises a spare switching relay and a spare bypass relay. Spare ASI signals are output directly from a spare ASI signal output interface in the power failure or hardware failure. By the equipment and the method, the secure and reliable broadcast of a digital television is ensured.
Description
Technical field
The present invention relates to the digital television techniques field, be specifically related to a kind of ASI signal switching equipment of high reliability and ASI signal fault delay decision method.
Background technology
How to guarantee that complete, the safe work of digital television program is the necessary functions of the Digital Television Station equipment.In common broadcast system link, have at least main road, standby road, when main road breaks down or automatic or manual switch to standby road, ensure the safety of final output.The product A methyst III Digital Television intelligence switch (user's manual Amethyst3_01.02.00_UserGuide_C.pdf) that Thomson video broadcasting company (Thomson Video Networks) issues in October, 2010, function ratio is more comprehensive, support multi-channel A SI manually (manual), redundancy (redundancy, semi-automatic, switch to another road during the current demand signal mistake), preferential (the main-spare of main road, automatically, switch to standby road during the main road mistake, automatic switchback main road after main road recovers) switch mode; Support minor failure to report to the police (minor alarm), major failure is reported to the police (major alarm), and the time-delay of catastrophe failure warning (critical alarm) is switched; Support the one tunnel main quick and safe output (Smart-Secured Outputs) with transfer relay and bypass relay.The present invention is directed to above-mentioned prior art and done improvement.ASI signal fault delay decision of the present invention, active and standby road cut off the power supply simultaneously or the ASI signal switching equipment of high reliability of bypass output during hardware fault has no report.
Summary of the invention
The objective of the invention is, provide ASI signal input in a kind of active and standby road can cut off the power supply simultaneously or bypass output during hardware fault, ASI signal fault delay decision when normally broadcasting, the ASI signal switching equipment of high reliability of avoiding broadcasting signal arbitrarily to switch.
One purpose more of the present invention is that ASI signal fault delay decision when a kind of normal broadcast is provided is avoided the arbitrarily ASI signal fault delay decision method of switching of broadcasting signal.
For achieving the above object, the technical scheme that the present invention takes is: a kind of ASI signal switching equipment of high reliability comprises main ASI signal input interface, standby ASI signal input interface, main transfer relay, main bypass relay, master equalizer, standby equalizer, main deserializer, standby deserializer, ASI signal pre-processing module, ASI signal fault delay decision module, ASI signal switchover policy administration module, serializer, driver, main ASI signal output interface, standby ASI signal output interface; Main ASI signal connects main transfer relay from main ASI signal input interface, directly exports from main ASI signal output interface by main bypass relay when outage or hardware fault, and when powering on, by master equalizer, main deserializer enters the ASI signal pre-processing module and processes; Standby ASI signal connects standby ASI signal input interface by standby equalizer, enters the ASI signal pre-processing module after standby deserializer and processes; Through ASI signal fault delay decision resume module, the signal of output is through serializer under ASI signal switchover policy administration module is controlled for ASI signal after processing, and driver is at main ASI signal output interface, and standby ASI signal output interface is exported simultaneously; ASI signal fault delay decision module comprises ASI signal interruption delay unit, the wrong delay unit of sync byte, transmit wrong delay unit, the abnormal delay unit of PID code check, the ASI signal that enters ASI signal fault delay decision module determines whether to exist through above-mentioned four cell processing the fault that needs switching.
A kind of ASI signal switching equipment of high reliability of the present invention also comprises standby transfer relay, standby bypass relay, standby ASI signal connects standby transfer relay from standby ASI signal input interface, passes through standby bypass relay when outage or hardware fault directly from standby ASI signal output interface output.
For realizing above-mentioned second purpose, the technical scheme that the present invention takes is: a kind of ASI fault delay decision method, comprise the following steps: detect the ASI signal and whether interrupt, and determine whether to exist the fault of needs switching according to ASI signal interruption duration parameter; Detect whether mistake of sync byte, and error rate parameter wrong according to sync byte, the wrong wrong timing parameter of sync byte, whether sync byte is misrepresented deliberately alert delay parameter and is determined to exist and need the fault switched; Whether the detected transmission bag mistake, and according to the wrong error rate parameter of transmission, transmit wrong wrong timing parameter, and transmission is misrepresented deliberately alert delay parameter and determined whether there is the fault that needs switching; Whether extremely, detect the PID code check, and according to PID code check lower limit parameter, PID limit bit rate parameter, PID code check abnormal alarm delay parameter determines whether there is the fault that needs switching.
The present invention has following beneficial effect: use ASI signal fault delay decision, avoided occurring small mistake and just switched current demand signal in the broadcast process, avoid broadcasting signal arbitrarily to switch impact and broadcast effect, especially the present invention has opened the time-delay of ASI signal interruption, the wrong time-delay of sync byte, the wrong time-delay of transmission, the major parameter of the abnormal time-delay of PID code check, the user can be according to the actual conditions configuration parameter, and reliable the broadcast ensures safety; ASI signal input in active and standby road can be cut off the power supply or bypass output during hardware fault simultaneously, ensures that active and standby road signal still can pass through equipment in device powers down or hardware fault situation, and signal does not interrupt, and broadcast ensures safety.
Description of drawings
Fig. 1 is described a kind of ASI signal switching equipment of high reliability principle schematic.
Fig. 2 is described a kind of ASI signal switching equipment of high reliability ASI signal fault delay decision modular structure schematic diagram.
Fig. 3 is described a kind of ASI fault delay decision method flow diagram.
Embodiment
The invention will be further described below in conjunction with embodiment and with reference to accompanying drawing.
The described a kind of ASI signal switching equipment of high reliability principle schematic of accompanying drawing 1, the Reference numeral and the part that wherein relate to are as follows:
1. the main transfer relay of main ASI signal input interface 2.
3. the main deserializer of master equalizer 4.
5. standby ASI signal input interface 6. is for transfer relay
7. standby equalizer 8. is for deserializer
9. main ASI signal output interface 10. is for the ASI signal output interface
11. the standby bypass relay of main bypass relay 12.
13. driver 14. serializers
15. condition reception interface 16.ASI signal pre-processing module
17. descrambling module 18. ASI signal switchover policy administration modules
19.ASI signal fault postpones handover module
Embodiment 1, can cut off the power supply simultaneously or bypass output during hardware fault for active and standby road ASI signal input, and when normally broadcasting, ASI signal fault delay decision, avoid broadcasting signal arbitrarily to switch, and the present embodiment provides a kind of ASI signal switching equipment of high reliability.Referring to Fig. 1, particular content is as follows:
Comprise main ASI signal input interface 1, standby ASI signal input interface 5, main transfer relay 2, standby transfer relay 6, main bypass relay 11, standby bypass relay 12, master equalizer 3, standby equalizer 7, main deserializer 4, standby deserializer 8, condition reception interface 15, descrambling unit 17, ASI signal pre-processing module 16, ASI signal fault delay decision module 19, ASI signal switchover policy administration module 18, serializer 14, driver 13, main ASI signal output interface 9, standby ASI signal output interface 10; Main ASI signal connects main transfer relay 2 from main ASI signal input interface 1, directly export from main ASI signal output interface 9 by main bypass relay 11 when outage or hardware fault, when powering on, by master equalizer 3, main deserializer 4 enters described ASI signal pre-processing module 16 and processes; Standby ASI signal connects 5 from standby ASI signal input and connects standby transfer relay 6, directly export from standby ASI signal output interface 10 by standby bypass relay 12 when outage or hardware fault, by standby equalizer 7, enter ASI signal pre-processing module 16 after standby deserializer 8 and process when powering on; ASI signal after processing is processed through ASI signal fault delay decision module 19 under ASI signal switchover policy administration module 18 is controlled, the signal of output is through serializer 14, driver 13 is at main ASI signal output interface 9, and standby ASI signal output interface 10 is exported simultaneously; Condition reception interface 15 is connected with descrambling unit 17, and the ASI signal that enters ASI signal pre-processing module 16 can be by descrambling unit 17 descramblings.
Fig. 2 is described a kind of ASI signal switching equipment of high reliability ASI signal fault delay decision modular structure schematic diagram.The Reference numeral and the part that wherein relate to are as follows:
191. ASI signal interruption delay unit 1911. ASI signal interruption duration registers
192. the wrong error rate register of wrong delay unit 1921. sync bytes of sync byte
1922. the wrong wrong timing register of sync byte 1923. sync bytes are misrepresented deliberately alert delay register
193. transmit the wrong delay unit 1931. wrong error rate registers of transmission
Misrepresent deliberately alert delay register 1932. transmit wrong wrong timing register 1933. transmission
194. the abnormal delay unit 1941. PID code check lower limit registers of PID code check
1942. PID limit bit rate register 1943. PID code check abnormal alarm delay registers
ASI signal fault delay decision module 19 comprises ASI signal interruption delay unit 191, the wrong delay unit 192 of sync byte, transmit wrong delay unit 193, the abnormal delay unit 194 of PID code check, the ASI signal that enters ASI signal fault delay decision module 19 determines whether to exist through above-mentioned four cell processing the fault that needs switching.ASI signal interruption delay unit 191 comprises configurable ASI signal interruption duration register 1911; The wrong delay unit 192 of sync byte comprises the wrong error rate register 1921 of configurable sync byte, the wrong wrong timing register 1922 of sync byte, and sync byte is misrepresented deliberately alert delay register 1923; Transmit wrong delay unit 193 and comprise the wrong error rate register 1931 of configurable transmission, transmit wrong wrong timing register 1932, alert delay register 1933 is misrepresented deliberately in transmission; The abnormal delay unit 194 of PID code check comprises configurable PID code check lower limit register 1941, PID limit bit rate register 1942, PID code check abnormal alarm delay register 1943.
Embodiment 2: can cut off the power supply simultaneously or bypass output during hardware fault for active and standby road ASI signal input, when normally broadcasting, ASI signal fault delay decision, avoid broadcasting signal arbitrarily to switch, and the present embodiment provides a kind of ASI signal switching equipment of high reliability.Referring to Fig. 1, Fig. 2, particular content is as follows:
Main transfer relay 2, standby transfer relay 6, main bypass relay 11 for bypass relay 12, is selected the high frequency relay of Omron Corp, and concrete this example of model does not limit.Master equalizer 3, standby equalizer 7, employing LM0034(SMPTE 292M/259M Adaptive Cable Equalizer), detect the ASI signal and also input the chip that unstrings after equilibrium.Main deserializer 4, standby deserializer 8 adopts GS9091B(270Mb/s Deserializer for SDI and DVB-ASI with Integrated Cable Equalizer), the clock that can recover the ASI signal is used for forwarding.Serializer 14 adopts GS9092B(270Mb/s serializer with an internal FIFO and an integrated cable driver), transfer the SPI signal to the ASI signal.Driver 13 adopts LM0002(SMPTE 292M/259M Serial Digital Cable Driver), the transmittability of increase ASI signal.Main ASI signal input interface 1, standby ASI signal input interface 5 adopts BNC connector.Main ASI signal input interface 1, main transfer relay 2, master equalizer 3, main deserializer 4 consists of the main channel; Standby ASI signal input interface 5, standby transfer relay 6, standby equalizer 7, standby deserializer 8 consists of standby passage.ASI signal pre-processing module 16 has or not selection wherein one the tunnel to export ASI signal switchover policy administration module 18 to according to the input signal carrier wave, and when signal exists simultaneously, the main channel is preferential.Main ASI signal output interface 9, standby ASI signal output interface 10 adopts BNC connector.Two paths of signals is exported simultaneously, and one the tunnel is main output channel, and one the tunnel is the backup output channel, and the content of two outputs is identical.The function of bypass when main output channel and primary input passage have outage or hardware fault, the function of bypass when standby output channel and standby input channel have outage or hardware fault.Descrambling unit 17, ASI signal pre-processing module 16 adopts the FPGA(field programmable gate array) realize, concrete this example of model is not restricted; ASI signal fault delay decision module 19, ASI signal switchover policy administration module 18 adopts CPU board (microprocessor adds peripheral components) to realize, and concrete this example of model is not restricted.
The ASI signal was mainly comprising for the SPI stream of parallel port through serializer in the past through after removing the string device: the SPI stream that outputs to descrambling unit 17; The SPI stream of descrambling unit 17 outputs; Output to the SPI stream of CPU board, totally 2 the tunnel; SPI stream from CPU board output.
When device powers down or hardware fault, automatically with active and standby two-way input signal source bypass output.After when normally powering on, active and standby two-way ASI signal transfers parallel SPI signal to, be input to the ASI signal pre-processing module 16 on FPGA, master equalizer 3 simultaneously, standby equalizer 7 is transferred to ASI signal switchover policy administration module 18 on CPU board with the signal condition of ASI.Main ASI signal input interface 1, the ASI stream of standby ASI signal input interface 5 inputs is not with CA(Certificate Authority) time, two-way SPI is sent into CPU board simultaneously.When main ASI signal input interface 1, the ASI stream band CA of standby ASI signal input interface 5 inputs, according to master equalizer 3, condition selecting one road SPI of standby equalizer 7 sends into descrambling unit 17 by CPU, and CPU board is sent the signal after descrambling in descrambling unit 17.Two-way ASI signal is processed through ASI signal fault delay decision module 19 and is differentiated effectively under ASI signal switchover policy administration module 18 is controlled, and when switches.The height of CPU board by IO controlled the function of FPGA, comprise relay switch, whether separate CA.
The strategy of ASI signal switchover policy administration module 18: switch to standby passage when break down in the main channel, standby passage switches to the main channel when breaking down.If the destination channel that switches exists fault not switch.
ASI signal fault delay decision module 19 supports that user configured parameter is as follows:
The PID maximum can arrange 30, and code check and the time-delay of reporting to the police need to arrange separately for each PID.If delay parameter is set to 0, expression corresponding mistake occurs and just switches immediately.The user can check the current concrete passage that is using, and can manually switch to another passage.Other are identical with embodiment 1.
Embodiment 3: ASI signal fault delay decision when normally broadcasting for Digital Television, and avoid broadcasting signal arbitrarily to switch, the present embodiment provides a kind of ASI signal fault delay decision method.Referring to Fig. 3, particular content is as follows:
Comprise step 200: enter ASI signal fault delay decision module, beginning ASI signal fault postpones to detect.
Step 201: detect the ASI signal and whether interrupt, and determine whether to exist the fault of needs switching according to ASI signal interruption duration parameter.
Step 202: detect whether mistake of sync byte, and error rate parameter wrong according to sync byte, the wrong wrong timing parameter of sync byte, whether sync byte is misrepresented deliberately alert delay parameter and is determined to exist and need the fault switched.
Step 203: whether the detected transmission bag mistake, and according to the wrong error rate parameter of transmission, transmit wrong wrong timing parameter, and transmission is misrepresented deliberately alert delay parameter and determined whether there is the fault that needs switching;
Step 204: whether extremely detect the PID code check, and according to PID code check lower limit parameter, PID limit bit rate parameter, PID code check abnormal alarm delay parameter determines whether there is the fault that needs switching.
Step 205: above-mentioned steps 201-204 conclusion is all no, and sign A SI signal is normal.
The arbitrary conclusion of step 206: above-mentioned steps 201-204 is yes, and there is the fault that needs switching in sign A SI signal.
The above is only the preferred embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvement and replenish, these improvement and replenish and also should be considered as protection scope of the present invention.
Claims (3)
1. an ASI signal switching equipment of high reliability, comprise main ASI signal input interface, standby ASI signal input interface, main transfer relay, standby transfer relay, main bypass relay, standby bypass relay, master equalizer, standby equalizer, main deserializer, standby deserializer, ASI signal pre-processing module, ASI signal fault delay decision module, ASI signal switchover policy administration module, serializer, driver, main ASI signal output interface, standby ASI signal output interface; Main ASI signal connects main transfer relay from main ASI signal input interface, directly export from main ASI signal output interface by main bypass relay when outage or hardware fault, when powering on, by master equalizer, main deserializer enters described ASI signal pre-processing module and processes; Standby ASI signal connects standby transfer relay from standby ASI signal input interface, directly export from standby ASI signal output interface by standby bypass relay when outage or hardware fault, when powering on, by standby equalizer, standby deserializer enters described ASI signal pre-processing module and processes; Through ASI signal fault delay decision resume module, the signal of output is through serializer under ASI signal switchover policy administration module is controlled for ASI signal after processing, and driver is at main ASI signal output interface, and standby ASI signal output interface is exported simultaneously; Described ASI signal fault delay decision module comprises ASI signal interruption delay unit, the wrong delay unit of sync byte, transmit wrong delay unit, the abnormal delay unit of PID code check, the ASI signal that enters ASI signal fault delay decision module determines whether to have the fault that needs switching through above-mentioned four cell processing, and it is characterized in that: described ASI signal interruption delay unit comprises configurable ASI signal interruption duration register; The wrong delay unit of described sync byte comprises the wrong error rate register of configurable sync byte, the wrong wrong timing register of sync byte, and sync byte is misrepresented deliberately alert delay register; The wrong delay unit of described transmission comprises the wrong error rate register of configurable transmission, transmits wrong wrong timing register, and alert delay register is misrepresented deliberately in transmission; The abnormal delay unit of described PID code check comprises configurable PID code check lower limit register, PID limit bit rate register, PID code check abnormal alarm delay register.
2. a kind of ASI signal switching equipment of high reliability according to claim 1, it is characterized in that: comprise the condition reception interface, described ASI signal pre-processing module comprises the descrambling unit, described condition reception interface is connected with described descrambling unit, and the ASI signal that enters described ASI signal pre-processing module can be by described descrambling unit descrambling.
3. application rights requires a kind of ASI fault delay decision method of the 1 or 2 described equipment of arbitrary claim, it is characterized in that comprising the following steps:
Detect the ASI signal and whether interrupt, and determine whether to exist the fault of needs switching according to ASI signal interruption duration parameter;
Detect whether mistake of sync byte, and error rate parameter wrong according to sync byte, the wrong wrong timing parameter of sync byte, whether sync byte is misrepresented deliberately alert delay parameter and is determined to exist and need the fault switched;
Whether the detected transmission bag mistake, and according to the wrong error rate parameter of transmission, transmit wrong wrong timing parameter, and transmission is misrepresented deliberately alert delay parameter and determined whether there is the fault that needs switching;
Whether extremely, detect the PID code check, and according to PID code check lower limit parameter, PID limit bit rate parameter, PID code check abnormal alarm delay parameter determines whether there is the fault that needs switching.
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