CN102237872A - Lock detector, method thereof, and phase locked loop using lock detector - Google Patents
Lock detector, method thereof, and phase locked loop using lock detector Download PDFInfo
- Publication number
- CN102237872A CN102237872A CN2010101693841A CN201010169384A CN102237872A CN 102237872 A CN102237872 A CN 102237872A CN 2010101693841 A CN2010101693841 A CN 2010101693841A CN 201010169384 A CN201010169384 A CN 201010169384A CN 102237872 A CN102237872 A CN 102237872A
- Authority
- CN
- China
- Prior art keywords
- pulse
- pulse wave
- phase
- wave
- bandwidth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a lock detector for a phase locked loop. The lock detector comprises a first pulse width increasing unit, a second pulse width increasing unit, a first delay circuit, a second delay circuit and an interleaved sampling circuit, wherein the first and second pulse width increasing units perform pulse width increasing on a first pulse and a second pulse to form a third pulse and a fourth pulse respectively; the first and second delay circuits delay the third and fourth pulses to form a first sampling time pulse and a second sampling time pulse respectively; and the interleaved sampling circuit samples the third pulse according to the second sampling time pulse, and samples the fourth pulse according to the first sampling time pulse to indicate whether the phase locked loop is in a locked state or not.
Description
[technical field]
The invention relates to a kind of pinning detector and its method, with the phase-locked loop (PLL that uses it, Phase Lock Loop), and particularly relevant for a kind of pinning detector and its method that can indicate whether to be in locking-in state, with the phase-locked loop of using it.
[background technology]
In the clock pulse generator framework, bound phase-locked loop.The phase-locked loop can be used for the accurate control of clock pulse or frequency.Such as the frequency tuning of radio wave or the clock pulse of digital product control all can use PLL to come the design frequency control loop, to simplify the complexity of circuit, increases accuracy.
Existing phase-locked loop is to utilize the pinning detector (lock detector) of simulating to indicate the operating state of phase-locked loop in principle: pin (locked) state or pin (unlocked) state.Yet simulation is pinned detector and can be occupied big circuit area and consume high power.Certainly, existing also the development numeral pinning detector.But, existing analog/digital pins detector and all can't define locking-in state (lock state) accurately.
[summary of the invention]
The digital pinning detector of the embodiment of the invention can precisely define locking-in state; That is, can be quantitatively (quantitatively) and the qualitative locking-in state that defines (qualitatively).And, dynamically design locking-in state.
An example of the present invention proposes a kind of state detector, is applied in the phase-locked loop.State detector comprises: one first and one second pulse bandwidth extension unit, carry out the pulse bandwidth prolongation to one first pulse wave and one second pulse wave respectively, to become one the 3rd pulse wave and one the 4th pulse wave; One first and one second delay circuit postpones to become one first sampling clock pulse and one second sampling clock pulse with the 3rd pulse wave and the 4th pulse wave respectively; And one intersect sample circuit, according to this second sampling clock pulse the 3rd pulse wave of taking a sample, and according to this first sampling clock pulse the 4th pulse wave of taking a sample, indicates this phase-locked loop whether to be in a locking-in state.
Another example of the present invention provides a kind of phase-locked loop, comprising: a phase/frequency detector, relatively and detect one with reference to clock pulse and one output clock pulse, to export one first pulse wave and one second pulse wave; Whether one pins detector, is coupled to this phase/frequency detector, according to this first pulse wave this second pulse wave of taking a sample, and according to this second pulse wave this first pulse wave of taking a sample, be pinning to indicate this phase-locked loop; One charge pump is coupled to this phase/frequency detector, with this first with this second pulse wave be converted to one control voltage; And a voltage-controlled oscillator, be coupled to this charge pump, produce this output clock pulse according to this control voltage.
Whether another example again of the present invention provides a kind of pinning detection method, pin to one with reference to clock pulse in order to detect an output clock pulse.This method comprises: relatively and detect this with reference to clock pulse and this output clock pulse, and to export one first pulse wave and one second pulse wave; Prolong a pulse bandwidth of this first pulse wave, to become one the 3rd pulse wave; Prolong a pulse bandwidth of the two or two pulse wave, to become one the 4th pulse wave; Postpone the 3rd pulse wave, to become one first sampling clock pulse; Postpone the 4th pulse wave, to become one second sampling clock pulse; And, according to this second sampling clock pulse the 3rd pulse wave of taking a sample, and according to this first sampling clock pulse the 4th pulse wave of taking a sample, with indicate this output clock pulse whether pin to this with reference to clock pulse.
For foregoing of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
[description of drawings]
Fig. 1 shows the functional block diagram according to the phase-locked loop of the embodiment of the invention.
Fig. 2 shows the functional block diagram of phase/frequency detector.
Fig. 3 show when be in reference to clock pulse CLKREF and feedback clock pulse CLKFB that phase place is located and frequency localization under pulse wave UP and the oscillogram of DN.
Waveform amplification figure when Fig. 4 demonstrates and is in the location with reference to clock pulse CLKREF and feedback clock pulse CLKFB.
Fig. 5 A shows the oscillogram of the pulse wave UP/DN under the positioning states.
Fig. 5 B shows the oscillogram of the pulse wave UP/DN of (feedback clock pulse CLKFB is for falling behind (behind)) under the no-fix state.
Fig. 5 C shows the oscillogram of the pulse wave UP/DN of (feedback clock pulse CLKFB is leading (ahead)) under the no-fix state.
Fig. 6 shows the functional block diagram according to the pinning detector of the embodiment of the invention.
Fig. 7 A shows the example according to the pulse bandwidth extension unit of the embodiment of the invention.
Fig. 7 B shows the oscillogram according to the pulse wave UP of the embodiment of the invention and pulse wave UPE (pulse bandwidth prolongs the back).
Fig. 8 shows the example according to the delay circuit of present embodiment.
Fig. 9 shows the example according to pulse wave UP, UPE and the sampling clock signal DN_CLK of the embodiment of the invention.
Figure 10 shows that PLL is in the signal waveforms of locking-in state.
[primary clustering symbol description]
100: phase-locked loop 110: phase/frequency detector
120: pin detector 130: charge pump
140: voltage-controlled oscillator 150: frequency eliminator
210_1,210_2: bolt lock device 220,710,810: delay cell
230,640,720: logic gate 410: uncertain region
610_1,610_2: pulse bandwidth extension unit
620_1,620_2: delay circuit 630_1,630_2: bolt lock device
[embodiment]
Now please refer to Fig. 1, it shows the functional block diagram according to the phase-locked loop of the embodiment of the invention.As shown in Figure 1, phase-locked loop 100 comprises: phase/frequency detector (Phase/FrequencyDetector, PFD) 110, pin detector 120, charge pump (charge pump) 130, voltage-controlled oscillator (Voltage Controlled Oscillator, VCO) 140 with frequency eliminator 150.
Phase/frequency detector 110 can be relatively with reference to clock pulse CLKREF and feedback clock pulse CLKFB, to detect phase difference amount and frequency difference amount between the two.When the frequency of reference clock pulse CLKREF is higher than the frequency of feedback clock pulse CLKFB, PFD output UP pulse wave.When if the anti-frequency with reference to clock pulse CLKREF is lower than the frequency of feedback clock pulse CLKFB, PFD output DN pulse wave.The UP/DN pulse wave signal that phase/frequency detector 110 produces is converted into control voltage via charge pump (also can be described as current controller) 130.This control voltage can be controlled voltage-controlled oscillator 140, to produce output clock pulse CLKOUT.
If output clock pulse CLKOUT directly becomes feedback clock pulse CLKFB (not passing through frequency eliminator), then be " phase-lock loop ", output clock pulse CLKOUT locking makes and exports clock pulse CLKOUT and keep locking phase and frequency state with reference to clock pulse CLKREF with reference to clock pulse CLKREF.
If output clock pulse CLKOUT just becomes feedback clock pulse CLKFB through behind the frequency elimination of frequency eliminator 150, when PLL is in the steady lock state, the frequency of two inputs of PFD should be with phase place and equates, so CLKOUT/M=CLKREF, wherein M is the frequency elimination multiple of frequency eliminator.
Fig. 2 shows the functional block diagram of phase/frequency detector 110.As shown in Figure 2, phase/frequency detector 110 comprises: bolt lock device (flip-flop, FF) 210_1 and 210_2, delay cell 220 and NAND gate (NAND Gate) 230.The delay time parameter of NAND gate 230 is t1; The delay time parameter of delay cell 220 is t2; And the delay time parameter of bolt lock device 210_1 and 210_2 is t3.Fig. 3 shows when be in phase place with reference to clock pulse CLKREF and feedback clock pulse CLKFB and locatees pulse wave UP under (phase alignment) and the frequency localization (frequency alignment) and the oscillogram of DN.
Waveform amplification figure when Fig. 4 demonstrates and is in location (alignment) with reference to clock pulse CLKREF and feedback clock pulse CLKFB.As seen from Figure 4, when (1) is close with reference to the appearance sequential of rising/drop edge of the rising/drop edge of clock pulse CLKREF and feedback clock pulse CLKFB and (2) with reference to the frequency of the frequency of clock pulse CLKREF and feedback clock pulse CLKFB when roughly close (that is,
), promptly can be considered with reference to clock pulse CLKREF and feedback clock pulse CLKFB and be in the location.
More can find out by Fig. 4, even will be considered as being in positioning states with reference to clock pulse CLKREF and feedback clock pulse CLKFB.But the appearance sequential with reference to rising/drop edge of the rising/drop edge of clock pulse CLKREF and feedback clock pulse CLKFB still falls within the uncertain region, shown in the symbol 410 of Fig. 4.This uncertain region may be influenced by many factors that circuit is real to be done.So, in present embodiment,, can more clearly define the pinning operating state by pinning detector 120, influenced by the bad factor avoiding.
Fig. 5 A demonstrates when the oscillogram that is in the pulse wave UP/DN under the positioning states.Can find out that by Fig. 5 A under this state, pulse wave UP equates (tpulse=t1+t2+t3) basically with the pulsewidth of pulse wave DN.Fig. 5 B demonstrates when the oscillogram that is in the pulse wave UP/DN of (feedback clock pulse CLKFB is for falling behind (behind)) under the no-fix state.Can find out that by Fig. 5 B under this state, the pulsewidth tpulse of pulse wave UP and pulse wave DN is unequal basically.Fig. 5 C demonstrates when the oscillogram that is in the pulse wave UP/DN of (feedback clock pulse CLKFB is leading (ahead)) under the no-fix state.Can find out that by Fig. 5 C under this state, the pulsewidth tpulse of pulse wave UP and pulse wave DN is unequal basically.
At this, " location " is to refer to that frequency and phase place between two signals (as CLKREF and CLKFB) are close, that is " location " be qualitative definition just.But " pinning " then is quantitative analysis, that is it can spell out phase difference between two signals and drops on earth how in the scope.
In the present embodiment, pin detector 120 pulse wave UP is treated as sampling clock pulse and sampled data, and pulse wave DN is treated as sampling clock pulse and sampled data.Furtherly, pin detector 120 according to the pulse wave DN pulse wave UP that takes a sample; And according to the pulse wave UP pulse wave DN that takes a sample.
Fig. 6 shows the functional block diagram according to the pinning detector of the embodiment of the invention.As shown in Figure 6, pinning detector 120 according to the embodiment of the invention comprises: pulse bandwidth extension unit (pulse widthextender) 610_1 and 610_2, delay circuit 620_1 and 620_2, bolt lock device (flip-flop) 630_1 and 630_2 and logic gate 640.When whether detection PLL pins, pin detector 120 and can carry out: prolong pulse bandwidth, delay and the sampling that intersects pulse wave UP and DN.Beneath each function square that pinning detector 120 will be described respectively.Logic gate 640 is for reaching logic gate.
Fig. 7 A shows the example according to the pulse bandwidth extension unit 610 of the embodiment of the invention.Shown in Fig. 7 A, pulse bandwidth extension unit 610 comprises N delay cell 710 and logic gate 720.Delay cell 710 has same delay time parameter t2 with the delay cell 220 of Fig. 2.Logic gate 720 is or logic (logic OR) grid.Pulse bandwidth extension unit 610 can be as pulse bandwidth extension unit 610_1 and the 610_2 among Fig. 6.
Fig. 7 B shows the oscillogram of pulse wave UP and pulse wave UPE (pulse bandwidth prolongs the back).By Fig. 7 A and Fig. 7 B as can be known, the pulse bandwidth of pulse wave UP is t1+t2+t3 originally; After the pulse bandwidth prolongation, the pulse bandwidth of pulse wave UPE is N*t2.And pulse wave UPE does not have surging (glitch), because the pulse bandwidth of (1) pulse wave UP is t1+t2+t3; (2) all be t2 the time of delay of each delay cell; (3) output signal of those delay cells is carried out the logic OR computing.For pulse wave UPE/DNE, it is very important not having surging.The purpose of pulse bandwidth extension unit 610 is that (1) makes that the pulse bandwidth N*t2 of output pulse wave UPE is known (because N and t2 are all known); And (2) compared to original pulse wave UP and DN, the pulse bandwidth broad of pulse wave UPE and DNE, so, when bolt lock device FF when carrying out bolt-lock, can carry out bolt-lock to pulse wave UPE and DNE than no problem ground.
Fig. 8 shows the example according to the delay circuit 620 of present embodiment.Delay circuit 620 can be used for delay circuit 620_1 and the 620_2 of Fig. 6.As shown in Figure 8, delay circuit 620 comprises N/2 delay cell 810.Delay cell 810 has same delay time parameter t2 with the delay cell 220 of Fig. 2.Delay circuit 620_1 postpones to be sampling clock signal DN_CLK with pulse wave UPE, in order to sampling pulse wave DN (say exactly, should be used to take a sample pulse wave DNE).Fig. 9 shows the example according to pulse wave UP, UPE and the sampling clock signal DN_CLK of the embodiment of the invention.
As shown in Figure 6, as bolt lock device 630_1 and 630_2 all during output logic 1, pin signal L and just can be logical one.When pinning signal L is logical one, represent PLL to be in locking-in state.
Figure 10 shows that PLL is in the signal waveforms of locking-in state.The first half of Figure 10 is represented the situation of bolt lock device 630_1 output logic 1; The Lower Half of Figure 10 is represented the situation of bolt lock device 630_2 output logic 1.Furtherly, when time difference between the rising edge (or drop edge) of the rising edge (or drop edge) of pulse wave UP and pulse wave DN during, represent PLL to be in locking-in state less than (N/2) * t2; Otherwise,, represent PLL not to be in locking-in state as yet when time difference between the rising edge (or drop edge) of the rising edge (or drop edge) of pulse wave UP and pulse wave DN during greater than (N/2) * t2.Furtherly, in embodiments of the present invention,, represent PLL to be in locking-in state when time difference between the rising edge (or drop edge) of the rising edge (or drop edge) of reference clock pulse CLKREF and feedback clock pulse CLKFB during less than (N/2) * t 2.So hence one can see that, the embodiment of the invention not only can define " locking-in state " qualitatively more can define " locking-in state " quantitatively.
And in embodiments of the present invention, the visual demand of locking-in state and dynamically changing get final product by changing N value, that is, in embodiments of the present invention, can change the sensitivity of pinning detector by change N value.When the N value more hour, the sensitivity of pinning detector is higher, because make the pinning detector be in locking-in state with reference to the little ability that must heal of the time difference between the rising edge (or drop edge) of the rising edge (or drop edge) of clock pulse CLKREF and feedback clock pulse CLKFB.Anti-is as the same.
Disclosed digital pinning detector of the above embodiment of the present invention and the phase-locked loop of using it have multiple advantages, below only enumerate the part advantage and are described as follows:
The digital pinning detector of the embodiment of the invention can precisely define locking-in state, and, dynamically design locking-in state.In addition, the digital pinning detector of the embodiment of the invention occupies small circuit area occupied, and consumed power is low.The sensitivity of pinning detector dynamically designs.
In sum, though the present invention discloses as above with embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (15)
1. a state detector is applied in the phase-locked loop, and this state detector comprises:
One first and one second pulse bandwidth extension unit carries out the pulse bandwidth prolongation to one first pulse wave and one second pulse wave respectively, to become one the 3rd pulse wave and one the 4th pulse wave;
One first and one second delay circuit postpones to become one first sampling clock pulse and one second sampling clock pulse with the 3rd pulse wave and the 4th pulse wave respectively; And
One intersects sample circuit, according to this second sampling clock pulse the 3rd pulse wave of taking a sample, and according to this first sampling clock pulse the 4th pulse wave of taking a sample, whether is in a locking-in state to indicate this phase-locked loop.
2. state detector according to claim 1 is characterized in that, the pulse bandwidth of the 3rd pulse wave and the 4th pulse wave is known.
3. state detector according to claim 2 is characterized in that:
This first delay circuit is to time of delay of the 3rd pulse wave being half of this pulse bandwidth of the 3rd pulse wave; And
This second delay circuit is to time of delay of the 4th pulse wave being half of this pulse bandwidth of the 4th pulse wave.
4. state detector according to claim 2 is characterized in that, this intersection sample circuit comprises:
One first latch circuit is according to this second sampling clock pulse the 3rd pulse wave of taking a sample;
One second latch circuit is according to this first sampling clock pulse the 4th pulse wave of taking a sample; And
One logical circuit, receive this first with the output of this second latch circuit, whether this phase-locked loop of output indication of this logical circuit is in this locking-in state.
5. state detector according to claim 2, it is characterized in that, phase difference when between this first pulse wave and this second pulse wave less than this pulse bandwidth of the 3rd pulse wave half or less than a half of this pulse bandwidth of the 4th pulse wave, this intersection sampling result indicates this phase-locked loop to be in this locking-in state.
6. phase-locked loop comprises:
One phase/frequency detector, relatively and detect one with reference to clock pulse and one output clock pulse, to export one first pulse wave and one second pulse wave;
Whether one pins detector, is coupled to this phase/frequency detector, according to this first pulse wave this second pulse wave of taking a sample, and according to this second pulse wave this first pulse wave of taking a sample, be pinning to indicate this phase-locked loop;
One charge pump is coupled to this phase/frequency detector, with this first with this second pulse wave be converted to one control voltage; And
One voltage-controlled oscillator is coupled to this charge pump, produces this output clock pulse according to this control voltage.
7. phase-locked loop according to claim 6 is characterized in that, this pinning detector comprises:
One first and one second pulse bandwidth extension unit carries out the pulse bandwidth prolongation to this first pulse wave and this second pulse wave respectively, to become one the 3rd pulse wave and one the 4th pulse wave;
One first and one second delay circuit postpones to become one first sampling clock pulse and one second sampling clock pulse with the 3rd pulse wave and the 4th pulse wave respectively; And
One intersects sample circuit, according to this second sampling clock pulse the 3rd pulse wave of taking a sample, and according to this first sampling clock pulse the 4th pulse wave of taking a sample, and intersects sampling result according to one and indicates this phase-locked loop whether to be in a locking-in state.
8. phase-locked loop according to claim 7 is characterized in that, the pulse bandwidth of the 3rd pulse wave and the 4th pulse wave is known.
9. phase-locked loop according to claim 7 is characterized in that:
This first delay circuit is to time of delay of the 3rd pulse wave being half of this pulse bandwidth of the 3rd pulse wave; And
This second delay circuit is to time of delay of the 4th pulse wave being half of this pulse bandwidth of the 4th pulse wave.
10. phase-locked loop according to claim 7 is characterized in that, this intersection sample circuit comprises:
One first latch circuit is according to this second sampling clock pulse the 3rd pulse wave of taking a sample;
One second latch circuit is according to this first sampling clock pulse the 4th pulse wave of taking a sample; And
One logical circuit, receive this first with the output of this second latch circuit, whether this phase-locked loop of output indication of this logical circuit is in this locking-in state.
11. phase-locked loop according to claim 7, it is characterized in that, phase difference when between this first pulse wave and this second pulse wave less than this pulse bandwidth of the 3rd pulse wave half or less than a half of this pulse bandwidth of the 4th pulse wave, this intersection sampling result indicates this phase-locked loop to be in this locking-in state.
12. whether one kind is pinned detection method, pin to one with reference to clock pulse in order to detect an output clock pulse, this method comprises:
Relatively and detect this, to export one first pulse wave and one second pulse wave with reference to clock pulse and this output clock pulse;
Prolong a pulse bandwidth of this first pulse wave, to become one the 3rd pulse wave;
Prolong a pulse bandwidth of this second pulse wave, to become one the 4th pulse wave;
Postpone the 3rd pulse wave, to become one first sampling clock pulse;
Postpone the 4th pulse wave, to become one second sampling clock pulse; And
According to this second sampling clock pulse the 3rd pulse wave of taking a sample, and according to this first sampling clock pulse the 4th pulse wave of taking a sample, with indicate this output clock pulse whether pin to this with reference to clock pulse.
13. method according to claim 12 is characterized in that, the pulse bandwidth of the 3rd pulse wave and the 4th pulse wave is known.
14. method according to claim 13 is characterized in that:
According to this pulse bandwidth of the 3rd pulse wave half, postponing the 3rd pulse wave becomes this first sampling clock pulse; And
According to this pulse bandwidth of the 4th pulse wave half, postponing the 4th pulse wave becomes this second sampling clock pulse.
15. method according to claim 13, it is characterized in that, phase difference when between this first pulse wave and this second pulse wave is less than half of this pulse bandwidth of the 3rd pulse wave or less than a half of this pulse bandwidth of the 4th pulse wave, represent this output clock pulse pin to this with reference to clock pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010169384.1A CN102237872B (en) | 2010-04-26 | 2010-04-26 | Pin detector and its method, with its phase-locked loop of application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010169384.1A CN102237872B (en) | 2010-04-26 | 2010-04-26 | Pin detector and its method, with its phase-locked loop of application |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102237872A true CN102237872A (en) | 2011-11-09 |
| CN102237872B CN102237872B (en) | 2016-08-03 |
Family
ID=44888170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010169384.1A Active CN102237872B (en) | 2010-04-26 | 2010-04-26 | Pin detector and its method, with its phase-locked loop of application |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102237872B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103918184A (en) * | 2011-11-14 | 2014-07-09 | 德州仪器公司 | Delay locked loop |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668498A (en) * | 1996-05-13 | 1997-09-16 | Zenith Electronics Corporation | Controlling FPLL polarity using pilot signal and polarity inverter |
| US6239632B1 (en) * | 1999-09-17 | 2001-05-29 | Cypress Semiconductor Corp. | Method, architecture and/or circuitry for controlling the pulse width in a phase and/or frequency detector |
| CN1509518A (en) * | 2001-05-14 | 2004-06-30 | 索尼电脑娱乐公司 | Apparatus/method for distributing clock signal |
| CN101588177A (en) * | 2009-06-22 | 2009-11-25 | 中国科学院微电子研究所 | Digital locking indictor, phase lock loop frequency synthesizer and wireless transceiver |
-
2010
- 2010-04-26 CN CN201010169384.1A patent/CN102237872B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668498A (en) * | 1996-05-13 | 1997-09-16 | Zenith Electronics Corporation | Controlling FPLL polarity using pilot signal and polarity inverter |
| US6239632B1 (en) * | 1999-09-17 | 2001-05-29 | Cypress Semiconductor Corp. | Method, architecture and/or circuitry for controlling the pulse width in a phase and/or frequency detector |
| CN1509518A (en) * | 2001-05-14 | 2004-06-30 | 索尼电脑娱乐公司 | Apparatus/method for distributing clock signal |
| CN101588177A (en) * | 2009-06-22 | 2009-11-25 | 中国科学院微电子研究所 | Digital locking indictor, phase lock loop frequency synthesizer and wireless transceiver |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103918184A (en) * | 2011-11-14 | 2014-07-09 | 德州仪器公司 | Delay locked loop |
| CN103918184B (en) * | 2011-11-14 | 2017-09-22 | 德州仪器公司 | Delay locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102237872B (en) | 2016-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102811053B (en) | Circuit and method for preventing false lock and delay locked loop using the same | |
| KR100380968B1 (en) | Zero-delay buffer circuit for a spread spectrum clock system and method therefor | |
| US8258834B2 (en) | Lock detector, method applicable thereto, and phase lock loop applying the same | |
| US20120319734A1 (en) | System and method for reducing power consumption in a phased-locked loop circuit | |
| US8401140B2 (en) | Phase/frequency detector for a phase-locked loop that samples on both rising and falling edges of a reference signal | |
| CN101494457B (en) | Delay locked loop circuit and method for eliminating jitter and offset therein | |
| US20030112913A1 (en) | Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal | |
| CN105959001B (en) | Become frequency domain all-digital phase-locked loop and locking phase control method | |
| CN102857222B (en) | A kind of dynamic adjusting method of system clock and circuit | |
| CN102237872B (en) | Pin detector and its method, with its phase-locked loop of application | |
| WO2006017368A2 (en) | An enhanced phase and frequency detector that improves performance in the presence of a failing clock | |
| US6990165B2 (en) | Phase and frequency lock detector | |
| US7664213B2 (en) | Clock alignment detection from single reference | |
| CN205039800U (en) | Time digital conversion circuit with sluggish function | |
| CN110166045B (en) | Snapshot circuit for extracting signal change edge | |
| Xia et al. | All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops | |
| US6937069B2 (en) | System and method for dead-band determination for rotational frequency detectors | |
| CN208046591U (en) | A kind of lock detecting circuit | |
| CN105262479B (en) | A kind of time-to-digital conversion circuit with lag function | |
| CN104917517A (en) | Energy-saving circuit for realizing low-power-consumption wide-measuring-range time-to-digital converter | |
| Ravi et al. | A new architecture of the phase frequency detector with improved gain and minimal blind zone for fast settling PLLs | |
| CN118018011B (en) | Locking detection circuit of adjustable delay phase-locked loop | |
| Foley et al. | A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5/spl mu/m CMOS | |
| CN112152596B (en) | Circuit and method for generating pulse output | |
| CN101521508B (en) | Multi-loop phase-locked loop device and phase-locked method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |