CN102237364A - Storage device and manufacturing method thereof - Google Patents
Storage device and manufacturing method thereof Download PDFInfo
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- CN102237364A CN102237364A CN201010157573.7A CN201010157573A CN102237364A CN 102237364 A CN102237364 A CN 102237364A CN 201010157573 A CN201010157573 A CN 201010157573A CN 102237364 A CN102237364 A CN 102237364A
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention discloses a storage device and a manufacturing method thereof. The storage device comprises an MOSFET (metal oxide semiconductor field effect transistor) formed in a semiconductor layer and a capacitor structure below the MOSFET, the capacitor structure comprises two capacitor electrodes, one of a source region and a drain region of the MOSFET is electrically connected with one of the two capacitor electrodes, wherein the capacitor structure comprises multiple first stacked capacitors and multiple second stacked capacitors in an alternatively stacked mode, each first stacked capacitor comprises a top plate, a bottom plate and a dielectric layer sandwiched between the top plate and the bottom plate, each multiple second stacked capacitor also comprises a top plate, a bottom plate and a dielectric layer sandwiched between the top plate and the bottom plate, the multiple first stacked capacitors and the multiple second stacked capacitors are connected in parallel through the two capacitor electrodes, the bottom plate of each first stacked capacitor and the top plate of the second stacked capacitor below the bottom plate are formed by a common first electrode layer, the bottom plate of each second stacked capacitor and the top plate of the first stacked capacitor below the bottom plate is formed by a common second electrode layer, wherein the first electrode layers and the second electrode layers are made of different conducting materials.
Description
Technical field
The present invention relates to a kind of memory device and manufacture method thereof, relate more specifically to a kind of embedded memory device and manufacture method thereof that comprises integrated capacitor.
Background technology
Such as applications such as mobile phones, the in-line memory (as eDRAM) that comprises integrated capacitor has obtained using widely owing to possessing small size and advantage of low power consumption.In eDRAM, the electric capacity of memory cell is the key parameter of decision retention time (retention time).In order to obtain the long retention time, the capacitance of memory cell should be big as far as possible.Yet this will require integrated large-sized capacitor on chip, thereby cause the integrated level of memory cell to reduce.
The eDRAM unit of the deep trench capacitor that forms in the substrate has been proposed to be included in people's such as Wang Geng U.S. Patent application No.US20090174031A1.The sidewall of deep trouth provides main pole plate area, thereby has reduced the area occupied (footprint) of substrate surface, still can obtain bigger capacitance simultaneously.
Yet, adopt the eDRAM unit of deep trench capacitor to exist many technologic difficulties, for example, because deep trouth has high aspect ratio (aspect ratio), in being used to form the reactive ion etching of groove (RIE) step, need long etching period, and, defectives such as hole may appear in filling step subsequently.As a result, the manufacturing cost of the eDRAM unit of employing deep trench capacitor is higher, and reliability is relatively poor.
On the other hand, because the difficulty of above-mentioned technology has limited the degree of depth of the groove that can form, the capacitance that is obtained may be too small and be not enough to make that the eDRAM unit obtains the desirable retention time.
Summary of the invention
The memory device and the manufacture method thereof that the purpose of this invention is to provide a kind of high integration, high reliability, high retention time.
According to an aspect of the present invention, a kind of memory device is provided, be included in the MOSFET that forms in the semiconductor layer, and the capacitor arrangement that is positioned at the MOSFET below, described capacitor arrangement comprises two electrode for capacitors, one of the source region of described MOSFET and drain region are electrically connected with one of described two electrode for capacitors, wherein, described capacitor arrangement comprises a plurality of first stacked capacitors and a plurality of second stacked capacitor that alternately piles up, described a plurality of first stacked capacitor and described a plurality of second stacked capacitor comprise top crown separately, bottom crown and be clipped in dielectric between the two, and be connected in parallel by described two electrode for capacitors, and the bottom crown of each in described a plurality of first stacked capacitor is formed by the first public electrode layer with the top crown of second stacked capacitor that is positioned at its below, the bottom crown of each in described a plurality of second stacked capacitor is formed by public the second electrode lay with the top crown of first stacked capacitor that is positioned at its below, and described first electrode layer is made up of different electric conducting materials with described the second electrode lay.
According to a further aspect in the invention, a kind of method of making capacitor arrangement is provided, may further comprise the steps: a) on Semiconductor substrate, alternately deposit first dielectric layer, first electrode layer, second dielectric layer and the second electrode lay, to form sandwich construction, described Semiconductor substrate comprises base substrate, sacrifice layer and top semiconductor layer; B) etching is carried out in first side of described sandwich construction, wherein with respect to first electrode layer, first dielectric layer, second dielectric layer, the part that the selective removal the second electrode lay exposes on first side, thus on described first side, stay depression; C) etching is carried out in second side of described sandwich construction, wherein with respect to the second electrode lay, first dielectric layer, second dielectric layer, the part that selective removal first electrode layer exposes on second side, thus on described second side, stay depression; D) cover layer of deposition of insulative material on described sandwich construction; E) in described cover layer, form the opening that exposes described first side and described second side, wherein stay described insulating material in the depression on first side and second side; F) filled conductive material in described opening forms respectively two electrode for capacitors that directly contact with all first electrode layers and all the second electrode lays; G) the upset Semiconductor substrate is removed base substrate and sacrifice layer; H) source region, drain region and the channel region between source region and drain region of formation MOSFET in the described top semiconductor layer of Semiconductor substrate, wherein one of the source region of MOSFET and drain region are electrically connected with one of described two electrode for capacitors; And i) above the channel region of MOSFET, forms gate-dielectric and grid conductor.
In memory device of the present invention, because capacitor arrangement comprises a plurality of stacked capacitors of piling up and it is connected in parallel, so the chip area footprints of this capacitor arrangement is less and capacitance is bigger, thereby can realize high integration and required retention time.
And because first electrode layer is made up of different materials with the second electrode lay, so this capacitor arrangement can utilize the etching step formation of wherein using mask, thereby can adopt known integrated circuit technology to make.
In addition, by changing the quantity of the lamination in the sandwich construction, can easily change the capacitance of capacitor.Therefore, this memory device also provides better design freedom.Owing to not needing to form the groove of high aspect ratio and it is filled in the mill, therefore in this memory device, there is not the defective of introducing owing to filling step, thereby improved reliability.
Description of drawings
Fig. 1-14 illustrates the method according to this invention, is used to form the memory device structures in each stage of the capacitor arrangement in the memory device.
Figure 15-16 illustrates the method according to this invention, is used to form the memory device structures in each stage of the MOSFET (mos field effect transistor) in the memory device.
Embodiment
Hereinafter with reference to accompanying drawing the present invention is described in more detail.In each accompanying drawing, components identical adopts similar Reference numeral to represent.For the sake of clarity, the various piece in the accompanying drawing is not drawn in proportion.
Be to be understood that, when the structure of outlines device, when one deck, zone are called be positioned at another layer, another zone " above " or when " top ", can refer to be located immediately at another layer, another is above zone, perhaps its and another layer, also comprise other layer or regional between another zone.And if with the device upset, this one deck, a zone will be positioned at another layer, another zone " following " or " below ".
If for describe be located immediately at another layer, another the zone above situation, this paper will adopt " directly existing ... top " or " ... top and with it the adjacency " form of presentation.
Described many specific details of the present invention hereinafter, for example structure of device, material, size, treatment process and technology are so that more be expressly understood the present invention.But such just as the skilled person will understand, can realize the present invention not according to these specific details.
According to the preferential embodiment of method of the present invention, the step that is used to form capacitor arrangement shown in the execution graph 1 to 14 successively.
Referring to Fig. 1, method of the present invention starts from SOI (i.e. " semiconductor-on-insulator ") wafer.The SOI wafer comprises base substrate 11, buried insulator layer (BOX) 12 and top semiconductor layer 13.Top semiconductor layer 13 for example comprise IV family semiconductor (as, silicon or germanium) and III family-IV family semiconductor (as, GaAs).
Instead, also can adopt the body silicon substrate, to replace above-mentioned base substrate 11, on the body silicon substrate, form epitaxy Si Ge layer then, to replace above-mentioned buried insulator layer 12, on the SiGe layer, form epitaxial semiconductor layer, to replace above-mentioned top semiconductor layer 13.In the present invention, buried insulator layer 12 and the SiGe layer that replaces are used at following Fig. 6 A and the step effect etching stopping layer shown in the 6B, and in following step shown in Figure 15 as sacrifice layer.
Referring to Fig. 2, by known depositing operation, as PVD, CVD, ald, sputter etc., deposited oxide layer 14 on the top semiconductor layer 13 of SOI wafer will be as interlayer insulating film in the final memory device that forms.
Referring to Fig. 3, by wherein using the etch process of photoresist mask, form opening 15 through patterning in the top semiconductor layer 13 (hereinafter referred to as " soi semiconductor layer ") of SOI wafer and above-mentioned oxide skin(coating) 14, this will be with the via hole that connects MOS transistor and capacitor (via hole) in the final memory device that forms.
This patterning can may further comprise the steps: by the photoetching process that comprises exposure and develop, form the photoresist mask that contains pattern on oxide skin(coating) 14; Pass through dry etching, as ion beam milling etching, plasma etching, reactive ion etching, laser ablation, perhaps by wherein using the wet etching of etchant solutions, remove the expose portion of soi semiconductor layer 13 and above-mentioned oxide skin(coating) 14, this etching step stops at the top of buried oxide layer 12; Remove the photoresist mask by dissolving or ashing in solvent.
Referring to Fig. 4, the highly doped conductive polycrystalline silicon floor 16 of deposition carries out chemical-mechanical planarization (CMP) then on the memory device structures that above-mentioned steps obtains, to obtain the flat surface of memory device structures.Polysilicon layer 16 has been filled opening 15, and at the bottom of opening 15 sidewalls contact soi semiconductor layer 13.Through after the complanation, polysilicon layer 16 is approximately 5～20nm at the thickness of the over top of oxide skin(coating) 14.
Referring to Fig. 5, by known depositing operation, as PVD, CVD, ald, sputter etc., alternating deposit first dielectric layer 21, first electrode layer 22, second dielectric layer 23 and the second electrode lay 24 above polysilicon layer 16, thereby form the sandwich construction of the lamination 20 of repeatedly stacking, wherein lamination 20 comprises first dielectric layer 21, first electrode layer 22, second dielectric layer 23 and the second electrode lay 24.
Aspect the designs of memory, the area constraints that each memory cell occupies the area of plane of capacitor.As mentioned below, the lamination 20 of repeatedly stacking has formed a plurality of capacitors that are connected in parallel in the capacitor arrangement of the present invention, thereby can adopt the area occupied that reduces that the capacitance of expectation is provided.
The minimum area occupied of first electrode layer 22 and the second electrode lay 24 only is decided by technological level.Memory cell
At the capacitance of expectation, the parameter that can change comprises the material and the thickness of area, first dielectric layer 21 and second dielectric layer 23 of first electrode layer 22 and the second electrode lay 24, and the quantity of lamination 20.For example, the thickness of lamination 20 is about 20～40nm, and the quantity of lamination 20 is approximately 10～1000 layers.
As described below, first electrode layer 22 should be made of the material that shows different etching speeds in etching step with the second electrode lay 24, and preferably, first electrode layer 22 is TiN, and the second electrode lay 24 is a polysilicon.
First dielectric layer 21 and second dielectric layer 23 can be made of identical or different dielectric substance, for example comprise oxide, nitride, oxynitride, silicate, aluminate, titanate, and wherein, oxide for example comprises SiO
2, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, nitride for example comprises Si
3N
4, silicate for example comprises HfSiOx, aluminate for example comprises LaAlO
3, titanate for example comprises SrTiO
3, oxynitride for example comprises SiON.And dielectric substance not only can be a material known to those skilled in the art, and can adopt the material that is used for capacitor dielectric of exploitation in the future.
Referring to Fig. 6 A and 6B, by using the etch process of photoresist mask, sandwich construction, polysilicon layer 16, oxide skin(coating) 14 and soi semiconductor layer 13 form the rectangular area of each memory cell through patterning, wherein Fig. 6 A shows the vertical view of the memory device structures in this stage, and Fig. 6 B shows corresponding sectional view.This etch exposed the sidewall of sandwich construction, and stop at the top of buried insulator layer 12.
Instead, if use the body silicon substrate in step shown in Figure 1, then this etching stops at the top of epitaxy Si Ge layer.Then, remove the photoresist mask by dissolving or ashing in solvent.
Should be noted that and figure 6 illustrates two memory devices that separate by opening 26.In fact, on substrate, can repeat to form a plurality of memory devices in this way.In the following description, for the sake of clarity, the structure and the manufacture method thereof of a memory device in the left side that is positioned at opening 26 only described.
Referring to Fig. 7 A and 7B, form photoresist mask 31 by photoetching process, wherein Fig. 7 A shows the vertical view of the memory device structures in this stage, and Fig. 7 B shows corresponding sectional view.The side that this photoresist mask 31 exposes sandwich construction (promptly is arranged in the side of opening 25, hereinafter referred to as " first side "), and major part and another side (promptly being arranged in the side of opening 26) of covering the top surface of sandwich construction hereinafter referred to as " second side ".
Then,, for example wherein use the conventional wet etching of etchant solutions, with respect to first dielectric layer 21, first electrode layer 22, second dielectric layer 23, selective removal the second electrode lay 24 by isotropic etching.
Since the existence of photoresist mask 31, the second electrode lay 24 only on first side of sandwich construction to the degree of depth of its inner etched about 2～10nm, thereby on first side of sandwich construction, form depression.
In addition, if the second electrode lay 24 and polysilicon layer 16 are made of identical materials, then this step has also been removed the part (shown in Fig. 7 B) of polysilicon layer 16.
Then, remove the photoresist mask by dissolving or ashing in solvent.
Referring to Fig. 8 A and 8B, form photoresist mask 32 by photoetching process, wherein Fig. 8 A shows the vertical view of the memory device structures in this stage, and Fig. 8 B shows corresponding sectional view.This photoresist mask 32 exposes second side of sandwich construction, and covers the major part and first side of the top surface of sandwich construction.
Then,, for example wherein use the conventional wet etching of etchant solutions, with respect to first dielectric layer 21, second dielectric layer 23, the second electrode lay 24, the part of selective removal first electrode layer 22 by isotropic etching.
Since the existence of photoresist mask 32, first electrode layer 22 only on second side of sandwich construction to the degree of depth of its inner etched about 2～10nm, thereby on second side of sandwich construction, form depression.
Then, remove the photoresist mask by dissolving or ashing in solvent.
Referring to Fig. 9, by known depositing operation, as PVD, CVD, ald, sputter etc., depositing insulating layer 33 on sandwich construction, and this insulating barrier 33 is for example by SiO
2Constitute.The thickness of insulating barrier 33 is enough to cover sandwich construction, and passes through chemical mechanism complanation (CMP) subsequently and handle, thereby obtains even curface on sandwich construction.In this step with the top dielectric layer of sandwich construction as stopping layer, thereby also removed the second electrode lay 24 that is positioned on second dielectric layer 23.
Should be noted that insulating barrier 33 filled first side of sandwich construction and the depression in second side.
Referring to Figure 10, the part by etching removal insulating barrier 33 forms opening 27,28 again in the position of opening 25,26.
The etch process that is used to form opening is normally anisotropic, for example reactive ion etching (RIE).As mentioned above, first side of insulating barrier 33 filling multilayer structures and the depression on second side, therefore, in the step that forms opening 27,28, a part of insulating material that is arranged in depression remains.Wherein, the a part of insulating material that is arranged in the depression on first side of sandwich construction makes the first electrode electric insulation that the second electrode lay 24 and subsequently step will form, and the second electrode electric insulation that a part of insulating material that is arranged in the depression on second side of sandwich construction will form win electrode layer 22 and step subsequently.
The a part of insulating material that also keeps insulating barrier 33 in the bottom of opening 27,28.The control etched depth makes the top surface of insulating barrier 33 between the top surface and basal surface of oxide skin(coating) 14.This partial insulative layer 33 make first electrode that subsequently steps will form and second electrode and between the soi semiconductor layer 13 below the oxide skin(coating) 14 electric insulation, make this second electrode and between the polysilicon layer above the oxide skin(coating) 14 16, electrically contacting simultaneously.
Referring to Figure 11 A and 11B, around the rectangular area of each memory cell, form isolated side wall 35, wherein Figure 11 A shows the vertical view of the memory device structures in this stage, and Figure 11 B shows corresponding sectional view.
Can adopt the conventional method that is used to form the transistor gate sidewall to form isolated side wall 35.For example, at first form the SiN thin layer by methods such as LPCVD, ALD or PECVD, this SiN thin layer has the good sidewall coverage to the rectangular area.Then the SiN thin layer is carried out lateral etches, remove the SiN thin layer and be positioned at the top of rectangular area and part on every side, only stay the SiN thin layer and be positioned at part on the sidewall of rectangular area.
Then, 34 layers of parallel planes processing of going forward side by side of deposition oxide make oxide skin(coating) 34 fill isolated side wall 35 part on every side.
Referring to Figure 12 A and 12B, by wherein using the etch process of photoresist mask, in SiN isolated side wall 35, form capacitor openings 29,30 through patterning, wherein Figure 12 A shows the vertical view of memory device structures, and Figure 12 B shows corresponding sectional view.Capacitor openings 29,30 exposes first side and second side of sandwich construction respectively, and is positioned in the opening of above-mentioned lithography mask version 31,32, is used for forming in step subsequently first electrode and second electrode of capacitor.
This step and the step that is used to form opening 27,28 shown in Figure 10 are similar, have wherein used anisotropic etch process, for example reactive ion etching (RIE).
Referring to Figure 13, by known depositing operation, as PVD, CVD, ald, sputter etc., deposits conductive material in capacitor openings 29,30 (for example tungsten).
Electric conducting material in the capacitor openings 29 contacts with all first electrode layers 22 in the sandwich construction, thereby provide first electrode 35 of capacitor, and the electric conducting material in the capacitor openings 30 contacts with all the second electrode lays 24 in the sandwich construction, thereby second electrode 36 of capacitor is provided.
And the bottom of second electrode 36 of capacitor contacts with the polysilicon layer 16 that forms in step shown in Figure 4, thus polysilicon layer 16 provide from second electrode 36 of capacitor to step subsequently with the conductive path of the MOSFET that forms.
After deposits conductive material, the top dielectric layer of utilizing sandwich construction is carried out chemical-mechanical planarization (CMP) as stopping layer, to obtain the flat surface of memory device structures.
Referring to Figure 14, for example, in technology rear end (BEOL), on sandwich construction, form interlayer insulating film 37 and the first electrode contact hole 38 that is arranged in the capacitor of interlayer insulating film.The first electrode contact hole 38 electrically contacts with first electrode 35 of capacitor and it is connected with the wiring (not shown).
Finished capacitor arrangement in the memory device of the present invention by above step.
In final capacitor arrangement, each is to the first adjacent electrode layer 22 and the second electrode lay 24 pole plate as a stacked capacitor, and in first dielectric layer 21 and second dielectric layer 23, except the dielectric layer that is positioned at sandwich construction bottommost and top, each is all as the dielectric layer of a capacitor, (wherein comprises first electrode layer 22 according to from bottom to up order thereby form a plurality of first stacked capacitors of alternately piling up in sandwich construction, second dielectric layer 23, the second electrode lay 24) and a plurality of second stacked capacitor (wherein comprise the second electrode lay 24 according to from bottom to up order, first dielectric layer 21, first electrode layer 22).First electrode 35 of capacitor and second electrode 36 of capacitor are connected in parallel the first all stacked capacitors and second stacked capacitor.
Then, according to the preferential embodiment of method of the present invention, carry out the step that is used to form MOSFET shown in Figure 15 to 16 successively.
Referring to Figure 15, the upset wafer by grind waiting from SOI wafer get on to break off the base portion's substrate 11 and buried insulator layer 12, thereby exposes soi semiconductor layer 13 at the top of memory device structures.
Instead, if in step shown in Figure 1, use the body silicon substrate, then in this step, remove epitaxy Si Ge layer and epitaxial semiconductor layer on the body silicon substrate.Replace grinding, in this step, can adopt wet etching.
Then, referring to Figure 16,, in top semiconductor layer 13, form MOSFET according to the semiconductor technology of routine (for example referring to people such as Wang Geng U.S. Patent application No.US20090174031A1).The isolated side wall 43 that this MOSFET is included in the soi semiconductor layer 13 gate-dielectric 41 above the source region 39 that forms, drain region 40, the raceway groove between the two and grid conductor 42, is provided with in the grid conductor both sides.And, above this MSOMOSFET, also formed interlayer insulating film 45, form metal connecting line 47 on the surface of interlayer insulating film 45 and in interlayer insulating film 45, forming the path (via) 46 that the source region 39 with MOSFET links to each other with metal connecting line 47.
Typically, the side in the drain region 40 of MOSFET directly contacts with polysilicon layer 16, thereby utilizes polysilicon layer 16 that being connected between second electrode 36 of MOSFET and capacitor is provided.In addition, the source region 39 of MOSFET links to each other with the bit line (not shown), and grid conductor links to each other with the word line (not shown).First electrode 35 of capacitor links to each other with ground.
More than describe just illustrating and description the present invention, but not be intended to exhaustive and restriction the present invention for example.Therefore, the present invention is not limited to described embodiment.For obvious modification or the change as can be known of those skilled in the art, all within protection scope of the present invention.
Claims (19)
1. memory device, be included in the MOSFET that forms in the semiconductor layer, and the capacitor arrangement that is positioned at the MOSFET below, described capacitor arrangement comprises two electrode for capacitors, one of the source region of described MOSFET and drain region are electrically connected with one of described two electrode for capacitors
Wherein, described capacitor arrangement comprises a plurality of first stacked capacitors and a plurality of second stacked capacitor that alternately piles up, described a plurality of first stacked capacitor and described a plurality of second stacked capacitor comprise top crown, bottom crown separately and are clipped in dielectric layer between the two, described a plurality of first stacked capacitor and described a plurality of second stacked capacitor are connected in parallel by described two electrode for capacitors, and
The bottom crown of each in described a plurality of first stacked capacitor is formed by the first public electrode layer with the top crown of second stacked capacitor that is positioned at its below, the bottom crown of each in described a plurality of second stacked capacitor is formed by public the second electrode lay with the top crown of first stacked capacitor that is positioned at its below, wherein, described first electrode layer is made up of different electric conducting materials with described the second electrode lay.
2. semiconductor device according to claim 1, wherein, described different electric conducting material has different etch-rates.
3. semiconductor device according to claim 2, the electric conducting material of wherein said first electrode layer and the electric conducting material of described the second electrode lay be selected from metal level, doped polysilicon layer respectively or comprise metal level and doped polysilicon layer in a kind of.
4. semiconductor device according to claim 3, wherein said metal level is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax by being selected from, and a kind of material of MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx and combination in any thereof constitutes.
5. semiconductor device according to claim 4, wherein first electrode layer is made of polysilicon, and the second electrode lay is made of TiN.
6. semiconductor device according to claim 1, wherein first stacked capacitor comprises identical dielectric with second capacitor.
7. semiconductor device according to claim 1, wherein first stacked capacitor comprises different dielectrics with second capacitor.
8. semiconductor device according to claim 1, wherein
First side at described capacitor arrangement in described two electrode for capacitors directly contacts all first electrode layers, and isolates with all the second electrode lay electricity; And
In described two electrode for capacitors another directly contacts all the second electrode lays described capacitor arrangement with the described first side second side surface opposite, and isolates with all first electrode layer electricity.
9. semiconductor device according to claim 1, also comprise described MOSFET and the separated insulating barrier of described capacitor arrangement, and the polysilicon layer that passes described insulating barrier, described polysilicon layer provides being electrically connected of one of the source region of described MOSFET and drain region and one of described two electrode for capacitors.
10. method of making memory device may further comprise the steps:
A) alternately deposit first dielectric layer, first electrode layer, second dielectric layer and the second electrode lay on Semiconductor substrate, to form sandwich construction, described Semiconductor substrate comprises base substrate, sacrifice layer and top semiconductor layer;
B) etching is carried out in first side of described sandwich construction, wherein with respect to first electrode layer, first dielectric layer, second dielectric layer, the part that the selective removal the second electrode lay exposes on first side, thus on described first side, stay depression;
C) etching is carried out in second side of described sandwich construction, wherein with respect to the second electrode lay, first dielectric layer, second dielectric layer, the part that selective removal first electrode layer exposes on second side, thus on described second side, stay depression;
D) cover layer of deposition of insulative material on described sandwich construction;
E) in described cover layer, form the opening that exposes described first side and described second side, wherein stay described insulating material in the depression on first side and second side;
F) filled conductive material in described opening forms respectively two electrode for capacitors that directly contact with all first electrode layers and all the second electrode lays;
G) the upset Semiconductor substrate is removed base substrate and sacrifice layer;
H) source region, drain region and the channel region between source region and drain region of formation MOSFET in described top semiconductor layer, wherein one of the source region of MOSFET and drain region are electrically connected with one of described two electrode for capacitors; And
I) above the channel region of MOSFET, form gate-dielectric and grid conductor.
11. method according to claim 10, wherein first electrode layer is made of polysilicon, and the second electrode lay is made of TiN.
12. method according to claim 10, wherein said first dielectric layer and described second dielectric layer are made up of identical materials.
13. method according to claim 10, wherein said first dielectric layer is made up of different materials with described second dielectric layer.
14. method according to claim 10, wherein said base substrate are the body silicon substrate.
15. method according to claim 14, wherein said sacrifice layer are the SiGe layer.
16. method according to claim 10, wherein said Semiconductor substrate are the SOI substrate.
17. method according to claim 10 wherein also is included in step a) and forms insulating barrier on the Semiconductor substrate, is used for the top semiconductor layer of isolation of semiconductor substrate and the sandwich construction of top.
18. method according to claim 17 wherein also is included in the described insulating barrier in step a) and forms opening; And the polysilicon layer of form filling described opening, described polysilicon layer provides being electrically connected of one of the source region of described MOSFET and drain region and one of described two electrode for capacitors.
19. method according to claim 10, wherein step e) also is included in the isolated side wall that forms in the described cover layer around described sandwich construction, and in described isolated side wall, form the opening that exposes described first side and described second side, wherein isolated side wall defines the rectangular area of memory cell.
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| CN201010157573.7A CN102237364B (en) | 2010-04-21 | 2010-04-21 | Manufacturing method of storage device |
| US13/003,723 US20110260231A1 (en) | 2010-04-21 | 2010-09-21 | Memory device and method for manufacturing the same |
| PCT/CN2010/001460 WO2011130891A1 (en) | 2010-04-21 | 2010-09-21 | Memory device and fabrication method thereof |
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| CN103839779A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Method for forming high-density capacitor structure and capacitor structure |
| CN107204331A (en) * | 2017-07-07 | 2017-09-26 | 上海华虹宏力半导体制造有限公司 | The manufacture method of multi-layer capacitor |
| CN108630685A (en) * | 2017-03-17 | 2018-10-09 | 东芝存储器株式会社 | Storage device and capacity cell |
| CN108666324A (en) * | 2017-03-31 | 2018-10-16 | 旺宏电子股份有限公司 | Memory construction and its manufacturing method |
| CN109712988A (en) * | 2018-12-27 | 2019-05-03 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN112310102A (en) * | 2019-07-23 | 2021-02-02 | 爱思开海力士有限公司 | Semiconductor memory device |
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| WO2011130891A1 (en) | 2011-10-27 |
| CN102237364B (en) | 2013-02-06 |
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