CN102222700A - Thin film transistor element and manufacturing method thereof - Google Patents
Thin film transistor element and manufacturing method thereof Download PDFInfo
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- CN102222700A CN102222700A CN2011101847670A CN201110184767A CN102222700A CN 102222700 A CN102222700 A CN 102222700A CN 2011101847670 A CN2011101847670 A CN 2011101847670A CN 201110184767 A CN201110184767 A CN 201110184767A CN 102222700 A CN102222700 A CN 102222700A
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- 239000010409 thin film Substances 0.000 title claims abstract description 94
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 101
- 239000010410 layer Substances 0.000 claims description 281
- 238000000059 patterning Methods 0.000 claims description 146
- 238000000034 method Methods 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 35
- 239000011229 interlayer Substances 0.000 claims description 23
- 238000005516 engineering process Methods 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229910045601 alloy Inorganic materials 0.000 claims description 16
- 239000000956 alloy Substances 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000000295 complement effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 16
- 230000000694 effects Effects 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 240000008168 Ficus benjamina Species 0.000 description 1
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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Abstract
A thin film transistor device includes a first conductivity type transistor and a second conductivity type transistor. The first conductive type transistor includes a first patterned doped layer, a first gate, a first source, a first drain, and a first semiconductor pattern. The second conductive type transistor includes a second patterned doped layer, a second gate, a second source, a second drain and a second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern constitute a patterned semiconductor layer. The first patterned doped layer is disposed below the first semiconductor pattern, and the second patterned doped layer is disposed above the second semiconductor pattern.
Description
Technical field
The invention relates to a kind of thin-film transistor element and preparation method thereof, refer to a kind of thin-film transistor that nonionic injection technology and laser processing technique form the Low ESR doped layer and preparation method thereof that utilizes especially.
Background technology
Polysilicon (poly silicon) thin-film transistor by this height of polycrystalline silicon material electronics mobility (electrical mobility) characteristic thereby have the better electrical performance of more general widely used amorphous silicon film transistor.Along with low temperature polycrystalline silicon (low temperature poly silicon, LTPS) technology constantly progresses greatly, for example large-area uniformity of film of some subject matters is not good to be improved gradually.Therefore, present low temperature polycrystalline silicon technology is also towards more developing in the large-size substrate application.Yet, in known low temperature polycrystalline silicon technology, generally be to utilize ion to inject (ion implant) technology to form doped layer to reduce the contact impedance of thin-film transistor, and the ion implantor that is used for carrying out ion implantation technology will import large-size substrate technology, except many technical problems also need overcome, the board cost of manufacture also is another big problem.Therefore, how otherwise to form one of direction that low-impedance doped layer also makes great efforts to develop for present industry.
In addition, because low temperature polycrystalline silicon has the different conduction-types doped layer of can arranging in pairs or groups forming the characteristic of N type thin-film transistor or P type thin-film transistor, so low temperature polycrystalline silicon technology generally also can be used to form simultaneously N type thin-film transistor and P type thin-film transistor on a substrate.And in known low temperature polycrystalline silicon technology, be to form patterning N type doped layer and patterning P type doped layer at grade respectively, therefore need to increase many extra processing steps and cause when avoiding variant conduction type doped layer to form and interact, make therefore also that but then integrated artistic is complicated and cost is increased.
Summary of the invention
One of main purpose of the present invention is to provide a kind of thin-film transistor element and preparation method thereof, utilize nonionic injection technology and laser processing technique to form low-impedance doped layer, the doped layer with different conduction-types of arranging in pairs or groups simultaneously is arranged at the design on the Different Plane, reaches the effect that work simplification, enhancing efficiency and cost reduce.
For reaching above-mentioned purpose, a preferred embodiment of the present invention provides a kind of thin-film transistor element.This thin-film transistor element comprises one first conductivity type of transistor and one second conductivity type of transistor.First conductivity type of transistor comprises one first patterning doped layer, a first grid, one first source electrode, one first drain electrode and one first semiconductor pattern.Second conductivity type of transistor comprises one second patterning doped layer, a second grid, one second source electrode, one second drain electrode and one second semiconductor pattern.First source electrode and first drain electrode are and the first patterning doped layer electrically connect, and second source electrode and second drain electrode are and the second patterning doped layer electrically connect.First semiconductor pattern and second semiconductor pattern constitute a patterned semiconductor layer.The first patterning doped layer is to be arranged under first semiconductor pattern, and the second patterning doped layer is to be arranged on second semiconductor pattern.
This first patterning doped layer comprises at least one N type alloy, and this second patterning doped layer comprises at least one P type alloy.
This patterned semiconductor layer comprises a polysilicon layer.
It is characterized in that, further comprise a gate dielectric, be arranged on this patterned semiconductor layer, this first patterning doped layer and this second patterning doped layer, wherein this first grid and this second grid are to be arranged on this gate dielectric.
It is characterized in that, comprise that further an interlayer dielectric layer is arranged on this gate dielectric, this first grid and this second grid, wherein this second source electrode and this second drain electrode be pass this interlayer dielectric layer and this gate dielectric and with this second patterning doped layer electrically connect, and this first source electrode and this first drain electrode be pass this interlayer dielectric layer, this gate dielectric and this first semiconductor pattern and with this first patterning doped layer electrically connect.
It is characterized in that, comprise that further an interlayer dielectric layer is arranged on this gate dielectric, this first grid and this second grid, wherein this second source electrode and this second drain electrode be pass this interlayer dielectric layer and this gate dielectric and with this second patterning doped layer electrically connect, and this first source electrode and this first drain electrode are to be arranged between this substrate and this first patterning doped layer to small part.
It is characterized in that this first conductivity type of transistor further comprises a first grid dielectric layer, be arranged between this substrate and this first patterning doped layer, and this first grid is to be arranged between this first grid dielectric layer and this substrate; And this second conductivity type of transistor more comprises a second grid dielectric layer, be arranged on this patterned semiconductor layer, this first patterning doped layer and this second patterning doped layer, and this second grid is to be arranged on this second grid dielectric layer.
It is characterized in that this first drain electrode and this second grid electrically connect.
It is characterized in that this first drain electrode is to electrically connect with this second source electrode, this first grid is and this second grid electrically connect.
For reaching above-mentioned purpose, a preferred embodiment of the present invention provides a kind of manufacture method of thin-film transistor element.This manufacture method comprises: a substrate is provided, and substrate has one first conductivity regions and one second conductivity regions; First conductivity regions in substrate forms one first patterning doped layer; First conductivity regions and second conductivity regions in substrate form semi-conductor layer, and wherein the semiconductor layer of first conductivity regions is to cover the first patterning doped layer; On the semiconductor layer of second conductivity regions, form one second patterning doped layer; Patterned semiconductor layer is so that the semiconductor layer of the semiconductor layer of first conductivity regions and second conductivity regions is disconnected from each other; And semiconductor layer, the first patterning doped layer and the second patterning doped layer carried out laser processing technique at least one time.
This laser processing technique comprises laser processing technique twice, carries out after reaching before this second patterning doped layer of formation.
This laser processing technique is to carry out after forming this second patterning doped layer.
This first patterning doped layer and this second patterning doped layer are to utilize a chemical vapor deposition method to form respectively.
This first patterning doped layer comprises at least one N type alloy, and this second patterning doped layer comprises at least one P type alloy.
This laser processing technique is a polysilicon layer with this semiconductor layer by an amorphous silicon layer upgrading.
Further comprise: form a gate dielectric, cover this semiconductor layer of this first conductivity regions and this semiconductor layer and this second patterning doped layer of this second conductivity regions simultaneously; On this gate dielectric of this first conductivity regions, form a first grid, and on this gate dielectric of this second conductivity regions, form a second grid; In this first conductivity regions, form one first source electrode and one first drain electrode, and make this first source electrode and this first drain electrode and this first patterning doped layer electrically connect; And in this second conductivity regions, form one second source electrode and one second drain electrode, and make this second source electrode and this second drain electrode and this second patterning doped layer electrically connect.
Further comprise: on this gate dielectric, this first grid and this second grid, form an interlayer dielectric layer; And in this interlayer dielectric layer and this gate dielectric, form a plurality of contact holes, to expose this second patterning doped layer of part, wherein this second source electrode and this second drain electrode are to see through these contact holes and this second patterning doped layer electrically connect.
Further comprise: before this first patterning doped layer forms, form a first grid in this first conductivity regions of this substrate; Before this first patterning doped layer forms, on this substrate, form a first grid dielectric layer to cover this first grid; On this substrate, form a second grid dielectric layer, cover semiconductor layer and this second patterning doped layer of this second conductivity regions; On this second grid dielectric layer of this second conductivity regions, form a second grid; Form one first source electrode and one first drain electrode in this first conductivity regions, and make this first source electrode and this first drain electrode and this first patterning doped layer electrically connect; And form one second source electrode and one second drain electrode, and make this second source electrode and this second drain electrode and this second patterning doped layer electrically connect in this second conductivity regions.
Further comprise: on this second grid dielectric layer and this second grid, form an interlayer dielectric layer; And in this interlayer dielectric layer and this second grid dielectric layer, form a plurality of contact holes, to expose this second patterning doped layer of part, wherein this second source electrode and this second drain electrode are by these contact holes and this second patterning doped layer electrically connect.
This first patterning doped layer and this second patterning doped layer are to utilize a nonionic to inject (non-implant) technology respectively to form.
The present invention utilizes the nonionic injection technology to form the patterning doped layer of different conduction-types on different surfaces, and the collocation laser processing technique reduces the impedance of doped layer, to realize making the thin-film transistor with dynamical different conduction-types simultaneously via the technology of simplifying.
Description of drawings
Fig. 1 is the schematic diagram of the thin-film transistor element of one first preferred embodiment of the present invention.
Fig. 2 A to Fig. 2 H is the manufacture method schematic diagram of the thin-film transistor element of one first preferred embodiment of the present invention.
Fig. 3 is the schematic diagram of the thin-film transistor element of another preferred embodiment of the present invention.
Fig. 4 is the schematic diagram of the thin-film transistor element of one second preferred embodiment of the present invention.
Fig. 5 A to Fig. 5 J is the manufacture method schematic diagram of the thin-film transistor element of one second preferred embodiment of the present invention.
Fig. 6 is the schematic diagram of the thin-film transistor element of another preferred embodiment of the present invention.
Fig. 7 is the schematic diagram of the thin-film transistor element of one the 3rd preferred embodiment of the present invention.
Fig. 8 is the schematic diagram of the thin-film transistor element of one the 4th preferred embodiment of the present invention.
Description of reference numerals
Embodiment
For making those skilled in the art can further understand the present invention, hereinafter the spy enumerates preferred embodiment of the present invention, and conjunction with figs., describe in detail constitution content of the present invention and the effect desiring to reach.
Please refer to Fig. 1.Fig. 1 is the schematic diagram of the thin-film transistor element of one first preferred embodiment of the present invention.For convenience of description, of the present invention each graphic only for signal being easier to understand the present invention, its detailed ratio can be adjusted according to the demand of design.As shown in Figure 1, thin-film transistor element 100 comprises one first conductivity type of transistor 110 and one second conductivity type of transistor 120.First conductivity type of transistor 110 comprises one first patterning doped layer 15, a first grid 11A, one first source electrode 12A, one first drain electrode 13A and one first semiconductor pattern 14A.Second conductivity type of transistor 120 comprises one second patterning doped layer 16, a second grid 11B, one second source electrode 12B, one second drain electrode 13B and one second semiconductor pattern 16.In the present embodiment, the first patterning doped layer 15 can comprise at least one N type alloy for example phosphorus (phosphorous) or other phosphorous compounds, and the second patterning doped layer 16 can comprise for example compound of boron (boron) or other boracics of at least one P type alloy, but the present invention can not utilize other N type alloy and P type alloys of being fit to form the first patterning doped layer 15 and the second patterning doped layer 16 respectively as limit.In addition, in the present embodiment, first conductivity type of transistor 110 is preferably a N type thin-film transistor and second conductivity type of transistor 120 is preferably a P type thin-film transistor, but the present invention is not as limit.In addition, in the present embodiment, the first source electrode 12A and the first drain electrode 13A are and the first patterning doped layer, 15 electrically connects, and the second source electrode 12B and the second drain electrode 13B are and the second patterning doped layer, 16 electrically connects.In the present embodiment, the first semiconductor pattern 14A and the second semiconductor pattern 14B constitute a patterned semiconductor layer 14C, that is first semiconductor pattern 14A and the second semiconductor pattern 14B be a part that is respectively patterned semiconductor layer 14C, but not as limit.For example, the first semiconductor pattern 14A and the second semiconductor pattern 14B also can be different semi-conducting materials.The patterned semiconductor layer 14C of present embodiment can comprise a polysilicon layer, but can not utilize as limit other semi-conducting materials that are fit to for example materials such as amorphous silicon semiconductor, oxide semiconductor or organic semiconductor form patterned semiconductor layer 14C.In addition, as shown in Figure 1, the first patterning doped layer 15 is to be arranged under the first semiconductor pattern 14A, and the second patterning doped layer 16 is to be arranged on the second semiconductor pattern 14B.The first patterning doped layer 15 of present embodiment and the second patterning doped layer 16 can utilize for example chemical vapour deposition (CVD) of nonionic injection technology, and (chemical vapor deposition, mode CVD) is formed, but not as limit.For example the first patterning doped layer 15 and the second patterning doped layer 16 also can utilize the ion injection mode to form.Other what deserves to be explained is, as shown in Figure 1, the thin-film transistor element 100 of present embodiment can comprise more that a gate dielectric 17 is arranged on patterned semiconductor layer 14C, the first patterning doped layer 15 and the second patterning doped layer 16, and first grid 11A and second grid 11B are arranged on the gate dielectric 17.Therefore, first conductivity type of transistor 110 of present embodiment and second conductivity type of transistor 120 are the thin-film transistors that belong to top grid (top-gate) structure.In addition, the thin-film transistor element 100 of present embodiment can comprise more that an interlayer dielectric layer 18 is arranged on gate dielectric 17, first grid 11A and the second grid 11B.The first source electrode 12A and first the drain electrode 13A be pass interlayer dielectric layer 18, gate dielectric 17 and the first semiconductor pattern 14A and with the first patterning doped layer, 15 electrically connects.The second source electrode 12B and the second drain electrode 13B be pass interlayer dielectric layer 18 and gate dielectric 17 and with the second patterning doped layer, 16 electrically connects.What deserves to be explained is, structure by present embodiment, can utilize a patterned conductive layer to form the first source electrode 12A, first drain electrode 13A, the second source electrode 12B and the second drain electrode 13B and reach the effect of simplifying processing step, but present embodiment can optionally not use identical or different electric conducting material to form each source electrode and each drain electrode as limit.
Please refer to Fig. 2 A to Fig. 2 H.Fig. 2 A to Fig. 2 H is the manufacture method schematic diagram of the thin-film transistor element of one first preferred embodiment of the present invention.The first half that please notes among Fig. 2 A to Fig. 2 H each figure is that top view and Lower Half are the profile that the hatching line A-A ' of corresponding top view is illustrated.The manufacture method of the thin-film transistor element of present embodiment comprises the following steps.Shown in Fig. 2 A, a substrate 10 at first is provided, substrate 10 has one first conductivity regions 10A and one second conductivity regions 10B.Then, the first conductivity regions 10A in substrate 10 forms one first patterning doped layer 15.In the present embodiment, the first patterning doped layer 15 can comprise at least one N type alloy for example phosphorus or other phosphorous compounds, but not as limit.The first patterning doped layer 15 can be modes such as utilizing a for example chemical vapour deposition (CVD) of nonionic injection technology, physical vapour deposition (PVD) (physical vapor deposition) or coating (spin-on) film forming and when film forming alloy is sneaked in the first patterning doped layer 15 in the lump, but the present invention not as limit and can with film-forming process with inject alloy technology for example ion implantation technology carry out respectively at the different process step.
Then, shown in Fig. 2 B, form semi-conductor layer 14 in the first conductivity regions 10A and the second conductivity regions 10B of substrate 10.The semiconductor layer 14 of present embodiment can comprise an amorphous silicon layer, but not as limit.The semiconductor layer 14 of the first conductivity regions 10A is to cover the first patterning doped layer 15.Then, the semiconductor layer 14 and the first patterning doped layer 15 are carried out a laser processing technique 31.In the present embodiment, be to be a polysilicon layer with semiconductor layer 14 by the amorphous silicon layer upgrading by laser processing technique 31, but not as limit.It should be noted that in addition by laser processing technique 31 also to make the resistance of the first patterning doped layer 15 reduce simultaneously.Therefore in manufacture method of the present invention, can utilize single laser processing technique 31 simultaneously the semiconductor layer 14 and the first patterning doped layer 15 to be produced treatment effects, or also can optionally select to carry out earlier before semiconductor layer 14 forms steps a laser processing technique reduces the resistance of the first patterning doped layer 15 and then carries out laser processing technique 31 more in addition and come semiconductor layer 14 generation treatment effects and the resistance that further reduces by the first patterning doped layer 15 after semiconductor layer 14 forms.
Then, shown in Fig. 2 C, on the semiconductor layer 14 of the second conductivity regions 10B, form one second patterning doped layer 16.In the present embodiment, the second patterning doped layer 16 can comprise for example compound of boron or other boracics of at least one N type alloy, but not as limit.The generation type of the second patterning doped layer 16 can be with reference to above-mentioned explanation to the first patterning doped layer, 15 generation types, at this and repeat no more.Other what deserves to be explained is, shown in Fig. 2 C, manufacture method of the present invention can comprise utilizes 32 pairs of semiconductor layers of a laser processing technique 14, the first patterning doped layer 15 and the second patterning doped layer 16 to handle, and the effect of laser processing technique 32 can comprise the resistance that reduces by the second patterning doped layer 16, make semiconductor layer 14 to be polysilicon layer or the resistance that reduces by the first patterning doped layer 15 by the amorphous silicon layer upgrading, but not as limit.For instance, production method of the present invention can only comprise laser processing technique for example laser processing technique 32 simultaneously semiconductor layer 14, the first patterning doped layer 15 and the second patterning doped layer 16 are handled so that the integrated artistic step is simplified, or carry out a laser processing technique or before the second patterning doped layer 16 forms step, carry out laser processing technique 31 before also can optionally optionally forming step respectively at semiconductor layer 14 again, to guarantee to reduce effectively the resistance of the first patterning doped layer 15 and the second patterning doped layer 16.
Then, shown in Fig. 2 D, semiconductor layer 14 is carried out patterning, so that the semiconductor layer 14 of the semiconductor layer 14 of the first conductivity regions 10A and the second conductivity regions 10B is disconnected from each other.In the present embodiment, semiconductor layer 14 is through formation one patterned semiconductor layer 14C behind the Patternized technique, and patterned semiconductor layer 14C comprises one first semiconductor pattern 14A that is positioned at the first conductivity regions 10A and the one second semiconductor pattern 14B that is positioned at the second conductivity regions 10B.Afterwards, shown in Fig. 2 E, form a gate dielectric 17, cover the first semiconductor pattern 14A, the second semiconductor pattern 14B and the second patterning doped layer 16 simultaneously.Then, shown in Fig. 2 F, on the gate dielectric 17 of the first conductivity regions 10A, form a first grid 11A, and on the gate dielectric 17 of the second conductivity regions 10B, form a second grid 11B.First grid 11A and second grid 11B can be defined by same conductive layer and by same Patternized technique, but not as limit.Shown in Fig. 2 G, go up formation one interlayer dielectric layer 18 subsequently in gate dielectric 17, first grid 11A and second grid 11B.
Then, shown in Fig. 2 H, in interlayer dielectric layer 18 and gate dielectric 17, form a plurality of contact holes 19, wherein the contact hole 19 of the second conductivity regions 10B expose the part the second patterning doped layer 16, and the contact hole 19 of the first conductivity regions 10A be more be passed down through the first semiconductor pattern 14A and expose the part the first patterning doped layer 15.Subsequently, form one first source electrode 12A and one first drain electrode 13A, and form one second source electrode 12B and one second drain electrode 13B in the second conductivity regions 10B in the first conductivity regions 10A.The second source electrode 12B and the second drain electrode 13B are contact hole 19 and the second patterning doped layer, 16 electrically connects that see through the second conductivity regions 10B, and the first source electrode 12A and the first drain electrode 13A are contact hole 19 and the first patterning doped layer, 15 electrically connects that see through the first conductivity regions 10A.The first source electrode 12A of present embodiment, first drain electrode 13A, the second source electrode 12B and the second drain electrode 13B can be by same conductive layers or are formed by different conductive layers respectively, and conductive layer can be formed by the electric conducting material of single or multiple lift.Can finish thin-film transistor element 100 shown in Fig. 2 H by above-mentioned manufacture method.What deserves to be explained is, shown in Fig. 2 H, the thin-film transistor element 100 of present embodiment first the drain electrode 13A can with second grid 11B electrically connect, this structure can be used in the driving element design that for example drives organic luminuous dipolar object display, and the thin-film transistor element 100 of present embodiment can be considered a kind of complementary thin-film transistor (complementary thin film transistor) element, but the present invention not as limit and the viewable design elasticity of demand make each grid, each source electrode and respectively drain electrically connect or separation each other.
Hereinafter will implement the sample attitude and describe, and be simplified illustration, and illustrate that below being primarily aimed at different the locating of each embodiment describes in detail, and no longer identical locating repeated to give unnecessary details at the difference of thin-film transistor element of the present invention and preparation method thereof.In addition, components identical is to indicate with identical label in the various embodiments of the present invention, is beneficial to check one against another between each embodiment.
Please refer to Fig. 3.Fig. 3 is the schematic diagram of the thin-film transistor element of another preferable enforcement sample attitude of the present invention.As shown in Figure 3, the difference of the thin-film transistor element 101 of this enforcement sample attitude and above-mentioned thin-film transistor element 100 is in the first drain electrode 13A of thin-film transistor element 101, and first grid 11A is and second grid 11B electrically connect.In other words, the thin-film transistor element 101 of this enforcement sample attitude can be considered a kind of complementary thin-film transistor element that is used in transducer (inverter), but the present invention is not as limit.
Please refer to Fig. 4.Fig. 4 is the schematic diagram of the thin-film transistor element of one second preferred embodiment of the present invention.As shown in Figure 4, thin-film transistor element 200 comprises one first conductivity type of transistor 210 and one second conductivity type of transistor 220.The places different with the first above-mentioned preferred embodiment are, first conductivity type of transistor 210 of present embodiment comprises that more a first grid dielectric layer 17A is arranged between the substrate 10 and the first patterning doped layer 15, and first grid 11A is arranged between first grid dielectric layer 17A and the substrate 10.In addition, second conductivity type of transistor 220 of present embodiment more comprises a second grid dielectric layer 17B, be arranged on patterned semiconductor layer 14C, the first patterning doped layer 15 and the second patterning doped layer 16, and second grid 11B is arranged on the second grid dielectric layer 17B.In other words, the thin-film transistor element 200 of present embodiment has first grid dielectric layer 17A and second grid dielectric layer 17B to replace the gate dielectric 17 of the foregoing description except other, and adjust first grid 11A relative position outside, the feature of all the other each parts is similar to above-mentioned first preferred embodiment to material behavior, so at this and repeat no more.What deserves to be explained is, as shown in Figure 4, first conductivity type of transistor 210 of present embodiment can be the thin-film transistor of a bottom grid (bottom-gate) structure, and second conductivity type of transistor 220 can be the thin-film transistor of a top grid structure, but the present invention is not as limit and viewable design need be adjusted the relative position of the second grid 11B of second conductivity type of transistor 220.
Please refer to Fig. 5 A to Fig. 5 J.Fig. 5 A to Fig. 5 J is the manufacture method schematic diagram of the thin-film transistor element of one second preferred embodiment of the present invention.The first half that please notes among Fig. 5 A to Fig. 5 J each figure is that top view and Lower Half are the profile that the hatching line B-B ' of corresponding top view is illustrated.What deserves to be explained is, shown in Fig. 5 A to Fig. 5 J, with above-mentioned first preferred embodiment different be in, the manufacture method of the thin-film transistor element 200 of present embodiment is before the first patterning doped layer 15 forms, in the first conductivity regions 10A of 10 substrates, form first grid 11A, and followed before the first patterning doped layer 15 forms, on substrate 10, form a first grid dielectric layer 17A to cover first grid 11A.In addition, the manufacture method of present embodiment is included in addition and forms a second grid dielectric layer 17B on the substrate 10, cover the semiconductor layer 14 (the second semiconductor pattern 14B just) and the second patterning doped layer 16 of the second conductivity regions 10B, and go up the formation second grid in the second grid dielectric layer 17B of the second conductivity regions 10B.Except above steps, the manufacture method of the thin-film transistor element 200 of present embodiment is similar to above-mentioned first preferred embodiment, at this and repeat no more.What deserves to be explained is, can finish thin-film transistor element 200 shown in Fig. 5 J by above-mentioned manufacture method.Shown in Fig. 5 J, the thin-film transistor element 200 of present embodiment first the drain electrode 13A can with second grid 11B electrically connect, this structure can be used in the driving element design that for example drives organic luminuous dipolar object display, and the thin-film transistor element 200 of present embodiment also can be considered a kind of complementary thin-film transistor element, but the present invention not as limit and the viewable design elasticity of demand make each grid, each source electrode and respectively drain electrically connect or separation each other.
Please refer to Fig. 6.Fig. 6 is the schematic diagram of the thin-film transistor element of another preferable enforcement sample attitude of the present invention.As shown in Figure 6, the difference of the thin-film transistor element 201 of this enforcement sample attitude and above-mentioned thin-film transistor element 200 is in the first drain electrode 13A of thin-film transistor element 201, and first grid 11A is and second grid 11B electrically connect.In other words, the thin-film transistor element 201 of this enforcement sample attitude can be considered a kind of complementary thin-film transistor element that is used in transducer, but not as limit.
Please refer to Fig. 7.Fig. 7 is the schematic diagram of the thin-film transistor element of one the 3rd preferred embodiment of the present invention.As shown in Figure 7, thin-film transistor element 300 comprises one first conductivity type of transistor 310 and one second conductivity type of transistor 320.The places different with the first above-mentioned preferred embodiment are, the first source electrode 12A of present embodiment and the first drain electrode 13A are arranged between the substrate 10 and the first patterning doped layer 15 to small part, in other words, when making the thin-film transistor element 300 of present embodiment, can then form the first patterning doped layer 15 again with first source electrode 12A of cover part and the first drain electrode 13A of part prior to forming the first source electrode 12A and the first drain electrode 13A on the substrate 10.The thin-film transistor element 300 of present embodiment is except the first source electrode 12A and the first drain electrode 13A, and the feature of all the other each parts, material behavior and manufacture method are similar to above-mentioned first preferred embodiment, so at this and repeat no more.In addition, in the present embodiment, also make each grid, each source electrode and respectively drain electrically connect or separation each other the viewable design elasticity of demand.
Please refer to Fig. 8.Fig. 8 is the schematic diagram of the thin-film transistor element of one the 4th preferred embodiment of the present invention.As shown in Figure 8, thin-film transistor element 400 comprises one first conductivity type of transistor 410 and one second conductivity type of transistor 420.The places different with the second above-mentioned preferred embodiment are, the first source electrode 12A of present embodiment and the first drain electrode 13A are arranged between the first grid dielectric layer 17A and the first patterning doped layer 15 to small part, in other words, when making the thin-film transistor element 400 of present embodiment, can form the back prior to first grid dielectric layer 17A and go up the formation first source electrode 12A and the first drain electrode 13A, then form the first patterning doped layer 15 again with first source electrode 12A of cover part and the first drain electrode 13A of part in first grid dielectric layer 17A.The thin-film transistor element 400 of present embodiment is except the first source electrode 12A and the first drain electrode 13A, and the feature of all the other each parts, material behavior and manufacture method are similar to above-mentioned second preferred embodiment, so at this and repeat no more.In addition, in the present embodiment, also make each grid, each source electrode and respectively drain electrically connect or separation each other the viewable design elasticity of demand.
Comprehensive the above, thin-film transistor element of the present invention is to utilize the different upper and lower surfaces that the patterning doped layer of different conduction-types are arranged at semiconductor layer respectively, reach the effect of simplifying technology, utilize laser processing technique to reduce the impedance of the doped layer that forms with the nonionic injection mode simultaneously, make under the situation of work simplification, still can obtain dynamical thin-film transistor element.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to protection scope of the present invention.
Claims (20)
1. a thin-film transistor element is arranged on the substrate, and this thin-film transistor element comprises:
One first conductivity type of transistor, comprise one first patterning doped layer, a first grid, one first source electrode, one first drain electrode and one first semiconductor pattern, wherein this first source electrode and this first drain electrode are and this first patterning doped layer electrically connect; And
One second conductivity type of transistor, comprise one second patterning doped layer, a second grid, one second source electrode, one second drain electrode and one second semiconductor pattern, wherein this second source electrode and this second drain electrode are and this second patterning doped layer electrically connect;
Wherein this first semiconductor pattern and this second semiconductor pattern constitute a patterned semiconductor layer, and this first patterning doped layer is to be arranged under this first semiconductor pattern, and this second patterning doped layer is to be arranged on this second semiconductor pattern.
2. thin-film transistor element as claimed in claim 1 is characterized in that, this first patterning doped layer comprises at least one N type alloy, and this second patterning doped layer comprises at least one P type alloy.
3. thin-film transistor element as claimed in claim 1 is characterized in that this patterned semiconductor layer comprises a polysilicon layer.
4. thin-film transistor element as claimed in claim 1, it is characterized in that, further comprise a gate dielectric, be arranged on this patterned semiconductor layer, this first patterning doped layer and this second patterning doped layer, wherein this first grid and this second grid are to be arranged on this gate dielectric.
5. thin-film transistor element as claimed in claim 4, it is characterized in that, comprise that further an interlayer dielectric layer is arranged on this gate dielectric, this first grid and this second grid, wherein this second source electrode and this second drain electrode be pass this interlayer dielectric layer and this gate dielectric and with this second patterning doped layer electrically connect, and this first source electrode and this first drain electrode be pass this interlayer dielectric layer, this gate dielectric and this first semiconductor pattern and with this first patterning doped layer electrically connect.
6. thin-film transistor element as claimed in claim 4, it is characterized in that, comprise that further an interlayer dielectric layer is arranged on this gate dielectric, this first grid and this second grid, wherein this second source electrode and this second drain electrode be pass this interlayer dielectric layer and this gate dielectric and with this second patterning doped layer electrically connect, and this first source electrode and this first drain electrode are to be arranged between this substrate and this first patterning doped layer to small part.
7. thin-film transistor element as claimed in claim 1, it is characterized in that, this first conductivity type of transistor further comprises a first grid dielectric layer, be arranged between this substrate and this first patterning doped layer, and this first grid is to be arranged between this first grid dielectric layer and this substrate; And this second conductivity type of transistor more comprises a second grid dielectric layer, be arranged on this patterned semiconductor layer, this first patterning doped layer and this second patterning doped layer, and this second grid is to be arranged on this second grid dielectric layer.
8. thin-film transistor element as claimed in claim 1 is characterized in that, this first drain electrode and this second grid electrically connect.
9. thin-film transistor element as claimed in claim 1 is characterized in that this first drain electrode is to electrically connect with this second source electrode, and this first grid is and this second grid electrically connect.
10. the manufacture method of a thin-film transistor element comprises:
One substrate is provided, and this substrate has one first conductivity regions and one second conductivity regions;
This first conductivity regions in this substrate forms one first patterning doped layer;
This first conductivity regions and this second conductivity regions in this substrate form semi-conductor layer, and wherein this semiconductor layer of this first conductivity regions is to cover this first patterning doped layer;
On this semiconductor layer of this second conductivity regions, form one second patterning doped layer;
This semiconductor layer of patterning makes this semiconductor layer of this semiconductor layer of this first conductivity regions and this second conductivity regions disconnected from each other; And
This semiconductor layer, this first patterning doped layer and this second patterning doped layer are carried out laser processing technique at least one time.
11. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that, this laser processing technique comprises laser processing technique twice, carries out after reaching before this second patterning doped layer of formation.
12. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that, this laser processing technique is to carry out after forming this second patterning doped layer.
13. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that, this first patterning doped layer and this second patterning doped layer are to utilize a chemical vapor deposition method to form respectively.
14. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that, this first patterning doped layer comprises at least one N type alloy, and this second patterning doped layer comprises at least one P type alloy.
15. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that, this laser processing technique is a polysilicon layer with this semiconductor layer by an amorphous silicon layer upgrading.
16. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that further comprising:
Form a gate dielectric, cover this semiconductor layer of this first conductivity regions and this semiconductor layer and this second patterning doped layer of this second conductivity regions simultaneously;
On this gate dielectric of this first conductivity regions, form a first grid, and on this gate dielectric of this second conductivity regions, form a second grid;
In this first conductivity regions, form one first source electrode and one first drain electrode, and make this first source electrode and this first drain electrode and this first patterning doped layer electrically connect; And
In this second conductivity regions, form one second source electrode and one second drain electrode, and make this second source electrode and this second drain electrode and this second patterning doped layer electrically connect.
17. the manufacture method of complementary thin-film transistor as claimed in claim 16 is characterized in that further comprising:
On this gate dielectric, this first grid and this second grid, form an interlayer dielectric layer; And
Form a plurality of contact holes in this interlayer dielectric layer and this gate dielectric, to expose this second patterning doped layer of part, wherein this second source electrode and this second drain electrode are to see through these contact holes and this second patterning doped layer electrically connect.
18. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that further comprising:
Before this first patterning doped layer forms, form a first grid in this first conductivity regions of this substrate;
Before this first patterning doped layer forms, on this substrate, form a first grid dielectric layer to cover this first grid;
On this substrate, form a second grid dielectric layer, cover semiconductor layer and this second patterning doped layer of this second conductivity regions;
On this second grid dielectric layer of this second conductivity regions, form a second grid;
Form one first source electrode and one first drain electrode in this first conductivity regions, and make this first source electrode and this first drain electrode and this first patterning doped layer electrically connect; And
Form one second source electrode and one second drain electrode in this second conductivity regions, and make this second source electrode and this second drain electrode and this second patterning doped layer electrically connect.
19. the manufacture method of thin-film transistor element as claimed in claim 18 is characterized in that further comprising:
On this second grid dielectric layer and this second grid, form an interlayer dielectric layer; And
In this interlayer dielectric layer and this second grid dielectric layer, form a plurality of contact holes, to expose this second patterning doped layer of part, wherein this second source electrode and this second drain electrode are by these contact holes and this second patterning doped layer electrically connect.
20. the manufacture method of thin-film transistor element as claimed in claim 10 is characterized in that this first patterning doped layer and this second patterning doped layer are to utilize a nonionic injection technology to form respectively.
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| TW100116472A TWI422039B (en) | 2011-05-11 | 2011-05-11 | Thin film transistor device and manufacturing method thereof |
| TW100116472 | 2011-05-11 |
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| US (1) | US8513668B2 (en) |
| CN (1) | CN102222700B (en) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017147970A1 (en) * | 2016-02-29 | 2017-09-08 | 深圳市华星光电技术有限公司 | Complementary thin film transistor and manufacturing method therefor |
| CN113130513A (en) * | 2016-11-01 | 2021-07-16 | 群创光电股份有限公司 | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011010542A1 (en) * | 2009-07-23 | 2011-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| TWI527201B (en) | 2013-11-06 | 2016-03-21 | 友達光電股份有限公司 | Pixel structure and fabricating method thereof |
| CN103715196B (en) * | 2013-12-27 | 2015-03-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| TWI535034B (en) | 2014-01-29 | 2016-05-21 | 友達光電股份有限公司 | Pixel structure and method of fabricating the same |
| CN105514126B (en) * | 2016-02-19 | 2019-01-22 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN107818986A (en) * | 2016-09-14 | 2018-03-20 | 天马日本株式会社 | Semiconductor device and its manufacture method and display device and its manufacture method |
| CN106847837B (en) * | 2017-04-26 | 2020-01-10 | 京东方科技集团股份有限公司 | Complementary thin film transistor, manufacturing method thereof and array substrate |
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| JPH09191114A (en) * | 1997-01-21 | 1997-07-22 | Casio Comput Co Ltd | Thin film transistor and its manufacture |
| US20050258486A1 (en) * | 2004-05-24 | 2005-11-24 | Han-Hee Yoon | Thin film transistor substrate and fabrication method thereof |
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| CN113130513A (en) * | 2016-11-01 | 2021-07-16 | 群创光电股份有限公司 | Display device |
Also Published As
| Publication number | Publication date |
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| CN102222700B (en) | 2013-01-09 |
| US20120286279A1 (en) | 2012-11-15 |
| US8513668B2 (en) | 2013-08-20 |
| TW201246549A (en) | 2012-11-16 |
| TWI422039B (en) | 2014-01-01 |
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