CN102221991B

CN102221991B - 4-bit RISC (Reduced Instruction-Set Computer) microcontroller

Info

Publication number: CN102221991B
Application number: CN201110135254.0A
Authority: CN
Inventors: 陈勤学; 丁东民; 金翔
Original assignee: China Resources Semiconductor Shenzhen Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2011-05-24
Filing date: 2011-05-24
Publication date: 2014-04-09
Anticipated expiration: 2031-05-24
Also published as: CN102221991A

Abstract

The invention provides a 4-bit RISC (Reduced Instruction-Set Computer) microcontroller comprising a control module, a program memory, a register file, a reset module, a clock module and at least one peripheral function module; the control module comprises an instruction register, an instruction encoder, a stack, an ALU (Arithmetic Logic Unit) and a program counter; a two-level two-phase assembly line architecture is adopted; each instruction cycle is divided into a first phase and a second phase; in the first phase, the control module completes the operations of stack warehousing, program memory reading, register reading, instruction encoding and ALU arithmetic; and in the second phase, the control module completes the operations of stack pulling, instruction register latching, register writing and program counter rewriting. The invention further provides an intelligent toy comprising a control chip. The control chip has improved voice playing effect and lower production cost.

Description

A kind of 4 digit RISC micro controllers

Technical field

The present invention relates to integrated circuit (IC) design field.More specifically, the present invention relates to a kind of low-cost multifunctional intellectual toy kernel control chip.

Background technology

Microcontroller kind is a lot, from data-bus width, there are four 8-digit microcontrollers, eight-bit microcontroller, sixteen bit microcontroller, 32 8-digit microcontrollers etc., from instruction framework, there is sophisticated vocabulary (Complex Instruction Set Computer, CISC) microcontroller and reduced instruction set computer (Reduced Instruction Set Computer, RISC) microcontroller etc.From architecture, for necessary more integrated special-purpose peripheral hardwares of kernel control chip of intelligent toy, such as speech memory, voice output driving circuit, LCD/LED driving circuit etc.Such control chip is except common computing and steering order, and also needing has enough phonetic control commands.

Fig. 1 illustrates the structured flowchart of the conventional toy control chip of prior art.The voice module of existing toy control chip only comprises speech memory 105 and voice driven 106, and control chip is by realizing its control to voice to the operation of special function register (SFR).Read with the data of common chip, process similar, the workflow of the control chip shown in Fig. 1 is as follows: CPU core 101 is first assigned to voice address register 102 the address of the speech data that will read, speech memory 105 is opened and the speech data on appropriate address is passed to speech data register 103, CPU core 101 is reading out data from speech data register 103 again, utilize the algorithm that Software for Design is good to process these data, convert certain format to, be assigned to voice driven register 104, voice driven module 106 becomes corresponding driving signal to remove to drive loudspeaker or loudspeaker the data-switching in voice driven register 104, through the time of being determined by speech sample rate, read again second data, so constantly repeat, can hear corresponding voice from loudspeaker or loudspeaker.As mentioned above, whole speech play process all needs CPU core 101 not stop to write out voice address, reads speech data, processed voice data are written out to voice driven register 104 again and judge that whether voice finish, and waste cpu resource and program resource very much.The advantage of this control chip is that voice coding/decoding algorithms is realized by software, so more flexible.But its shortcoming is also apparent, as: (1) speech memory is generally 8 bit wides, and CPU core is also 8, adopts the instruction encoding bit wide of 16, causes chip area bigger than normal, high expensive; (2) phonetic algorithm is realized by software, take program memory space and CPU working time, while being unfavorable for playing voice, process other processes, to the calculating of sampling rate, also will increase in addition a timer simultaneously, and allow CPU enter speech processes program in modes such as interruptions, increased system resource, and the sampling rate calculating is also accurate not, if phonetic algorithm is too complicated, required procedure quantity is too large, may also can cause voice output speed inhomogeneous, affect sound effect; (3) there is no voice operating instruction, the control of voice is passed through to the realization to the operation of the corresponding positions of corresponding special function register, and normally unaddressable position, these positions, so easily cause maloperation, the also bad judgement of end of voice simultaneously; (4) with software, realize phonetic algorithm, make the Application Engineer must self-developing phonetic algorithm and organize speech data to be written in speech memory, increased the design difficulty of program development difficulty and developing instrument; (5) generally this quasi-controller all lacks LCD driver module, has dwindled range of application.

In order adapting to the functional new needs of intelligent toy, and to provide the intelligent toy of low cost and low-power consumption, to need a kind of novel Intelligent toy control chip.

Summary of the invention

One object of the present invention is, a kind of control chip is provided, and this control chip comprises the voice module that can be independent of CPU operation, so that during voice module operation, CPU can process other processes simultaneously, significantly improves the work efficiency of CPU.

The invention provides a kind of 4 digit RISC micro controllers, comprise control module, program storage, register file, reseting module, clock module and at least one peripheral functional modules, it is characterized in that,

This control module comprises order register, command decoder, and storehouse, arithmetic logic unit alu, and programmable counter, it adopts secondary two-phase pipelined architecture;

Program storage is used for storing one-cycle instruction and binary cycle instruction, each one-cycle instruction takes out next instruction when carrying out instruction, the first instruction cycle of each binary cycle instruction is taken out next instruction when carrying out instruction, the instruction fetch again when carrying out instruction of its second instruction cycle, each instruction cycle is divided into first-phase and second-phase

At described first-phase, control module completes that storehouse is stacked, program storage reads, register read, Instruction decoding and ALU arithmetic operation,

At described second-phase, control module completes that storehouse ejects, order register latchs, register writes, programmable counter rewriting operation.

Preferably, this microcontroller architecture comprises a set of reduced instruction set computer with 49 instructions, and the signal of described command decoder output comprises:

The instruction of register manipulation class, command decoder output register address information and read-write operation signal are to register file, and output s operation control signal is to ALU;

Immediate instruction, command decoder output immediate and s operation control signal are to ALU;

The instruction of program jump class and interruption, command decoder written-out program address information and redirect control signal are to programmable counter, and output storehouse control signal is to storehouse, and output is interrupted control signal to interrupt handler;

Control class instruction, command decoder is exported various control signals to functional module or corresponding peripheral functional modules;

Peripheral functional modules steering order, command decoder output peripheral functional modules steering order is for controlling and detect the work of voice module.

Preferably, described program storage is that 15 bit wides are for depositing the program storage of order code.

Preferably, described at least one peripheral functional modules comprises voice module.

Preferably, described register file comprises for depositing the voice address register of voice initial address and for depositing the sampling rate register of speech sample rate,

Described voice module comprises voice address generator, sample frequency frequency divider, and speech memory, Voice decoder, voice driven module and speech control module,

Described speech control module is according to the enabling signal from control module, clock signal, and described voice initial address and speech sample rate are controlled voice module output voice driven signal.

Preferably, described sample frequency frequency divider produces sampling rate signal according to clock signal and described speech sample rate, and exports to voice address generator;

Described voice address generator produces the address of speech memory according to described initial address and described sampling rate signal;

Described Voice decoder is decoded to the coded voice data from speech memory, and the speech data of output decoding is to voice driven module, and when voice finish end of output sign;

Described speech control module is exported voice end signal to control module according to the end mark from Voice decoder.

Preferably, described clock module comprises quick oscillation device, oscillator and timing generator at a slow speed, and described control module comprises mode of operation processor, for controlling clock module clock signal according to following four kinds of chip operation patterns:

When chip operation is during in normal mode, clock module is usingd the output of oscillator at a slow speed as the work clock of control module;

When chip operation is during in quick mode, clock module is usingd the output of quick oscillation device as the work clock of control module;

When chip operation is during in park mode, clock module stops the work clock of control module;

When chip operation is during in park mode, clock module stops clock and exports and close quick oscillation device and oscillator at a slow speed.

Preferably, described at least one peripheral functional modules comprises LCD driver module, and described register file comprises for controlling the LCD control register of LCD driver module work and for storing the LCD RAM that shows data.

Preferably, speech memory is 4 bit memories.

Preferably, described voice module receives the clock signal from quick oscillation device.

Preferably, when voice module is not worked and when chip is not worked with quick mode, clock module is closed quick oscillation device.

The present invention further provides a kind of toy, this toy comprises the control chip of Harvard as above framework.

Voice module in the present invention, comprise voice address generator, speech memory, ADPCM Voice decoder, PWM, DAC, sample frequency frequency divider and speech control module, under the triggering of cpu instruction PVOX, decoding, broadcasting and the detection of end that can automatically complete voice, completely no longer need the intervention of CPU.

Another object of the present invention is to provide a kind of 4 novel digit RISC micro controllers, to solve chip cost, phonetic algorithm, take the program space and CPU processing time, speech sample rate out of true and affect the problems such as sound effect, development difficulty are large, and increased LCD driver module, to be more suitable for actual needs.

The solution of the present invention comprises the peripheral functional modules such as CPU core, program storage, register file, reseting module, clock module and voice module, LCD driver module and I/O of 4 RISC frameworks.

The CPU core of 4 RISC frameworks that the present invention includes, comprises mode of operation processor, interrupt handler, storehouse, programmable counter, order register, command decoder and arithmetic logic unit alu, has used a secondary two-phase pipelined architecture.Each instruction cycle takes out next instruction when carrying out instruction.Each instruction cycle is divided into Q1 and Q2 two-phase, more fast again than the travelling speed of the RISC microcontroller of general four phases.In Q1 phase, CPU core completes the actions such as storehouse is stacked, instruction fetch, register read, ALU computing.In Q2 phase, complete the actions such as storehouse ejection, order register latch instruction, register write, programmable counter rewriting.

Register file in the present invention, comprise the special function register that d type flip flop forms, the LCD display data memory that the conventional data storer that single-ended asynchronous static RAM forms and the asynchronous static RAM of both-end form, its address is mapped in unified logical address by address mapping circuit.

According to Intelligent toy control chip of the present invention, adopt RISC order set, comprise 49 powerful instructions, these instructions have following features:

A. long word instruction, instruction width is 15;

B. single-word instruction, every instruction all accounts for the coding of 15, and program storage is also 15 bit wides, so all program memory cell is all effective instruction, has avoided program storage waste;

C. one-cycle instruction, except jump instruction, call instruction and link order are binary cycle instruction, other instructions are all one-cycle instructions, each instruction cycle is two oscillation period;

D. symmetry, instruction encoding is strictly symmetrical, makes instruction study become simple;

E. compressed encoding, simplifies and compresses instruction encoding, and coding only has 15 bit wides.

The operation of control chip instruction of the present invention adopts two-level pipeline structure, and the operational process of every instruction can be divided into instruction fetch and carry out two stages of instruction, and each stage all needs the working time of an instruction cycle.Control chip of the present invention is used Harvard's framework, the framework that program storage and data-carrier store separate, and the access of program and the access of data can be carried out simultaneously, make the extract operation of different instruction and executable operations also can carry out simultaneously.Such as one-cycle instruction, when instruction 0 is carried out, instruction 1 is removed, when the next instruction cycle arrives, instruction 1 is performed, and instruction 2 is simultaneously removed, although so see separately, every instruction all needs two instruction cycles, on average get off and only need an instruction cycle.When executive routine transfer instruction or interruption, because will rewrite programmable counter, so need to add an instruction cycle, be again written into new instruction.

In instruction set of the present invention, comprise 19 arithmetical logic instructions, to the data in totalizer and register file add, subtract, with or, XOR, negate, add 1, subtract 1 arithmetic logical operation, operation result can be kept to totalizer and/or deposit back register file.

Arithmetical logic instruction in instruction set of the present invention, comprises the arithmetical logic instruction that 9 results leave totalizer in, and its operation result is not deposited back register file.

Arithmetical logic instruction in instruction set of the present invention, comprises the arithmetical logic instruction that 10 results are deposited back register file, and its operation result not only leaves totalizer in, but also deposits back register file.

Arithmetical logic instruction in instruction set of the present invention, comprises 4 full adds, subtracts instruction.

In instruction set of the present invention, comprise the instruction of 2 data transmission classes, the data transmission of register file to totalizer or the data transmission of totalizer to register file.

In instruction set of the present invention, comprise 7 immediate instructions, immediate be transferred to totalizer or immediate and accumulator data add, subtract, with or, XOR, result leaves totalizer in.

In instruction set of the present invention, comprise 2 decimal adjust instructions, leaving binary data in totalizer after addition, subtraction operation in, be adjusted to the decimal system, result leaves totalizer in.

In instruction set of the present invention, comprise 2 band carry shift orders, totalizer and carry storage register are carried out to ring shift left or ring shift right.

In instruction set of the present invention, comprise 12 program transfer commands, by the value of reprogramming counter, carry out the transfer of control program.

Program transfer command in instruction set of the present invention, comprises a routine call instruction CALL, is used for call subroutine.

Program transfer command in instruction set of the present invention, comprises 1 unconditional jump instruction JUMP, is used for making program unconditional jump to destination address.

Program transfer command in instruction set of the present invention, comprise 4 condition jump instruction JZ, JNZ, JC and JNC, by judge totalizer be whether zero or carry flag be whether 1 as condition, condition makes program jump to destination address while setting up, and carries out next instruction while being false.

Program transfer command in instruction set of the present invention, comprises 2 condition skip instruction SKZ and SKNZ, by judging whether a certain position of totalizer is zero as condition, and condition makes program skip next instruction while setting up, and carries out next instruction while being false.

Program transfer command in instruction set of the present invention, comprises 2 link order RET and RETI, and RET returns from subroutine or interrupt routine, and RETI returns and opens and interrupts enabling from interrupt.

Program transfer command in instruction set of the present invention, comprise 2 tables of data look-up commands, make instruction from the tables of data of program storage, search data, wherein TJUMP instruction jumps to look-up table place, and RETW reads in the data of look-up table totalizer and lookup table register and returns.

In instruction set of the present invention, comprise 3 steering orders, for CPU or other peripheral modules are controlled.

Steering order in instruction set of the present invention, comprises 1 pause instruction HALT, carries out this instruction, can make chip enter park mode, the break-off of CPU core, and other peripheral functional modules are unaffected.

Steering order in instruction set of the present invention, comprises 1 watchdog zero clearing instruction CLRWDT, is used for zero clearing house dog counter.

Steering order in instruction set of the present invention, comprises 1 non-operation instruction NOP, and any action is not done in this instruction.

In instruction set of the present invention, comprise 2 voice class instructions, for controlling and detect the work of voice module.

Voice class instruction in instruction set of the present invention, comprises 1 speech play instruction PVOX, for starting voice module, makes it start to play voice.

Voice class instruction in instruction set of the present invention, comprises 1 voice and finishes jump instruction JVEND, for the end signal that voice module is returned, detects, once voice end signal be detected, jumps to destination address.

Control chip of the present invention, except adopting four bit CPU kernels of RISC framework, also integrated voice module.Like this, the decoding of voice and broadcasting are all independent of outside CPU, and CPU can do other work when playing voice, has strengthened the service efficiency of CPU in control chip.Meanwhile, owing to there being special-purpose tone decoding hardware circuit, do not need programmer to write software decode, reduced the development difficulty of application yet.Adopt control chip of the present invention, instruction set also only needs to adopt the code width of 15, when keeping arithmetic capability and operation efficiency, saved the program's memory space of 1, voice Stand Alone Memory can only have 4 bit wides simultaneously, so all reduced chip production cost and cost of development, and made the miniaturization of control chip become possibility.

Control chip according to the present invention is applied to intelligent toy, can in the speech play effect that improves intelligent toy, significantly reduces production cost and the cost of development of existing voice toy.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, with reference to the preferred embodiments of the present invention, the features and advantages of the invention are elaborated, wherein,

Fig. 1 illustrates the structured flowchart of the conventional toy control chip of prior art;

Fig. 2 illustrates according to the structured flowchart of toy control chip of the present invention;

Fig. 3 illustrates the functional block diagram of control chip shown in Fig. 2;

Fig. 4 illustrates the one-cycle instruction streamline schematic diagram of control chip shown in Fig. 2;

Fig. 5 illustrates the binary cycle instruction pipelining schematic diagram of control chip shown in Fig. 2;

Fig. 6 illustrates according to register file addresses of the present invention and distributes schematic diagram;

Fig. 7 illustrates according to voice module structured flowchart of the present invention.

Embodiment

Fig. 2 illustrates according to a kind of structured flowchart that can be used for the control chip of toy of the present invention.Control chip according to the present invention comprises that reseting module 208, clock module 209, program storage 210, CPU core 211, register file 212, timer group 216, I/O interface 217, voice module 218 and LCD drive 219, and wherein register file 212 comprises special function register 213, conventional data RAM214 and LCD RAM215.

Fig. 3 illustrates a kind of concrete functional block diagram of the control chip that can be used for toy shown in Fig. 2.Below in conjunction with Fig. 2 and Fig. 3, each functional module in the control chip according to the present invention is elaborated.

Reseting module 208 in the control chip of the present embodiment is shown in Figure 3 for reseting module 308.This reseting module 308 for example comprises external reset circuit 360, electrify restoration circuit 320, low-voltage reset circuit 321, watchdog circuit 322 and reseting signal generator 323.External reset circuit 360 provides external reset signal.Electrify restoration circuit 320 provides power-on reset signal.The low-voltage threshold of low-voltage reset circuit 321 can arrange, when supply voltage output LOW voltage reset signal during lower than this threshold voltage.Watchdog circuit 322 is for example a selectable counter of counting clock, and clock, from clock module 309, is exported a spill over to reseting signal generator 323 when counting overflows, and this counter can be used instruction CLRWDT zero clearing.Watchdog reset is for making system return from the state of program fleet.The output signal of above four modules enters reseting signal generator 323, obtains final global reset signal after the processing such as time delay, exports to other modules in control chip.Therefore control chip has four kinds of reset modes: electrification reset, voltage reset, external reset and house dog counting overflow reset, to adapt to multiple application demand, whether wherein low-voltage resets and house dog counting overflowing that to reset be optional, can enable according to the security requirement selection of application.

Clock module 309 in the control chip of the present embodiment comprises quick oscillation device 324, oscillator 325 and clock generator 326 at a slow speed, for whole chip provides work clock.Oscillator 325 can be selected the crystal oscillator of 32768Hz or the RC of 256KHz vibration at a slow speed.Quick oscillation device 324 is RC vibrations of 2MHz.The output of two oscillators, through frequency division and the processing of clock generator 326, finally generates the needed clock signal of modules.The output of clock module 309 is subject to the control of mode of operation processor 327, and when chip operation is during in normal mode, clock module 309 selects the output of oscillator 325 at a slow speed as the work clock of CPU core 311; When chip operation is during in quick mode, clock module 309 selects the output of quick oscillation devices 324 as the work clock of CPU core 311; When chip operation is during in park mode, clock module 309 stops the work clock of CPU core 311, and timer group 316, voice module 318 and LCD drive 319 clock to continue to provide; When chip operation is during in park mode, clock module 309 stops all clocks outputs, and closes vibration.The clock source of voice module 318 comes from quick oscillation device 324, when voice module 318 is not worked and when chip is not operated in quick mode, clock module 309 is closed quick oscillation device 324.Mode of operation management according to the present invention can reduce the power consumption of chip significantly.

Program storage 310 in the control chip of the present embodiment is for example the ROM of a 16K * 15BITS, for depositing order code, about the details of order code, asks for an interview below instruction encoding part.Program storage in control chip of the present invention adopts the program storage of 15 bit wides, and effectively saving chip area, makes the further miniaturization of control chip become possibility.

CPU core 311 in the toy control chip of the present embodiment is kernel control modules of chip, and data bit width is four.CPU core, in this article also referred to as control module, comprises mode of operation processor 327, interrupt handler 328, storehouse 329, programmable counter 330, order register 331, command decoder 332 and arithmetic logic unit alu 333.CPU core 311 adopts secondary two-phase pipelined architecture, and each instruction cycle takes out next instruction when carrying out instruction.Each instruction cycle is divided into Q1 and Q2 two-phase, more fast again than the travelling speed of the RISC microcontroller of general four phases.In Q1 phase, complete the actions such as stacked, fetching, register read, ALU computing.In Q2 phase, complete pop, the action such as latch instruction, register write, programmable counter variation.

Be included in the mode of operation processor 327 in the CPU core 311 of control chip, detect the mode of operation of control chip.The present embodiment provides for example four kinds of mode of operations: normal mode, quick mode, park mode and park mode.When the position of the control mode of operation in other SFR334 in the special function register 313 in register file 312 is set up, chip enters certain mode of operation, mode of operation processor 327 output control signals, control the work of clock module 309, specifically please refer to the introduction of clock module 309.

Be included in the interrupt handler 328 in the CPU core 311 of control chip, be responsible for the interruption item of process chip.Control chip of the present invention provides for example four kinds of interruptions: external interrupt, timer T overflow interruption, time base timer overflow and interrupt and voice end interrupt, it is interrupt vector that each interruption has independent fixing entry address.Some registers in other SFR334 in special function register 313 in register file 312 are controlled enabling and interrupt identification of interrupting.When an interrupt occurs, respective interrupt flag set, interrupt handler 328 output control signals, are pressed into storehouse 329 the currency of programmable counter 330, interrupt vector write-in program counter 330.When returning from interruption, interrupt handler 328 produces control signals, ejects address date write-in program counter 330 from storehouse 329.

Be included in storehouse 329 in the CPU core 311 of control chip and be for example the belt storehouse of 16 grades, 14, when carrying out call instruction and response interruption, the currency of programmable counter 330 is pressed into, when carrying out link order, the value that is finally pressed into storehouse is ejected to programmable counter 330.

For example be included in programmable counter 330 in the CPU core 311 of control chip and be 14 can prevalue up counter, during reset, be zero, addressable is the program storage 310 of 16K for example.During operation general procedure, programmable counter 330 as shown in Figure 4, automatically adds 1 when the clock Q2 of each instruction cycle finishes mutually.When moving for example CALL, JUMP, JZ, JNZ, JC, JNC, SKZ, SKNZ, TJUMP, RET, RETI, when RETW or JVEND supervisor transfer instruction and/or generation are interrupted, programmable counter 330 as shown in Figure 5, divide page information the address of command decoder 332 output with the program in other SFR334 in special function register 313 in register file 312 when the Q2 of instruction cycle T2 finishes mutually together with, be written into, now programmable counter 330 needs an extra instruction cycle T3 to carry out instruction fetch again, so these CALL, JUMP, JZ, JNZ, JC, JNC, SKZ, SKNZ, TJUMP, RET, RETI, RETW and JVEND instruction are called as binary cycle instruction, its implementation is as shown in the T2 of Fig. 5 and T3 cycle.

Be included in order register 331 in the CPU core 311 of control chip for depositing the order code of taking out from program storage 310, and export to command decoder 332 and carry out decoding.

The command decoder 332 being included in the CPU core 311 of control chip is responsible for the instruction in order register 331 to carry out decoding, and instruction translation is become to corresponding control action, exports corresponding control signal, control chip operation.The output signal of command decoder 332 has following a few class: to the instruction of register manipulation class, command decoder 332 output register address information and read/write operation signal are to register file 312, and output s operation control signal is to arithmetic logic unit alu 333; To immediate instruction, output immediate and s operation control signal are to arithmetic logic unit alu 333; To the instruction of program jump class and interruption, written-out program address information and redirect control signal are to programmable counter 330, and output storehouse control signal is to storehouse 329, and output is interrupted control signal to interrupt handler 328; To controlling class instruction, export various control signals to correlation modules such as mode of operation processor 327, voice module 318 or reseting modules 308.

Being included in the ALU333 in the CPU core 311 of control chip, is the ALU of four for example, can complete add, subtract, with or, the computing such as XOR, negate, displacement, also can only transmit data.In ALU333, also comprise a totalizer, be used for latching operation result.Command decoder 332 output s operation control signals, control the computing of ALU333.In the Q1 of instruction cycle phase, the reading out data row operation of going forward side by side from register file 312, and latch operation result; In the Q2 of instruction cycle phase, operation result is write back in register file 312.Some registers in other SFR334 in special function register 313 in register file 312 are deposited the Status Flag of ALU, as carry flag, zero flag etc.

Register file 312 in the control chip of the present embodiment comprises special function register (SFR) 313, conventional data RAM314 and LCD RAM315.Register file 312 can, by 311 read-writes of CPU core, be carried out exchanges data by data bus and ALU333.Special function register 313, conventional data RAM314 and LCD RAM315 are different data registers, the mode of shining upon by address is mapped to their address in same set of logical address, form thus register file 312, their address mapping relation is with reference to figure 6.

Being included in the special function register 313 in the register file 312 of control chip, d type flip flop, consisting of, is all some registers with specific function, and CPU core 311 can be realized the control to peripheral functional modules by these registers.For example, special function register 313 comprises LCD control register 339, for controlling LCD, drives 319 work; Voice address register 338, for depositing the initial address of voice, outputs to voice module 318; Sampling rate register 337, for depositing the sampling rate of voice, outputs to voice module 318; I/O register 336, for depositing input-output data and the I/O direction control bit of I/O, wherein the input of part I/O can also be exported to interrupt handler 328 to judge whether to enter external interrupt; Timer register 335, for depositing clock selecting position, enable bit and the counting overflow indicator of timer group 316, wherein overflow indicator is exported to interrupt handler 328 to judge whether to enter interruption; Other SFR334, comprise status register, interrupt control register, mode of operation register, vibration mask register etc., do not list one by one, can have for example 45 special function registers.

The conventional data RAM314 being included in the register file 312 of control chip is single-ended asynchronous static RAM (SRAM), and total for example 480 * 4BITS, as conventional data storer.

The LCD RAM315 being included in the register file 312 of control chip is the asynchronous static RAM (SRAM) of both-end, be used for storing LCD and show data, one in two port for CPU core 311 read operations, another drives 319 for output display data to LCD, does not affect LCD when guaranteeing that CPU core 311 operates to show.LCD RAM315 also can be used as general data storer and uses when being not used in storage LCD demonstration data.

Timer group 316 in the control chip of the present embodiment comprises timer T340 and Shi Ji timer 341.

Be included in the timer T340 in the timer group 316 of control chip, be for example one can prevalue, 8 down counters of heavy duty automatically, counting clock is selected by corresponding SFR, while counting down to zero, produce spill over and trigger the interrupt identification in special function register 313, and export to interrupt handler 328 to judge whether to enter interruption.

Be included in the time base timer 341 in the timer group 316 of control chip, for example 8 digit counters, counting clock is selected by corresponding SFR, counting produces spill over and triggers the interrupt identification in special function register 313 while overflowing, and exports to interrupt handler 328 to judge whether to enter interruption.

I/O port 317 in the control chip of the present embodiment for example comprises 8 independently general purpose I/O, have in addition that 4 I/O and LCD drive port to share pad, 32 delivery outlets drive port to share pad with LCD, the mask option in the time of can be by chip production is selected as I/O(or delivery outlet) or LCD driving port.

Voice module 318 in the control chip of the present embodiment, the function that voice storage is provided and has play, its functional module and work please refer to Fig. 7.Voice module 318 obtains voice initial address from voice address register 338, obtains speech sample rate parameter from sampling rate register 337, from clock module 309, obtains work clock.Once the voice module in control chip of the present invention is triggered by instruction PVOX, will automatically play voice, whole playing process no longer needs the interference of CPU core 311, do not take any cpu resource and program resource, voice finish rear automatic generation end signal and export to CPU core 311, and CPU core 311 is reacted in modes such as interruption or JVEND instructions.

LCD driver module 319 in the control chip of the present embodiment, for driving LCD display, controls its work by LCD control register 339, and from LCD RAM315, obtains demonstration data.The present embodiment provides for example LCD of 36SEG * 4COM, 1/3 bias voltage, 3V driving voltage to drive 319, can meet most of intelligent toy application.

Fig. 4 illustrates the one-cycle instruction streamline schematic diagram of control chip shown in Fig. 2.Control chip takes out next instruction when carrying out instruction.For example, at instruction cycle T2, control chip takes out next instruction PC+1 when carrying out instruction PC.When next instruction cycle T 3 arrives, control chip is carried out instruction PC+1, takes out instruction PC+2 simultaneously.According to control chip of the present invention, other instructions except program transfer command are all one-cycle instructions.Each instruction cycle is divided into Q1 and Q2 two-phase.In Q1 phase, complete the actions such as stacked, fetching, register read, ALU computing.In Q2 phase, complete pop, the action such as latch instruction, register write, programmable counter variation.

Fig. 5 illustrates the binary cycle instruction pipelining schematic diagram of control chip shown in Fig. 2.Control chip, when carrying out binary cycle instruction or interrupting, destination address loader counter, and additionally increases an instruction cycle T3 and carrys out instruction fetch again when the Q2 of instruction cycle T2 finishes mutually.For example, at instruction cycle T1, control chip fill order cycles per instruction PC0-1 also takes out next instruction PC0.This instruction PC0 is binary cycle instruction.At instruction cycle T2, control chip is carried out instruction PC0, and as usual takes out in order instruction PC0+1, but because PC0 is binary cycle instruction, so do not carry out instruction PC0+1 when instruction cycle T3 arrives, but also carrying out PC0, and take out the instruction PC1 of destination address.At instruction cycle T4, carry out instruction PC1 and take out next instruction PC1+1.

Fig. 6 illustrates according to register file addresses of the present invention and distributes schematic diagram.The mode of shining upon by address is mapped to the address of special function register, conventional data storer and LCD display data memory in same set of logical address.For example wherein address is special function register from 000H to 03FH, from 080H to 0A3H, is LCD display data memory, is conventional data storer from 100H to 1FFH and from 300H to 3DFH.LCD display data memory can be used as general data storer and uses when LCD module is not used.

Fig. 7 illustrates according to voice module structured flowchart of the present invention.Voice module according to the present invention comprises voice address generator 742, speech memory 743, ADPCM Voice decoder 744, PWM745 or DAC746, sample frequency frequency divider 747 and Speech Control Logic 748.Voice address generator 742 be for example one can prevalue 17 up counters, the address of being responsible for producing speech memory 743.The voice address register 338 of Speech Control Logic 748 from register file 312 obtains the start address of one section of voice and is written into counter, and the sampling rate signal that the sample frequency frequency divider 747 of take provides is counting clock Auto-counting, until voice finish.Speech memory 743 is for example the storer of a 96K * 4BITS, and storage ADPCM voice scrambling coding can be stored some sections of voice simultaneously, and the data on the address that voice address generator 742 is provided are exported to ADPCM Voice decoder 744.Whether the data that the responsible ADPCM quantization encoding four of ADPCM Voice decoder 744 is decoded into the PCM form of eight are exported to PWM745 or DAC746, and automatically detect voice and finish.PWM745 or DAC746 are responsible for that the speech data of PCM form is converted to corresponding loudspeaker and drive signal.Although in Fig. 7, illustrated voice module comprise PWM745 and DAC746 the two, at PWM and DAC, can only select one of them by the mask option of production run, control module selects PWM or DAC as voice driven module.Sample frequency frequency divider 747 is one of features of the present invention, and it,, according to high-frequency clock being carried out to frequency division from the sampling rate parameter in sampling rate register 337 in register file 312, obtains corresponding sampling rate signal and export to voice address generator 742.Sampling rate frequency divider for example can provide 2KHz～64KHz, such as the different phonetic sampling rate of 6KHz, 8KHz, 12KHz, 16KHz, thereby has improved the dirigibility of developing.Speech Control Logic 748 is responsible for controlling the operation of whole voice module.The operational process of voice module of the present invention is as follows: during chip power, Speech Control Logic 748 is resetted by global reset signal, when CPU receives PVOX instruction, to voice module output enabling signal, after Speech Control Logic 748 is received enabling signal, start to enable, PWM745 or DAC746 open, and distribute high-speed clock signal to sample frequency frequency divider 747, sample frequency frequency divider 747 carries out frequency division according to the sampling rate parameter in the sampling rate register 337 in register file 312 to high-frequency clock, obtain corresponding sampling rate signal, in the voice address register 338 of voice address generator 742 from register file 312, be written into voice start address, start speech memory 743 addressing, four ADPCM quantization encodings of speech memory 743 outputs, ADPCM Voice decoder 744 is decoded into ADPCM quantization encoding that the PCM speech data of eight is exported to PWM745 or DAC746 removes to drive loudspeaker, whether and detecting voice finishes, if voice do not finish, voice address generator 742 adds 1, the next data of speech memory 743 output, ADPCM Voice decoder 744 is decoded again, PWM745 or DAC746 export again, so constantly circulation, if voice finish, an end mark of ADPCM Voice decoder 744 outputs, exports to CPU core 311 after Speech Control Logic 748 latchs, and CPU core 311 can be reacted accordingly.So can find out, whole speech play process is all that voice module automatically completes, and does not take any cpu resource and program resource.

Instruction

The present embodiment is supported the typical instructions of common RISC microcontroller, such as arithmetical logic instruction, program transfer command etc., all instructions employing bit wides are the coded system of 15, for chip has been saved the program storage of, and don't too much weaken the ability of instruction.

The operation of the instruction of the present embodiment adopts pipeline system, and most of instruction is all one-cycle instruction, and only having program transfer command is binary cycle instruction.Be a machine cycle (T) two oscillation period (Q1 phase and Q2 phase), and an instruction cycle is one or two machine cycle.The execution of one-cycle instruction as shown in Figure 4, is taken out next instruction when carrying out present instruction.The execution of binary cycle instruction as shown in Figure 5, need to increase a machine cycle so that CPU fetching from new destination address.

In the present embodiment, all instructions are all single-length, and every instruction accounts for 1 program memory address.According to decoding, can be divided into immediate addressing, directly address, register indirect addressing and four kinds of addressing modes of tables of data addressing.Wherein tables of data addressing mode realizes by two special-purpose instructions, TJUMP and RETW.When programming, Application Engineer can be left some fixed datas in program storage in RETW, as data look-up table, then jumps to this look-up table with TJUMP instruction, carries out RETW these data are read in totalizer ACC and lookup table register TBL.

49 altogether of instructions, have contained the function needing in general application.Instruction adopts symmetrical compressed encoding, 15 bit wides.Wherein, 19 of arithmetical logic class instructions, comprise ADC, ADCM, ADD, ADDM, SBC, SBCM, SUB, SUBM, XOR, XORM, OR, ORM, AND, ANDM, CPLM, INC, INCM, DEC, DECM.2 of data transmission class instructions, comprise LDA, STA.7 of immediate instructions, comprise LDI, ADI, SBI, SBIA, XORI, ORI, ANDI.2 of decimal adjust instructions, for adjusting decimal number signed magnitude arithmetic(al) result afterwards, comprise DAA, DAS.2 of shift orders, comprise RORC, ROLC.12 of program transfer commands, comprise CALL, JUMP, JZ, JNZ, JC, JNC, SKZ, SKNZ, RET, RETI, RETW, TJUMP.3 of steering orders, comprise pause instruction HALT, watchdog zero clearing instruction CLRWDT, non-operation instruction NOP.2 of voice class instructions, comprise that speech play instruction PVOX, voice finish jump instruction JVEND.Wherein PVOX instruction is play specially voice and is used, if CPU has taken out PVOX instruction, after command decoder decoding, export an enabling signal to voice module, triggered voice, made voice module play the voice from starting with the definite address of voice address register with the definite sampling rate of sampling rate register.And after voice finish, returning to an end signal, CPU enters interruption, or with JVEND, this signal is detected, once voice end signal be detected, jumps to destination address.

It is below instruction set of the present invention.

Operand explanation

Instruction set is described

ADC

Function: full add method instruction.Storer (Mx) content, carry flag (CF) and totalizer (ACC) content are added, and result is returned and is deposited in totalizer (ACC), and operation result affects carry flag bit, have carry CF to be set as 1, otherwise CF is set as 0.

Form: ADC Mx

Equation: ACC ← Mx+ACC+CF

Instruction cycle: 1

ADCM

Function: full add method is also returned and deposited storer.Storer (Mx) content, carry flag (CF) and totalizer (ACC) content are added, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result affects carry flag bit, have carry CF to be set as 1, otherwise CF is set as 0.

Form: ADCM Mx

Equation: ACC, Mx ← Mx+ACC+CF

Instruction cycle: 1

ADD

Function: not full add method instruction.Storer (Mx) content and totalizer (ACC) content are added, and result is returned and is deposited in totalizer (ACC), and operation result affects carry flag bit, have carry CF to be set as 1, otherwise CF is set as 0.

Form: ADD Mx

Equation: ACC ← Mx+ACC

Instruction cycle: 1

ADDM

Function: full add method is not also returned and deposited storer.Storer (Mx) content and totalizer (ACC) content are added, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result affects carry flag bit, have carry CF to be set as 1, otherwise CF is set as 0.

Form: ADDM Mx

Equation: ACC, Mx ← Mx+ACC

Instruction cycle: 1

SBC

Function: band borrow subtraction instruction.Storer (Mx) content is deducted to totalizer (ACC) content, then deduct anti-phase carry flag (CF), result is returned and is deposited in totalizer (ACC), and operation result affects carry flag bit, and when subtraction produces borrow, CF is set as 0, otherwise CF is set as 1.

Form: SBC Mx

CF

Instruction cycle: 1

SBCM

Function: band borrow subtraction also returns and deposits storer.Storer (Mx) content is deducted to totalizer (ACC) content, deduct anti-phase carry flag (CF), result is returned and is deposited in totalizer (ACC) and storer (Mx) again, and operation result affects carry flag bit, when subtraction produces borrow, CF is set as 0, otherwise CF is set as 1.

Form: SBCM Mx

CF

Instruction cycle: 1

SUB

Function: be not with borrow subtraction instruction.Storer (Mx) content is deducted to totalizer (ACC) content, and result is returned and is deposited in totalizer (ACC), and operation result affects carry flag bit, and when subtraction produces borrow, CF is set as 0, otherwise CF is set as 1.

Form: SUB Mx

Equation: ACC ← Mx-ACC

Instruction cycle: 1

SUBM

Function: be not with borrow subtraction and return and deposit storer.Storer (Mx) content is deducted to totalizer (ACC) content, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result affects carry flag bit, and when subtraction produces borrow, CF is set as 0, otherwise CF is set as 1.

Form: SUBM Mx

Equation: ACC, Mx ← Mx-ACC

Instruction cycle: 1

XOR

Function: step-by-step XOR instruction.Storer (Mx) content and totalizer (ACC) content are made to XOR, and result is returned and is deposited in totalizer (ACC), and operation result does not affect zone bit.

Form: XOR Mx

Equation:

Instruction cycle: 1

XORM

Function: step-by-step XOR also returns and deposits storer.Storer (Mx) content and totalizer (ACC) content are made to XOR, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result does not affect zone bit.

Form: XORM Mx

Equation: ACC,

Instruction cycle: 1

OR

Function: step-by-step or instruction.Storer (Mx) content and totalizer (ACC) content are made to exclusive disjunction, and result is returned and is deposited in totalizer (ACC), and operation result does not affect zone bit.

Form: OR Mx

Equation: ACC ← Mx|ACC

Instruction cycle: 1

ORM

Function: step-by-step or and return and to deposit storer.Storer (Mx) content and totalizer (ACC) content are made to exclusive disjunction, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result does not affect zone bit.

Form: ORM Mx

Equation: ACC, Mx ← Mx|ACC

Instruction cycle: 1

AND

Function: step-by-step and instruction.Storer (Mx) content and totalizer (ACC) content are done and computing, and result is returned and is deposited in totalizer (ACC), and operation result does not affect zone bit.

Form: AND Mx

Equation: ACC ← Mx & ACC

Instruction cycle: 1

ANDM

Function: step-by-step with and return and to deposit storer.Storer (Mx) content and totalizer (ACC) content are done and computing, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result does not affect zone bit.

Form: ANDM Mx

Equation: ACC, Mx ← Mx & ACC

Instruction cycle: 1

CPLM

Function: storer step-by-step negate is also returned and deposited.Storer (Mx) content is read to totalizer (ACC), step-by-step negate, result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result does not affect zone bit.

Form: CPLM Mx

Equation: ACC, Mx ←! Mx

Instruction cycle: 1

INC

Function: memory increments instruction.Storer (Mx) content is added to 1, and result is deposited in totalizer (ACC), and operation result affects carry flag bit, have carry CF to be set as 1, otherwise CF is set as 0.

Form: INC Mx

Equation: ACC ← Mx+1

Instruction cycle: 1

INCM

Function: memory increments is also returned and deposited.Storer (Mx) content is added to 1, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result affects carry flag bit, have carry CF to be set as 1, otherwise CF is set as 0.

Form: INCM Mx

Equation: ACC, Mx ← Mx+1

Instruction cycle: 1

DEC

Function: the storer instruction of successively decreasing.Storer (Mx) content is deducted to 1, and result is deposited in totalizer (ACC), and operation result affects carry flag bit, have borrow CF to be set as 0, otherwise CF is set as 1.

Form: DEC Mx

Equation: ACC ← Mx-1

Instruction cycle: 1

DECM

Function: storer successively decreases and returns and deposit.Storer (Mx) content is deducted to 1, and result is returned and is deposited in totalizer (ACC) and storer (Mx), and operation result affects carry flag bit, have borrow CF to be set as 0, otherwise CF is set as 1.

Form: DECM Mx

Equation: ACC, Mx ← Mx-1

Instruction cycle: 1

LDA

Function: to totalizer (ACC), transmitting result does not affect zone bit by storer (Mx) delivery of content.

Form: LDA Mx

Equation: ACC ← Mx

Instruction cycle: 1

STA

Function: to storer (Mx), transmitting result does not affect zone bit by totalizer (ACC) delivery of content.

Form: STA Mx

Equation: Mx ← ACC

Instruction cycle: 1

LDI

Function: immediate (I) is passed to totalizer (ACC), and transmitting result does not affect zone bit.

Form: LDI I

Equation: ACC ← I

Instruction cycle: 1

ADI

Function: totalizer (ACC) content and immediate (I) are added, and result is returned and deposited in totalizer (ACC), and operation result affects carry flag bit, have carry CF to be set as 1, otherwise CF is set as 0.

Form: ADI I

Equation: ACC ← ACC+I

Instruction cycle: 1

SBIA

Function: immediate (I) is deducted to totalizer (ACC) content, and result is returned and deposited totalizer (ACC), and operation result affects carry flag bit, have borrow CF to be set as 0, otherwise CF is set as 1.

Form: SBIA I

Equation: ACC ← I-ACC

Instruction cycle: 1

SBI

Function: totalizer (ACC) content is deducted to immediate (I), and result is returned and deposited in totalizer (ACC), and operation result affects carry flag bit, have borrow CF to be set as 0, otherwise CF is set as 1.

Form: SBI I

Equation: ACC ← ACC-I

Instruction cycle: 1

XORI

Function: by totalizer (ACC) content and immediate (I) XOR, result is returned and deposited in totalizer (ACC), and operation result does not affect carry flag bit.

Form: XORI I

Equation:

Instruction cycle: 1

ORI

Function: by totalizer (ACC) content and immediate (I) exclusive disjunction, result is returned and deposited in totalizer (ACC), and operation result does not affect carry flag bit.

Form: ORI I

Equation: ACC ← ACC|I

Instruction cycle: 1

ANDI

Function: by totalizer (ACC) content and immediate (I) and computing, result is returned and deposited in totalizer (ACC), and operation result does not affect carry flag bit.

Form: ANDI I

Equation: ACC ← ACC & I

Instruction cycle: 1

DAA

Function: storer (Mx) content is done to decimal addition adjustment, and result is returned and deposited in totalizer (ACC) and storer (Mx), and adjustment mode is: if the content of storer is greater than 9 or CF=1, the content of storer is added to 6, and CF is made as to 1.Before using this instruction, must first carry out a decimal addition operation, otherwise result can be made mistakes.

Form: DAA Mx

Instruction cycle: 1

DAS

Function: storer (Mx) content is done to decimal subtraction adjustment, and result is returned and deposited in totalizer (ACC) and storer (Mx), and adjustment mode is: if the content of storer is greater than 9 or CF=0, the content of storer is added to 0AH, and CF is made as to 0.Before using this instruction, must first carry out a decimal subtraction operation, otherwise result can be made mistakes.

Form: DAS Mx

Instruction cycle: 1

RORC

Function: by totalizer (ACC) with the ring shift right of carry once.Result affects zone bit CF.

Form: RORC

Equation: CF, ACC[3:0] ACC[3:0], CF

Instruction cycle: 1

ROLC

Function: by totalizer (ACC) with the ring shift left of carry once.Result affects zone bit CF.

Form: ROLC

Equation: ACC[3:0], CF CF, ACC[3:0]

Instruction cycle: 1

CALL

Function: subroutine call instruction, operation is first saved in storehouse by PC, and stack pointer adds 1, and execution subroutine is removed in the target location that then jumps to lab appointment.

Form: CALL lab

Instruction cycle: 2

JUMP

Function: unconditional jump instruction, from current address, leap to target label and remove executive routine.

Form: JUMP lab

Instruction cycle: 2

JZ

Function: if the value of totalizer (ACC) equals 0, leap to target label and remove executive routine, otherwise continue to carry out next instruction.

Form: JZ lab

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

JNZ

Function: if the value of totalizer (ACC) is not equal to 0, leaps to target label and remove executive routine, otherwise continue to carry out next instruction.

Form: JNZ lab

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

JC

Function: if carry flag (CF) equals 1, leap to target label and remove executive routine, otherwise continue to carry out next instruction.

Form: JC lab

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

JNC

Function: if carry flag (CF) equals 0, leap to target label and remove executive routine, otherwise continue to carry out next instruction.

Form: JNC lab

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

SKZ

Function: if the I position of totalizer (ACC) equals 0, skip next instruction, otherwise carry out next instruction.

Form: SKZ I

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

SKNZ

Function: if the I position of totalizer (ACC) is not equal to 0, skip next instruction, otherwise carry out next instruction.

Form: SKNZ I

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

RETW

Function: return from subroutine; Stack pointer subtracts 1, takes out original address and return from storehouse, immediate I is passed to ACC simultaneously, and L passes to TBL.

Form: RETW L, I

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

RET

Function: return from subroutine; Stack pointer subtracts 1, takes out original address and return from storehouse.

Form: RET

Instruction cycle: 2

RETI

Function: return from interrupt service routine; Stack pointer subtracts 1, takes out original address and return from storehouse, total interrupt enable bit (IEA) is made as to 1 simultaneously.

Form: RETI

Instruction cycle: 2

TJUMP

Function: unconditional jump instruction, forms destination address by PC<13:8>, TBL and ACC.

Form: TJUMP

Instruction cycle: 2

HALT

Function: suspend MCU programmed instruction, after instruction is carried out, MCU stops carrying out instruction, but still continuation of vibration, LCD demonstration, timer and voice are unaffected, by the time have while interrupting occurring and recover normal work, to save power consumption.

Form: HALT

Instruction cycle: 1

CLRWDT

Function: zero clearing house dog counter.

Form: CLRWDT

Instruction cycle: 1

NOP

Function: non-operation instruction.

Form: NOP

Instruction cycle: 1

PVOX

Function: speech play instruction.

Form: PVOX

Instruction cycle: 1

JVEND

Function: if voice finish, leap to target label and remove executive routine, otherwise continue to carry out next instruction.

Form: JVEND lab

Instruction cycle: redirect condition is 2 while setting up, otherwise is 1

Claims

1. 4 digit RISC micro controllers, comprise control module, program storage, register file, reseting module, clock module and at least one peripheral functional modules,

At described second-phase, control module completes that storehouse ejects, order register latchs, register writes, programmable counter rewriting operation,

It is characterized in that, this microcontroller adopts a set of reduced instruction set computer with 49 instructions, and the signal of described command decoder output comprises:

To the instruction of register manipulation class, command decoder output register address information and read-write operation signal are to register file, and output s operation control signal is to ALU;

To immediate instruction, command decoder output immediate and s operation control signal are to ALU;

To the instruction of program jump class and interruption, command decoder written-out program address information and redirect control signal are to programmable counter, and output storehouse control signal is to storehouse, and output is interrupted control signal to interrupt handler;

To controlling class instruction, command decoder is exported various control signals to control module or corresponding peripheral functional modules;

To peripheral functional modules steering order, command decoder output peripheral functional modules steering order is for controlling and detect the work of voice module.

2. 4 digit RISC micro controllers as claimed in claim 1, it is characterized in that, the described reduced instruction set computer with 49 instructions comprises 19 arithmetical logic instructions, to the data in ALU and register file add, subtract, with or, XOR, negate, add 1, subtract 1 arithmetic logical operation, operation result is kept at ALU or deposits back register file.

3. 4 digit RISC micro controllers as claimed in claim 2, is characterized in that, described 19 arithmetical logic instructions comprise that arithmetical logic instruction and 10 operation results that 9 results only leave ALU in not only leave the instruction that ALU also deposits back register file in.

4. 4 digit RISC micro controllers as claimed in claim 2, is characterized in that, described arithmetical logic instruction comprises 4 full adds, subtracts instruction.

5. 4 digit RISC micro controllers as claimed in claim 1, is characterized in that, described in there are 49 instructions reduced instruction set computer comprise the instruction of 2 data transmission classes, for the data transmission of register file to ALU or the data transmission of ALU to register file.

6. 4 digit RISC micro controllers as claimed in claim 1, it is characterized in that, the described reduced instruction set computer with 49 instructions comprises 7 immediate instructions, for immediate is transferred to ALU or immediate and ALU data add, subtract, with or, XOR, result leaves ALU in.

7. 4 digit RISC micro controllers as claimed in claim 1, it is characterized in that, the described reduced instruction set computer with 49 instructions comprises 2 decimal adjust instructions, and the binary data leaving in after addition, subtraction operation in ALU is adjusted to decimal data, and result leaves ALU in.

8. 4 digit RISC micro controllers as claimed in claim 1, is characterized in that, described in there are 49 instructions reduced instruction set computer comprise 2 band carry shift orders, ALU and carry storage register are carried out to ring shift left or ring shift right.

9. 4 digit RISC micro controllers as claimed in claim 1, is characterized in that, described in there are 49 instructions reduced instruction set computer comprise the instruction of 12 program jump classes, by the value of reprogramming counter, carry out the transfer of control program.

10. 4 digit RISC micro controllers as claimed in claim 9, is characterized in that, the instruction of described program jump class comprises 1 routine call instruction CALL, are used for call subroutine.

11. 4 digit RISC micro controllers as claimed in claim 9, is characterized in that, the instruction of described program jump class comprises 1 unconditional jump instruction JUMP, are used for making program unconditional jump to destination address.

12. 4 digit RISC micro controllers as claimed in claim 9, is characterized in that, the instruction of described program jump class comprises 4 condition jump instruction JZ, JNZ, JC and JNC, condition makes program jump to destination address while setting up, while being false, carry out next instruction, wherein

Jump instruction JZ using judgement totalizer value equal zero as condition;

Jump instruction JNZ is usingd the value of judgement totalizer and is not equal to zero as condition;

Jump instruction JC is usingd carry flag and is equaled 1 as condition;

Jump instruction JNC is usingd carry flag and is equaled 0 as condition.

13. 4 digit RISC micro controllers as claimed in claim 9, it is characterized in that, the instruction of described program jump class comprises 2 condition skip instruction SKZ and SKNZ, by judging whether a certain position of ALU is zero as condition, condition makes program skip next instruction while setting up, and carries out next instruction while being false.

14. 4 digit RISC micro controllers as claimed in claim 9, is characterized in that, the instruction of described program jump class comprises 2 link order RET and RETI, and RET returns from subroutine or interrupt routine, and RETI returns and opens and interrupts enabling from interrupt.

15. 4 digit RISC micro controllers as claimed in claim 9, it is characterized in that, the instruction of described program jump class comprises 2 tables of data look-up commands, make instruction from the tables of data of program storage, search data, wherein TJUMP instruction jumps to look-up table place, and RETW instruction is read in the data of look-up table ALU and lookup table register and returns.

16. 4 digit RISC micro controllers as claimed in claim 1, is characterized in that, described in there are 49 instructions reduced instruction set computer comprise 3 and control class instruction, for control module or peripheral functional modules are controlled.

17. 4 digit RISC micro controllers as claimed in claim 16, is characterized in that, the instruction of described control class comprises 1 pause instruction HALT, carry out this instruction and make chip enter park mode, and control module break-off, each functional module is unaffected.

18. 4 digit RISC micro controllers as claimed in claim 16, is characterized in that, the instruction of described control class comprises 1 watchdog zero clearing instruction CLRWDT, are used for zero clearing house dog counter.

19. 4 digit RISC micro controllers as claimed in claim 16, is characterized in that, the instruction of described control class comprises 1 non-operation instruction NOP, and any action is not done in this instruction.

20. 4 digit RISC micro controllers as claimed in claim 1, is characterized in that, described peripheral functional modules steering order comprises 1 peripheral functional modules enable command PVOX, for starting peripheral functional modules, starts working.

21. 4 digit RISC micro controllers as claimed in claim 1, it is characterized in that, described peripheral functional modules steering order comprises 1 peripheral functional modules and finishes jump instruction JVEND, for the end signal that peripheral functional modules is returned, detect, once peripheral functional modules end signal be detected, jump to destination address.

22. 4 digit RISC micro controllers as claimed in claim 9, is characterized in that, the instruction of described program jump class is binary cycle instruction.

23. 4 digit RISC micro controllers as claimed in claim 21, is characterized in that, it is binary cycle instruction that described peripheral functional modules finishes jump instruction.

24. 4 digit RISC micro controllers as claimed in claim 2, is characterized in that, described arithmetical logic instruction is one-cycle instruction.

25. 4 digit RISC micro controllers as claimed in claim 1, is characterized in that, described program storage is that 15 bit wides are for depositing the program storage of order code.

26. 4 digit RISC micro controllers as claimed in claim 20, is characterized in that, described at least one peripheral functional modules comprises voice module.

27. 4 digit RISC micro controllers as claimed in claim 26, is characterized in that, described register file comprises for depositing the voice address register of voice initial address and for depositing the sampling rate register of speech sample rate,

28. 4 digit RISC micro controllers as claimed in claim 27, is characterized in that, described sample frequency frequency divider produces sampling rate signal according to clock signal and described speech sample rate, and exports to voice address generator;

29. 4 digit RISC micro controllers as claimed in claim 1, it is characterized in that, described clock module comprises quick oscillation device, oscillator and timing generator at a slow speed, described control module comprises mode of operation processor, for controlling clock module clock signal according to following four kinds of chip operation patterns:

30. 4 digit RISC micro controllers as claimed in claim 26, it is characterized in that, described at least one peripheral functional modules comprises LCD driver module, and described register file comprises for controlling the LCD control register of LCD driver module work and for storing the LCD RAM that shows data.

31. 4 digit RISC micro controllers as claimed in claim 27, is characterized in that, speech memory is 4 bit memories.

32. 4 digit RISC micro controllers as claimed in claim 29, is characterized in that, described at least one peripheral functional modules comprises voice module, and described voice module receives the clock signal from quick oscillation device.

33. 4 digit RISC micro controllers as claimed in claim 32, is characterized in that, when voice module is not worked and when chip is not worked with quick mode, clock module is closed quick oscillation device.

34. 4 digit RISC micro controllers as claimed in claim 5, is characterized in that, the instruction of described data transmission class is one-cycle instruction.

35. 4 digit RISC micro controllers as claimed in claim 6, is characterized in that, described immediate instruction is one-cycle instruction.

36. 4 digit RISC micro controllers as claimed in claim 7, is characterized in that, described decimal adjust instruction is one-cycle instruction.

37. 4 digit RISC micro controllers as claimed in claim 8, is characterized in that, described in to bring bit shift instruction into be one-cycle instruction.

38. 4 digit RISC micro controllers as claimed in claim 16, is characterized in that, the instruction of described control class is one-cycle instruction.

39. 1 kinds of toys, comprise 4 digit RISC micro controllers according to claim 1.