CN102214614A - Chip package body - Google Patents
Chip package body Download PDFInfo
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- CN102214614A CN102214614A CN2010101577200A CN201010157720A CN102214614A CN 102214614 A CN102214614 A CN 102214614A CN 2010101577200 A CN2010101577200 A CN 2010101577200A CN 201010157720 A CN201010157720 A CN 201010157720A CN 102214614 A CN102214614 A CN 102214614A
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- chip
- metal strip
- conductive pad
- layer
- chip packing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The invention discloses a chip package body. The chip package body comprises a chip and a sealing ring, wherein the chip is provided with a plurality of conductive pads arranged at the periphery of the chip; the sealing ring comprises a plurality of metal bar-shaped objects; and the metal bar-shaped objects are arranged in a space encircled by two adjacent conductive pads, and are not electrically connected with the two adjacent conductive pads at the same time.
Description
Technical field
The present invention relates to chip packing-body, particularly a kind of seal ring structure of chip packing-body.
Background technology
At present industry has developed at the encapsulation of chip and a kind of wafer-class encapsulation technology, after the wafer-class encapsulation body is finished, need between each chip, to carry out cutting step, to separate each chip, in order to reduce the fracture extension that produces in the cutting step probability to the chip, between each chip, sealing ring need be set, to improve the reliability of chip packing-body.In addition, the area that sealing ring such as occupying volume are outer, then the tube core sum on the wafer may reduce.
Summary of the invention
The object of the present invention is to provide a kind of core packaging body, to address the above problem.
For reaching above-mentioned purpose, embodiments of the invention provide a kind of chip packing-body, comprising: chip, have a plurality of conductive pads, and be arranged at around the chip; And sealing ring, comprise a plurality of metal strip things, be arranged at two in the spatial dimension that conductive pad enclosed, and each metal strip thing does not electrically connect with the conductive pad of two adjacency simultaneously.
For allow above-mentioned purpose of the present invention, feature, and advantage can become apparent, following conjunction with figs. is described in detail below:
Description of drawings
Fig. 1 is the vertical view according to the seal ring structure region of the chip packing-body of the embodiment of the invention;
Fig. 2 A is the enlarged diagram at Fig. 1 center line 3B place;
Fig. 2 B is the partial structurtes stereogram according to the seal ring structure of the embodiment of the invention;
Fig. 3 A is the vertical view according to the seal ring structure of the embodiment of the invention;
Fig. 3 B is the vertical view according to the seal ring structure of another embodiment of the present invention; And
Fig. 4 A-Fig. 4 F is the generalized section according to each processing step of the making chip packing-body of the embodiment of the invention.
Description of reference numerals
30～chip;
36～connecting portion;
32～sealing ring;
34～conductive pad;
40,41,43,45,401-408～metal strip thing;
41a～external series gap;
45a～internal clearance;
The width of w～conductive pad;
The spacing of d～external series gap and internal clearance;
42～guide hole;
44～stress barricade;
341,342, the metal level of 343～conductive pad;
411,412, the metal level of 413～metal strip thing;
361,362, the metal level of 363～connecting portion;
100～wafer substrate;
The wafer substrates of 100 '～thinning;
102～conductive pad;
104～dielectric layer;
106～wall;
107～hole;
109～recess;
110～microlens array;
112 insulating barriers;
114～conductor layer;
116～protective layer;
118～conductive projection;
200～encapsulated layer;
C～Cutting Road;
Bending channel between S～two metal strip things.
Embodiment
Below describe the present invention in detail with embodiment and conjunction with figs., in accompanying drawing or specification were described, similar or identical part was used identical figure number.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.Moreover the part of each element will be it should be noted that the element that does not illustrate among the figure or describe to describe explanation in the accompanying drawing, be the form known to the those of ordinary skill in the affiliated technical field.In addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
The present invention is with the embodiment that makes image sensing element packaging body (image sensor package) as an illustration.Yet, scrutablely be, in the embodiment of chip packing-body of the present invention, it can be applicable to the various electronic components (electroniccomponents) that comprise active element or passive component (active or passive elements), digital circuit or analogous circuit integrated circuits such as (digital or analog circuits), for example relates to photoelectric cell (opto electronic devices), MEMS (micro electro mechanical system) (Micro Electro Mechanical System; MEMS), physical quantitys such as microfluid system (micro fluidicsystems) or utilization heat, light and pressure change the physical sensors of measuring (PhysicalSensor).Particularly can select to use wafer-class encapsulation (wafer scale package; WSP) technology is to Image Sensor, light-emitting diode (light-emitting diodes; LEDs), solar cell (solarcells), radio-frequency (RF) component (RF circuits), accelerometer (accelerators), gyroscope (gyroscopes), little brake (micro actuators), surface acoustic wave element (surface acoustic wave devices), pressure sensor (process sensors) or ink gun semiconductor chips such as (ink printer heads) encapsulate.
Wherein above-mentioned wafer-class encapsulation technology mainly is meant after wafer stage is finished encapsulation step, cut into independently packaging body again, yet, in a particular embodiment, the semiconductor chip redistribution that for example will separate is on bearing wafer, carry out packaging technology again, also can be referred to as wafer-class encapsulation technology.In addition, above-mentioned wafer-class encapsulation technology also is applicable to by piling up the multi-disc wafer that (stack) mode arrangement has integrated circuit, to form the chip packing-body of multilevel integration (multi-layer integrated circuit devices).
Fig. 1 is centered on by sealing ring 32 around each chip 30 for the vertical view of demonstration according to the sealing ring region of the chip packing-body of embodiments of the invention, is Cutting Road c between two sealing rings 32.Fig. 2 A is the amplification plan view at Fig. 1 center line 3B place, finds out that by knowing among Fig. 2 A a plurality of conductive pads are provided with around chip, and 32 of sealing rings comprise two in abutting connection with the metal strip thing 40 between the conductive pad 34.In an embodiment, metal strip thing 40 integral body can be positioned at the spatial dimension of being enclosed in abutting connection with conductive pad 34 by two, and therefore, the seal ring structure of present embodiment can utilize the space between conductive pad 34 itself and the two adjacent conductive pads to finish.In another embodiment, width as sealing ring 32 is no more than two width in abutting connection with conductive pad 34, and then width between the two adjacent sealing rings 32 such as need are about 80 μ m, and then required Cutting Road width c is 80 μ m only also, with 8 inches wafer, therefore the tube core sum can increase.In addition, the design of the seal ring structure of present embodiment can also be applicable to chip on board encapsulation (chip on board is called for short COB) and wafer-level package (chip scale package is called for short CSP) technology.
In an embodiment, conductive pad 34 can be for extending contact mat, and it utilizes the joint sheet on connecting portion 36 and the chip to electrically connect, and does not need retaining space that inner seal ring is set between extension contact mat and joint sheet, therefore can further dwindle area of chip.
In an embodiment, the width w of conductive pad 34 for example is about 50 μ m, and the width of metal strip thing 40 for example is about 10 μ m, therefore shown in Fig. 2 A, 3 metal strip things parallel to each other 41,43 and 45 can be set between conductive pad 34.In addition, in another embodiment, also can be provided with more than 3 between the conductive pad 34 or following metal strip thing, look closely actual demand and decide.It should be noted that, each metal strip thing 41,43 and 45 two ends can be not simultaneously and two adjacent conductive pads 34 electrically connect, that is has the gap at least, it is between the conductive pad at each metal strip thing and two ends, to avoid short circuit, wherein, at least one external series gap is positioned at the outside of two conductive pad enclosed spaces; And at least one internal clearance is positioned at the inboard of two conductive pad enclosed spaces.For example, between the metal strip thing 41 of chip exterior such as Cutting Road c and conductive pad 34, comprise external series gap 41a, between the metal strip thing 45 of chip 30 inside and conductive pad 34, comprise internal clearance 45a.In another embodiment, external series gap 41a and internal clearance 45a can form bending channel, it is greater than the rectilineal interval d of this external series gap 41a and internal clearance 45a, that is, can must just can enter as the bending channel between 41,43 or 43,45 along two metal strip things by the stress that metal strip thing 41,43 and/or 45 produces cutting step, avoid above-mentioned stress directly to pass internal clearance and form the crack that extends to chip internal from external series gap.
Then, see also Fig. 2 B, it shows the partial structurtes stereogram of sealing ring 32, in this embodiment, conductive pad 34 has three-layer metal layer 341,342 and 343, and also has three-layer metal layer 361,362 and 363 from the connecting portion 36 that conductive pad 34 extends to and joint sheet (not drawing) electrically connects.In this embodiment, conductive pad electrically connects with three-layer metal layer and joint sheet, yet, in another embodiment, also can only utilize the layer of metal layer to be connected to joint sheet, the metal level 362 in the middle of for example utilizing is connected to joint sheet.In an embodiment, have a plurality of guide holes 42 between the three-layer metal layer 341,342 and 343 of conductive pad 34, to electrically connect each metal level, the position of guide hole 42 does not limit, and the crack of guide hole 42 all right stop portions avoids it to extend to chip internal simultaneously.
In an embodiment, each metal strip thing 41,43 and 45 between two conductive pads 34 also can have the three-layer metal layer, as shown in Fig. 2 B, metal strip thing 41 has three-layer metal layer 411,412 and 413, and between each metal level 411,412 and 413, have a plurality of guide holes 42, to electrically connect each metal level, the position of guide hole 42 can be provided with arbitrarily.In an embodiment, owing to can select the metal level of conductive pad and the metal level of metal strip thing to form simultaneously on technology, therefore, the number of plies of the number of plies of the metal level of conductive pad and the metal level of metal strip thing can be identical.It should be noted that, in an embodiment, have a stress barricade 44 at least between the metal level 411,412 and 413 of metal strip thing 41, this stress barricade 44 is except that the structure of reinforced seal ring 32 more, more can stop the crack effectively, avoid it to extend to chip internal.In another embodiment, at least has a stress barricade between each metal strip thing 41,43 and 45 the metal level, that is metal strip thing 41,43 and 45 all has the stress barricade separately, shown in Fig. 2 B, gap between this stress barricade and conductive pad can be provided with according to the described mode of above-mentioned Fig. 2 A, so that the stress that cutting step produced must enter along the extension passage between the two stress barricades, avoid above-mentioned stress directly to pass internal clearance and form the crack that extends to chip internal from external series gap.
In the seal ring structure of present embodiment, the set-up mode of the metal strip thing 40 between the conductive pad 34 can have many kinds of kenels, and Fig. 2 A is depicted as wherein a kind of kenel.In addition, Fig. 3 A to Fig. 3 B shows other two kinds of kenels, see also Fig. 3 A, in an embodiment, have two metal strip things 401 and 403 parallel to each other between the conductive pad 34, metal strip thing 401 is connected with conductive pad 34 with an end of 403, the other end then and keep the gap between the conductive pad, metal strip thing 401 and 403 and conductive pad 34 between the gap be staggered, the stress that cutting step is produced must enter along the extension passage S between two metal strip things 401 and 403, can avoid the crack directly to extend to chip internal.
Then, see also Fig. 3 B, in this embodiment, have three metal strip things 405,407 and 408 between the conductive pad 34, metal strip thing 405 and 407 wherein is located along the same line, its rectilinear direction of arranging is perpendicular to conductive pad 34, and metal strip thing 405 is connected with conductive pad 34 with an end of 407, has the gap between metal strip thing 405 and 407.408 of another metal strip things are arranged in parallel with 405,407, and the two ends of metal strip thing 408 all keep gaps with conductive pad 34.It should be noted that these gaps among Fig. 3 B also are staggered.
Though in specification of the present invention, only enumerate the arrangement mode of several metal strip things, yet, be understandable that, metal strip thing between conductive pad can also have other kinds arrangement mode, as long as these metal strip things can not make and produce short circuit between the conductive pad, and it is staggered arrangement each other and gets final product with gap or the gap between each metal strip thing between two conductive pads.
Fig. 4 A-Fig. 4 F is the generalized section of demonstration according to each processing step of the making chip packing-body of the embodiment of the invention, and these profiles show the section along Fig. 2 A center line X-X ', and therefore it can not show metal strip thing 40 on the position of conductive pad 34.See also Fig. 4 A, at first, provide substrate 100, it for example is semiconductor wafer, having a plurality of chip (not shown)s on semiconductor wafer 100, is Image Sensor for example, and can have corresponding microlens array 110 as image sensor surface on Image Sensor.Having dielectric layer 104 in the substrate of semiconductor wafer, for example is silica, and each chip has corresponding conductive pad (conductive pad) 102, is arranged in this dielectric layer 104.
Then, front with semiconductor wafer 100, that is surface and encapsulated layer 200 with chip are bonding, and encapsulated layer is as the bearing structure of encapsulation, and it can be for example glass, quartz (quartz), opal (opal), plastic cement or other any transparency carrier for the light turnover.What deserves to be mentioned is, also can optionally form filter (filter) and/or anti-reflecting layer (anti-reflective layer) on encapsulated layer.Wall (spacer) 106 can be set between encapsulated layer 200 and semiconductor wafer 100, make and form gap (cavity) 107 between semiconductor wafer 100 and the encapsulated layer 200, gap 107 is spaced apart 106 on layer and centers on.
Above-mentioned wall 106 can be epoxy resin (epoxy), welding resisting layer (solder mask) or other megohmite insulant that is fit to, the for example silicon oxide layer of inorganic material, silicon nitride layer, silicon oxynitride layer, metal oxide or its combination, or the polyimide resin (polyimide of organic high score material; PI), benzocyclobutene (butylcyclobutene; BCB), Parylene (parylene), naphthalene polymer (polynaphthalenes), fluorine carbide (fluorocarbons), acrylate (accrylates) etc., and this wall 106 can be to utilize coating method, for example rotary coating (spin coating), spraying (spraycoating) or drench curtain coating cloth (curtain coating), or other depositional mode that is fit to, for example liquid deposition (liquid phase deposition), physical vapour deposition (PVD) (physical vapor deposition; PVD), chemical vapour deposition (CVD) (chemical vapor deposition; CVD), low-pressure chemical vapor deposition (lowpressure chemical vapor deposition; LPCVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition; PECVD), rapid heat chemical vapour deposition (rapid thermal-CVD; RTCVD) or aumospheric pressure cvd (atmospheric pressurechemical vapor deposition; APCVD) mode forms, and pollutes or avoids aqueous vapor to invade with isolated environment.
In an embodiment, above-mentioned Image Sensor can be complementary metal oxide semiconductor element (CMOS) or charge coupled cell (charge-couple device; CCD).In addition, above-mentioned conductive pad 102 also can be to extend joint sheet (extension pad), and preferably can be by copper (copper; Cu), aluminium (aluminum; Al) or other suitable metal material made.
Then, see also Fig. 4 B, back side thinning semiconductor wafer from semiconductor wafer 100 becomes the semiconductor wafer 100 ' with predetermined thickness, and this thinning technology can be etching (etching), milling (milling), grinding (grinding) or the modes such as (polishing) of grinding.Then, the back side with the semiconductor wafer 100 ' of indentation technology after thinning forms recess (notch) 109.After this recess 109 formed, semiconductor wafer 100 ' can be isolated many semiconductor chips (chip)
See also Fig. 4 C, the dielectric layer 104 of etching recess 109 bottoms is to the contact surface that exposes conductive pad 102.Then, see also Fig. 4 D, form insulating barrier 112 with the lateral zones of covering recess 109 and the back side of semiconductor wafer 100 '.In an embodiment, above-mentioned insulating barrier 112 can be an epoxy resin, welding resisting layer or other megohmite insulant that is fit to, the silicon oxide layer of inorganic material for example, silicon nitride layer, silicon oxynitride layer, metal oxide or its combination, or the polyimide resin of organic high score material, benzocyclobutene, Parylene, the naphthalene polymer, the fluorine carbide, acrylate etc., and this insulating barrier 112 can utilize coating method, rotary coating for example, spraying or pouring curtain coating cloth, or other depositional mode that is fit to, for example liquid deposition, physical vapour deposition (PVD), chemical vapour deposition (CVD), low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, the mode of rapid heat chemical vapour deposition or aumospheric pressure cvd forms, with the conductor layer 114 of isolation of semiconductor wafer 100 ' with follow-up formation.
Then, form conductor layer 114 in recess 109 and on the back side of semiconductor wafer 100 ', can be by for example being physical vaporous deposition (PVD) or sputtering method (sputtering), compliance ground deposition for example is copper, aluminium, silver (silver; Ag), nickel (nickel; Ni) or the conductive layer of its alloy in recess 109 and on the back side of semiconductor wafer 100 ', again by photoengraving carving technology patterned conductive layer, to form conductor layer 114.Conductor layer 114 contacts with the surface of conductive pad 102, forms the contact of L type, and extends to the terminal contact (not drawing) on the semiconductor wafer 100 ' back side.
Then, see also Fig. 4 E, form protective layer (passivation) 116 on conductor layer 114, cover the back side and the recess of semiconductor wafer 100 ', protective layer for example is soldering-resistance layer (solder mask).Then, see also Fig. 4 F, form conductive projection (conductive bump) 118 and pass protective layer 116 and conductor layer 14 electric connections.In an embodiment; after forming above-mentioned protective layer 116; this protective layer 116 of patterning; to form the opening of expose portion conductor layer 114; then, the mode by plating or screen painting (screenprinting) fills in scolder (solder) in the above-mentioned opening; and carrying out reflow (re-flow) technology, for example is the conductive projection 118 of soldered ball (solder ball) or weld pad (solder paste) to form.Then, cut apart the wafer-class encapsulation body of said chip,, finish chip packing-body of the present invention to separate each chip along Cutting Road (scribe line).
According to the manufacture method of the chip packing-body of the embodiment of the invention, conductive pad 102 is not etched, and conductive pad 102 only exposes contact-making surface and contacts with conductor layer 114, to form the contact of L type.Therefore, the sealing ring of being made up of the metal strip thing between conductive pad and the conductive pad can not suffer damage in the manufacture process of chip packing-body, can reach the effect of sealing ring.
In sum, seal ring structure of the present invention comprises various embodiment.For example in an embodiment, it is the space that utilizes between conductive pad itself and two conductive pads.In another embodiment, the width of seal ring structure can not surpass the width of conductive pad.Or in another embodiment, sealing ring comprises a plurality of metal strip things, has an at least one external series gap and an internal clearance between itself and two adjacent conductive pads, and the bending channel that both form can reduce stress.
Though the present invention has disclosed preferred embodiment as above; right its is not in order to qualification the present invention, any person skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.
Claims (14)
1. chip packing-body comprises:
Chip has a plurality of conductive pads, is arranged at around this chip; And
Sealing ring, it comprises a plurality of metal strip things, is arranged at two in the spatial dimension that conductive pad enclosed, and each metal strip thing does not electrically connect with the conductive pad of above-mentioned two adjacency simultaneously.
2. chip packing-body as claimed in claim 1, wherein, described conductive pad has width, and described metal strip thing is positioned at the spatial dimension that width enclosed of above-mentioned two adjacent conductive pads, and described metal strip thing is arranged in parallel with each other.
3. chip packing-body as claimed in claim 1 or 2, wherein each this metal strip thing at least with one of above-mentioned two adjacent conductive pads gap that is separated by.
4. chip packing-body as claimed in claim 3, wherein, the outside, the space that width enclosed of above-mentioned two adjacent conductive pads also comprises external series gap, and the inboard, space that width enclosed of above-mentioned two adjacent conductive pads also comprises internal clearance, this external series gap and the formed bending channel of this internal clearance are greater than the rectilineal interval of this external series gap and this internal clearance.
5. chip packing-body as claimed in claim 3, arrange for dislocation in wherein said gap.
6. chip packing-body as claimed in claim 4, wherein this bending channel comprises along the space between the two metal strip things as communication passage.
7. chip packing-body as claimed in claim 6, wherein this conductive pad comprises the multiple layer metal layer.
8. chip packing-body as claimed in claim 7 comprises that also a plurality of guide holes are arranged between the described metal level of this conductive pad.
9. chip packing-body as claimed in claim 7, wherein this metal strip thing comprises the multiple layer metal layer.
10. chip packing-body as claimed in claim 9, the number of plies of the described metal level of this metal strip thing is identical with the number of plies of the described metal level of this conductive pad.
11. chip packing-body as claimed in claim 9 comprises that also at least one stress barricade is arranged between the described metal level of this metal strip thing.
12. chip packing-body as claimed in claim 9 wherein has the stress barricade between each metal level of each this metal strip thing.
13. chip packing-body as claimed in claim 3 also comprises:
Encapsulated layer is arranged on this chip, engages with the first surface of this chip;
Conductor layer is arranged in this chip on the second surface with respect to this first surface, extends to the surface of described conductive pad to contact;
Protective layer is arranged on this conductor layer, has this conductor layer that opening exposes a part; And
Conductive projection is arranged on this opening, electrically connects with this conductor layer.
14. a chip packing-body comprises:
Chip has a plurality of conductive pads, is arranged at around this chip, and described conductive pad has width; And
Sealing ring comprises a plurality of metal strip things, is arranged at two in the spatial dimension that conductive pad enclosed, and the width of sealing ring is not more than the width of described conductive pad, and each this metal strip thing does not electrically connect with the conductive pad of above-mentioned two adjacency simultaneously; The outside, the space that width enclosed of wherein above-mentioned two adjacent conductive pads also comprises external series gap, and the inboard, space that width enclosed of above-mentioned two adjacent conductive pads also comprises internal clearance, this external series gap and the formed bending channel of this internal clearance are greater than the rectilineal interval of this external series gap and this internal clearance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101577200A CN102214614B (en) | 2010-04-01 | 2010-04-01 | Chip package body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101577200A CN102214614B (en) | 2010-04-01 | 2010-04-01 | Chip package body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102214614A true CN102214614A (en) | 2011-10-12 |
| CN102214614B CN102214614B (en) | 2013-06-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101577200A Expired - Fee Related CN102214614B (en) | 2010-04-01 | 2010-04-01 | Chip package body |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1617312A (en) * | 2003-11-10 | 2005-05-18 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| US20070069365A1 (en) * | 2005-09-28 | 2007-03-29 | Archer Vance D | Semiconductor with damage detection circuitry |
| US20090315184A1 (en) * | 2008-05-26 | 2009-12-24 | Oki Semiconductor Co., Ltd. | Semiconductor Device |
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2010
- 2010-04-01 CN CN2010101577200A patent/CN102214614B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1617312A (en) * | 2003-11-10 | 2005-05-18 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| US20070069365A1 (en) * | 2005-09-28 | 2007-03-29 | Archer Vance D | Semiconductor with damage detection circuitry |
| US20090315184A1 (en) * | 2008-05-26 | 2009-12-24 | Oki Semiconductor Co., Ltd. | Semiconductor Device |
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| Publication number | Publication date |
|---|---|
| CN102214614B (en) | 2013-06-12 |
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