CN102207882B - Anchor address loading method of immediate in application program compilation of reduced instruction-set computer (RISC) processor - Google Patents
Anchor address loading method of immediate in application program compilation of reduced instruction-set computer (RISC) processor Download PDFInfo
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- CN102207882B CN102207882B CN 201110141121 CN201110141121A CN102207882B CN 102207882 B CN102207882 B CN 102207882B CN 201110141121 CN201110141121 CN 201110141121 CN 201110141121 A CN201110141121 A CN 201110141121A CN 102207882 B CN102207882 B CN 102207882B
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Abstract
The invention discloses an anchor address loading method of an immediate in application program compilation of a reduced instruction-set computer (RISC) processor. The method comprises the following steps of: distributing a general register for a code segment of an application program to store an anchor address (Rx) of the code segment, and initializing the anchor address (Rx) as a base address of the code segment; when a code segment symbol address immediate (IAx) is required to be loaded for the application program, realizing anchor address loading by using an addition instruction which corresponds to a formula, namely (Rx)+{IAx-(Rx)}; distributing the general register for a data segment of the application program as an anchor address (Ry) of the data segment, and initializing the anchor address (Ry) as the base address of the data segment; when a data segment symbol address immediate (IAy) is required to be loaded for the application program, realizing anchor address loading by using the addition instruction which corresponds to a formula, namely (Ry)+{IAy-(Ry)}. By the invention, the working efficiency of the application program can be improved, an additional memory space is not consumed, and real-time property is excellent.
Description
Technical field
The present invention relates to the compiling and the chained technology field of risc processor application program, location, the anchorage stowage of counting immediately in especially a kind of application program compiling.
Background technology
In the embedded system development of risc-based processor, processor compiling and the link instrument that is absolutely necessary, it is the discernible binary code of processor that collector is write the code conversion that forms with user's higher level lanquage (being generally the C/C++ language), link module then a plurality of such binary code modules are linked together become the scale-of-two that can on processor, move can executive routine.Since 32 RISC architecture processors can't be directly in instruction coding 32 bit address count immediately, so the current architecture processor of RISC in the industry all is to instruct to finish by access memory instruction as LOAD to load the address and count immediately, has the low and low problem of code density of efficient.In the compiling link of risc processor application program, the main access memory instruction of adopting processor is loaded in address number immediately at present, and instruction is finished as LOAD.
The access memory instruction of Embedded RISC processor generally need take the external data address bus, needs a plurality of cycles to finish, thereby causes this instruction than general computing class, and is lower as the add instruction operational efficiency.Though so by access memory instruct load the address immediately number realize simply, efficient is low, except the access memory instruction, count immediately the address that also needs additional space to deposit 32.
Summary of the invention
In order to overcome the outer storage space of inefficiency, the occupying volume of counting stowages in the existing risc processor application program compiling immediately, the deficiency of real-time difference, the invention provides and a kind ofly promote work efficiency, do not need to consume location, the anchorage stowage of counting immediately in the good risc processor application program compiling in extra memory space, real-time.
The technical solution adopted for the present invention to solve the technical problems is:
Location, the anchorage stowage of counting immediately in a kind of risc processor application program compiling, described application program comprises code segment and data segment;
For general-purpose register of code segment distribution of application program is deposited code segment anchorage location Rx, and it is initialized as the base address of code segment, need load a code segment symbolic address when counting IAx immediately when application program, adopt the corresponding processor add instruction of formula (Rx)+{ IAx-(Rx) } to realize that the location, anchorage loads;
Simultaneously, for the application's data section distributes a general-purpose register as data segment anchorage location Ry, and it is initialized as the data segment base address, need load a data segment symbolic address when counting IAy immediately when application program, adopt the corresponding processor add instruction of formula (Ry)+{ IAy-(Ry) } to realize that the location, anchorage loads.
Further, location, described anchorage stowage may further comprise the steps:
(1) be two register Rx of application assigned, Ry is respectively applied for and deposits location, code segment anchorage and location, data segment anchorage;
(2) definition code segment address is counted the relocation information array ARx that load the location, anchorage immediately, and does initialization; If needing to load the address that belongs to code segment, the Lx place, address of the code segment of application program counts IAx immediately to register Rm, then generating a code segment relocation information RELx leaves among the array ARx, this information comprises needs the code segment of reorientation address Lx, and the code segment symbolic address is counted IAx and register Rm immediately;
(3) definition code segment address is counted the relocation information array ARy that load the location, anchorage immediately, and does initialization; If needing to load the address that belongs to data segment, the Ly place, address of the code segment of processor application programs counts IAy immediately to register Rn, then generating a data segment relocation information RELy leaves among the array ARy, this information comprises needs the code segment of reorientation address Ly, and the data segment symbolic address is counted IAy and register Rn immediately;
(4) code segment and the data segment to each input file links, and the result outputs to the code segment and the data segment of destination application again with link, and the location, code segment anchorage of temporary export target application program is that At and location, data segment anchorage are Ad;
When (5) code segment of each input and data segment being linked, the relocation information array ARx of scanning step (2) output is done as follows each code segment relocation information RELx in the array:
(5.1) according to temporary At in middle IAx that RELx comprised that generates of step (2) and the step (4), calculate IAx-At, temporary is that code segment is counted side-play amount OFFSETx immediately;
(5.2) at the Lx place that RELx comprises, generate Rm＜-(Rx)+the processor add instruction of OFFSETx correspondence;
When (6) code segment of each input and data segment being linked, the relocation information array ARy of scanning step (3) output is done as follows each data segment relocation information RELy in the array:
(6.1) according to temporary Ad in middle IAy that RELy comprised that generates of step (3) and the step (4), calculate IAy-Ad, temporary is that data segment is counted side-play amount OFFSETy immediately;
(6.2) comprise several Ly places at RELy, generate Rn＜-(Ry)+the processor add instruction of OFFSETy correspondence;
(7) Rx with step (1) is initialized as the temporary code segment anchorage location At of step (4), and the Ry of step (1) is initialized as the temporary data segment anchorage location Ad of step (4).
Beneficial effect of the present invention mainly shows:
1) loading that the address is counted does not immediately relate to access memory, the operational efficiency height of application program;
2) do not need to consume extra memory headroom, improved the code density of application program;
3) can effectively reduce the occupancy of CPU, improve system real time external bus;
4) this method can realize that very strong transplantability is arranged in the compiling link module of multiple risc processor;
5) this method is very little to the change of the compiling link module of risc processor, and the change cost is low.
Description of drawings
Fig. 1 supports the address to count the application program compiling link synoptic diagram that load the location, anchorage immediately;
Fig. 2 is that execution is loaded all over process flow diagram in the location, anchorage that count immediately the address in the collector;
Fig. 3 is that process flow diagram is loaded in the location, anchorage that link module is counted immediately to the address.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Fig. 3, location, the anchorage stowage of counting immediately in a kind of risc processor application program compiling, described application program comprises code segment and data segment;
For general-purpose register of code segment distribution of application program is deposited code segment anchorage location Rx, and it is initialized as the base address of code segment, need load a code segment symbolic address when counting IAx immediately when application program, adopt the corresponding processor add instruction of formula (Rx)+{ IAx-(Rx) } to realize that the location, anchorage loads;
Simultaneously, for the application's data section distributes a general-purpose register as data segment anchorage location Ry, and it is initialized as the data segment base address, need load a data segment symbolic address when counting IAy immediately when application program, adopt the corresponding processor add instruction of formula (Ry)+{ IAy-(Ry) } to realize that the location, anchorage loads.
With reference to Fig. 1, concrete enforcement comprises the steps:
(1) in the collector, be that processor application programs distributes two register Rx, Ry is respectively applied for and deposits location, code segment anchorage and location, data segment anchorage, and counts the locations, anchorage with reference to 200 of Fig. 2 immediately with the mode increase of plug-in unit and load and carry out time;
(2) with reference to 201 of Fig. 2, definition code segment address is counted the relocation information array ARx that load the location, anchorage immediately, and does initialization, and each member variable comprises in the array needs the code segment of reorientation address Lx, number immediately that is loaded and the destination register that loads;
(3) with reference to 202 of Fig. 2, definition code segment address is counted the relocation information array ARy that load the location, anchorage immediately, and does initialization, and each member variable comprises in the array needs the code segment of reorientation address, number immediately that is loaded and the destination register that loads;
(4) with reference to 203～206 of Fig. 2, count A_Func immediately to register Rm if need to load the address that belongs to code segment in the code segment of processor application programs, then generating a relocation information RELx leaves among the initialized array ARx of step (2) institute, this information comprises needs the code segment of reorientation address Lx, and the address of code segment is counted A_Func and register Rm immediately;
(5) with reference to 207～210 of Fig. 2, count A_Data immediately to Rn if need to load the address that belongs to data segment in the code segment of processor application programs, then generating a relocation information RELy leaves among the initialized array ARy of step (3) institute, this information comprises needs the code segment of reorientation address Ly, and the address of data segment is counted A_Data and register Rn immediately;
(6) in link module, code segment and data segment to each input file link, the link result is outputed to again the code segment and the data segment of destination application, and the location, code segment anchorage of temporary export target application program is that At and location, data segment anchorage are Ad, with reference to 300 of Fig. 3, count location, anchorage repositioning process immediately simultaneously with the increase of plug-in unit mode;
(7) with reference to 300 of Fig. 3, when the code segment of each input and data segment were linked, the relocation information array ARx of scanning step (4) output was done as follows each relocation information RELx in the array:
(7.1) according to temporary At in (4) middle A_Func that RELx comprised that generates and the step (6), with reference to 301 of Fig. 3, calculate A_Func-At, temporary is that code segment is counted side-play amount OFFSET_A_Func, i.e. OFFSET_A_Func=A_Func-At immediately;
(7.2) with reference to 302 and 303 of Fig. 3, at the Lx place that RELx comprises, generate Rm＜-(Rx)+the processor add instruction of OFFSET_A_Func correspondence;
(8) with reference to 300 of Fig. 3, when the code segment of each input and data segment were linked, the relocation information array ARy of scanning step (5) output was done as follows each relocation information RELy in the array:
(8.1) according to temporary Ad in (5) middle A_Data that RELy comprised that generates and the step (6), with reference to 304 of Fig. 3, calculate A_Data-Ad, temporary is that data segment is counted side-play amount OFFSET_A_Data immediately,
Be OFFSET_A_Data=A_Data-Ad;
(8.2) with reference to 305 and 306 of Fig. 3, comprise several Ly places at RELy, generate Rn＜-(Ry)+the processor add instruction of OFFSET_A_Data correspondence;
(9) when application program launching, the Rx of step (1) is initialized as the temporary code segment anchorage location At of step (6), the Ry of step (1) is initialized as the temporary data segment anchorage location Ad of step (6).
Example: in risc processor collector and link module, use this method to realize myFunction is loaded into myCallback function pointer variable, the address of myData is loaded into myDataPTR integer pointer variable.Realize that the concrete step that comprises of present embodiment is as follows:
(1) in collector, be that processor application programs distributes two register R30, R31 is respectively applied for and deposits location, code segment anchorage and location, data segment anchorage, and counts the locations, anchorage with reference to 200 of Fig. 2 immediately with the mode increase of plug-in unit and load and carry out time;
(2) with reference to 201 of Fig. 2, definition code segment address is counted the relocation information array ARRAY_Relocation_Text that load the location, anchorage immediately, and do initialization, each member variable comprises in the array needs the code segment of reorientation address, number immediately that is loaded and the destination register that loads;
(3) with reference to 202 of Fig. 2, definition code segment address is counted the relocation information array ARRAY_Relocation_Data that load the location, anchorage immediately, and do initialization, each member variable comprises in the array needs the code segment of reorientation address, number immediately that is loaded and the destination register that loads;
(4) with reference to 203～206 of Fig. 2, for myCallback function pointer variable distributes register R1, and needing to load the several immediately myFunction in the address that belongs to code segment in the code segment of discovery processor application programs is register R1 to myCallback function pointer variable, then generating a relocation information REL_myFunction leaves among the array ARRAY_Relocation_Text, this information comprises needs the code segment of reorientation address Location_myCallback, myFunction function address and R1;
(5) with reference to 207～210 of Fig. 2, count to R2 immediately if need to load the address of the myData variable that belongs to data segment in the code segment of processor application programs, then generating a relocation information REL_myData leaves among the array ARRAY_Relocation_Data, this information comprises needs the code segment of reorientation address Location_myDataPTR, myData address of variable and R2;
(6) in link module, code segment and data segment to each input file link, the link result is outputed to again the code segment and the data segment of destination application, and the location, code segment anchorage of temporary export target application program is that Address_Text_Start and location, data segment anchorage are Address_Data_Start, with reference to 300 of Fig. 3, count location, anchorage repositioning process immediately simultaneously with the increase of plug-in unit mode;
(7) with reference to 300 of Fig. 3, when the code segment of each input and data segment were linked, the relocation information array ARRAY_Relocation_Text of scanning step (4) output was done as follows each relocation information REL_myFunction in the array:
(7.1) according to temporary Address_Text_Start in middle myFunction that REL_myFunction comprised that generates in step _ (4) and the step (6), calculate (myFunction-Address_Text_Start), temporary is OFFSET_myFunction;
(7.2) at the Location_myCallback place that REL_myFunction comprises, generate R1＜-(R30)+add instruction of OFFSET_myFunction processor correspondence;
(8) with reference to 300 of Fig. 3, when the code segment of each input and data segment were linked, the relocation information array ARRAY_Relocation_Data of scanning step (5) output was done as follows each relocation information REL_myData in the array:
(8.1) according to temporary Address_Data_Start in middle myData that REL_myData comprised that generates of step (5) and the step (6), calculate (myData-Address_Data_Start), temporary is OFFSET_myData;
(8.2) comprise several Location_myDataPTR places at REL_myData, generate R2＜-(R31)+the processor add instruction of OFFSET_myData correspondence;
(9) when application program launching, the R30 of step (1) is initialized as the temporary code segment anchorage location Address_Text_Start of step (6), the R30 of step (1) is initialized as the temporary data segment anchorage location Address_Data_Start of step (6).
Claims (2)
1. several immediately location, anchorage stowage during a risc processor application program compiles, it is characterized in that: described application program comprises code segment and data segment;
For general-purpose register of code segment distribution of application program is deposited code segment anchorage location Rx, and it is initialized as the base address of code segment, need load a code segment symbolic address when counting IAx immediately when application program, adopt the corresponding processor add instruction of formula (Rx)+{ IAx-(Rx) } to realize that the location, anchorage loads;
Simultaneously, for the application's data section distributes a general-purpose register as data segment anchorage location Ry, and it is initialized as the data segment base address, need load a data segment symbolic address when counting IAy immediately when application program, adopt the corresponding processor add instruction of formula (Ry)+{ IAy-(Ry) } to realize that the location, anchorage loads.
2. location, the anchorage stowage of counting immediately in the risc processor application program compiling as claimed in claim 1, it is characterized in that: location, described anchorage stowage may further comprise the steps:
(1) is two registers of application assigned, is respectively applied for and deposits code segment anchorage location Rx and data segment anchorage location Ry;
(2) definition code segment address is counted the relocation information array ARx that load the location, anchorage immediately, and does initialization; If needing to load, the Lx place, address of the code segment of application program belongs to the several immediately IAx of code segment symbolic address to register Rm, then generating a code segment relocation information RELx leaves among the array ARx, this information comprises needs the code segment of reorientation address Lx, and the code segment symbolic address is counted IAx and register Rm immediately;
(3) definition code segment address is counted the relocation information array ARy that load the location, anchorage immediately, and does initialization; If needing to load, the Ly place, address of the code segment of processor application programs belongs to the several immediately IAy of data segment symbolic address to register Rn, then generating a data segment relocation information RELy leaves among the array ARy, this information comprises needs the code segment of reorientation address Ly, and the data segment symbolic address is counted IAy and register Rn immediately;
(4) code segment and the data segment to each input links, and the result outputs to the code segment and the data segment of destination application again with link, and the location, code segment anchorage of temporary export target application program is that At and location, data segment anchorage are Ad;
When (5) code segment of each input and data segment being linked, the relocation information array ARx of scanning step (2) output is done as follows each code segment relocation information RELx in the array:
(5.1) according to temporary At in middle IAx that RELx comprised that generates of step (2) and the step (4), calculate IAx-At, temporary is that code segment is counted side-play amount OFFSETx immediately;
(5.2) at the Lx place that RELx comprises, generate Rm＜-(Rx)+the processor add instruction of OFFSETx correspondence;
When (6) code segment of each input and data segment being linked, the relocation information array ARy of scanning step (3) output is done as follows each data segment relocation information RELy in the array:
(6.1) according to temporary Ad in middle IAy that RELy comprised that generates of step (3) and the step (4), calculate IAy-Ad, temporary is that data segment is counted side-play amount OFFSETy immediately;
(6.2) comprise several Ly places at RELy, generate Rn＜-(Ry)+the processor add instruction of OFFSETy correspondence;
(7) Rx with step (1) is initialized as the temporary code segment anchorage location At of step (4), and the Ry of step (1) is initialized as the temporary data segment anchorage location Ad of step (4).
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| US5276822A (en) * | 1989-11-15 | 1994-01-04 | Matsushita Electric Industrial Co., Ltd. | System with enhanced execution of address-conflicting instructions using immediate data latch for holding immediate data of a preceding instruction |
| WO2001025900A1 (en) * | 1999-10-06 | 2001-04-12 | Cradle Technologies | Risc processor using register codes for expanded instruction set |
| CN101211256A (en) * | 2006-12-29 | 2008-07-02 | 上海贝岭股份有限公司 | Special-purpose double production line RISC instruction system and its operation method |
| CN101382884A (en) * | 2007-09-07 | 2009-03-11 | 上海奇码数字信息有限公司 | Instruction coding method, instruction coding system and digital signal processor |
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| JPH02249027A (en) * | 1989-03-22 | 1990-10-04 | Fujitsu Ltd | Instruction fetch decoder |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276822A (en) * | 1989-11-15 | 1994-01-04 | Matsushita Electric Industrial Co., Ltd. | System with enhanced execution of address-conflicting instructions using immediate data latch for holding immediate data of a preceding instruction |
| WO2001025900A1 (en) * | 1999-10-06 | 2001-04-12 | Cradle Technologies | Risc processor using register codes for expanded instruction set |
| CN101211256A (en) * | 2006-12-29 | 2008-07-02 | 上海贝岭股份有限公司 | Special-purpose double production line RISC instruction system and its operation method |
| CN101382884A (en) * | 2007-09-07 | 2009-03-11 | 上海奇码数字信息有限公司 | Instruction coding method, instruction coding system and digital signal processor |
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