CN102202243A - Method and device for detecting signalling No.7 channel based on E1 - Google Patents
Method and device for detecting signalling No.7 channel based on E1 Download PDFInfo
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Abstract
The invention discloses a method and a device for detecting a signalling No.7 channel based on E1, comprising the following steps: S1. an E1 inputting and collecting step: collecting multi-path E1 input signals with signalling No.7; S2. a step of connecting pulse code modulation (PCM) in crossing manner: carrying out timelot cross connection on the multi-path E1 input signals; S3. a high level data link control (HLDL) channel timeslot detection step: the timeslot channel detection of the crossed obtained signal; and S4. an E1 output sending step: converging the detected effective signalling No.7 channel timeslot to an output port. The invention also discloses a device for realizing the method. As the method and device finish the convergence of the signalling No.7 from input to output, thus the condition that the error possibly appear in HDLC channel parameters of manually configured collection equipment can be avoided, and the E1 interface resources of the collection equipment also can be saved. As the practical detection method and device, the method and the device in the invention can be widely applied to a signalling No.7 monitoring system.
Description
Technical field
The present invention relates to a kind of detection technique of signal of communication, particularly a kind of device that reaches existing this method based on the signalling system No.7 passage detection method of E1.
Background technology
Signalling system No.7 is called common channel signalling again.Promptly on a high speed data link, transmit the signaling method of a group speech channel signaling, be generally used for interoffice with time division way.The Signaling System 7(SS-7) that uses in China is called Chinese Signaling System 7(SS-7).The SS7 net is the outer data communication network of a band, and it is superimposed upon on network operator's the switching network, is the important component part of supporting network.Signaling System 7(SS-7) adopts the multifunctional modular design, is a kind of signaling system that is fit to digital communications network more.
When E1 was used for Signaling System Number 7, in 32 time slots (Time Slot), the 0th time slot was used as frame synchronization information, generally uses the passage of the 16th time slot as No. 7 signalings, and all the other 30 time slots are used as voice channel.In some system, also use other time slot to be used as the passage of No. 7 signalings sometimes.
Because what signalling system No.7 used in link layer is the HDLC agreement, therefore in general collecting device all can be equipped with a plurality of HDLC passages to gather signaling data.When we need monitor the signaling in the E1 transmission link, the signal collecting equipment of front end is overlapped on the E1 link that will monitor by E1 high resistant head, and the HDLC channel slot of configuration signal collecting device and the actual time slot correspondence that takies of signalling system No.7, the hdlc controller of collecting device receives signaling data and break into the Ethernet data bag, passes to background system data are handled and analyzed.
Because initial time slot and the shared timeslot number of signalling system No.7 in the E1 link is unfixed, need the DHLC channel parameters of collecting device manually be provided with.If variation has taken place in the shared time slot (comprising initial time slot position and timeslot number) of signaling, just need the manager of artificial notice collecting device again the parameter of HDLC passage to be configured, cumbersomely so also make mistakes easily.
In addition, in general the time slot in the E1 link has only a part wherein to be used for transmitting signalling system No.7, if directly the E1 link that will monitor is connected on the collecting device, this E1 interface resource to collecting device will form very big waste.
Summary of the invention
In order to solve the problem of above-mentioned present stage, the purpose of this invention is to provide a kind of simple, practical signalling system No.7 detection method, and a kind of device of realizing this method is provided based on E1 based on the signalling system No.7 passage detection technique existence of E1.Because this method and apparatus has been finished signalling system No.7 from being input to the convergence of output, what the time slot of output E1 link all transmitted is signalling system No.7, can avoid like this because the constantly parameter of the HDLC passage of human configuration collecting device and the mistake that may occur, but also can save the E1 interface resource of collecting device.
The technical solution used in the present invention is:
A kind of signalling system No.7 passage detection method based on E1 may further comprise the steps:
S1, the E1 input acquisition step that is used to gather the multichannel E1 input signal that has signalling system No.7;
S2, the multichannel E1 input signal that is used for collecting carry out the cross-coupled PCM interconnection of time slot step;
S3, the signal slot that obtains after being used for intersecting carry out the HDLC channel slot that passage detects and detect step;
S4, be used for the detected effective signalling system No.7 channel slot of S3 is intersected the E1 output forwarding step that converges to the E1 output port, described E1 output port is connected with follow-up E1 high resistant head.
Further, described step S1 supports to gather simultaneously 64 road E1 input signals, 64 * 64 2M code streams are supported in time slot interconnection described in the step S2, it is the clog-free full intersection of 2048*2048 64K passage, passage among the step S3 detects and includes 32 road hdlc controllers, can detect 32 kinds of combination of channels simultaneously.
Further, the E1 output port described in the step S4 has 16 road E1 output ports.
Further, the idiographic flow of described step S2 is as follows:
S21, under the control of E1 signal frame lock-out pulse, the data of each time slot of multichannel E1 input signal of collecting are converted to the byte of 8bit, under the effect of controller, deposit in the datarams block RAM according to time-slot sequence;
S22, obtain output time solt after multichannel E1 input signal time slot rearranged combination, the time-gap number of the corresponding input time slot of output time solt that obtains is stored among the time slot connection relational table RAM successively;
S23, controller are read each time slot of output time solt in order from time slot connection relational table RAM annexation, and from the datarams block RAM, read out corresponding input data according to this annexation;
S24, the input data that obtain among the step S23 are carried out and go here and there conversion, obtain 2M serial output E1 link.
Described datarams block RAM and time slot connection relational table RAM all have 2048 memory spaces.
Further, the HDLC channel slot testing process of described step S3 is as follows:
S31, at first add an E1 link to be scanned, and check whether current E1 link has the circuit alarm,, and it is labeled as scans, continue to add an E1 link to be scanned if there is the circuit alarm then to skip this E1 link, otherwise, step S32 directly entered;
S32, from this E1 link 32 kinds of combination of channels of disposable selection, the order of combination of channels is followed successively by 2M link, 64K link, 2*64K link, 3*64K link to the 31*64K link, has 32 links;
S33, configure the parameter of the 32 paths combination of selecting, check whether the hdlc controller corresponding with described 32 paths receives correct signalling system No.7 bag behind the time-delay 300ms, if receive correct signalling system No.7 Bao Ze the signalling system No.7 channel parameters of this hdlc controller is write the scan chain circuit pond, and detect whether to also have the not E1 link of scanning, scan direct detection whether not next bar E1 link of scanning is arranged otherwise abandon this;
S34, if also have the not E1 link of scanning, then add this E1 link of scanning, otherwise, after all E1 links have scanned, the signalling system No.7 channel parameters that writes down in the above-mentioned scan chain circuit pond is write in the time slot connection relational table.
Further, the implementation that converges of the described intersection of step S4 is: finish signalling system No.7 and output to the E1 output port by reading the time slot connection relational table.
Signalling system No.7 passage checkout gear based on E1 comprises:
E1 imports acquisition module: be used to gather the multichannel E1 input signal that has signalling system No.7;
The PCM cross-connect module: the multichannel E1 input signal that is used for collecting carries out the time slot interconnection;
HDLC channel slot detection module: the signal slot that is used for obtaining after intersecting carries out passage and detects;
E1 exports sending module: be used for detected effective signalling system No.7 channel slot intersection is converged to the E1 output port, described E1 output port is connected with the signal collecting device by follow-up E1 high resistant head;
The input of described PCM cross-connect module and E1 input acquisition module join, and output joins with HDLC channel slot detection module and E1 output sending module respectively.
Further, described E1 input acquisition module has 64 road E1 input ports, described PCM cross-connect module is supported 64 * 64 2M code streams, it is the clog-free full intersection of 2048*2048 64K passage, described HDLC channel slot detection module includes 32 road hdlc controllers, can detect 32 kinds of combination of channels simultaneously, described E1 output sending module has 16 road E1 output ports.
Further, this device is realized by the cpu peripheral that the extensive PFGA of a slice and a slice are used for parameter configuration and realization network management function.
The invention has the beneficial effects as follows: because this method and device have been finished signalling system No.7 from being input to the convergence of output, what the time slot of output E1 link all transmitted is signalling system No.7, can avoid like this because the constantly parameter of the HDLC passage of human configuration collecting device and the mistake that may occur, but also can save the E1 interface resource of collecting device.In addition, because this device only just can realize that by a slice FPGA and external CPU system architecture is succinctly reasonable, implement fairly simple.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples.
Fig. 1 is the flow chart of steps of detection method of the present invention;
Fig. 2 is the flow chart of Fig. 1 step S2;
Fig. 3 is the testing process figure of Fig. 1 step S3;
Fig. 4 is the structure chart of apparatus of the present invention.
Embodiment
With reference to Fig. 1, a kind of signalling system No.7 passage detection method based on E1 may further comprise the steps:
S1, the E1 input acquisition step that is used to gather the multichannel E1 input signal that has signalling system No.7;
S2, the multichannel E1 input signal that is used for collecting carry out the cross-coupled PCM interconnection of time slot step;
S3, the signal slot that obtains after being used for intersecting carry out the HDLC channel slot that passage detects and detect step;
S4, be used for the detected effective signalling system No.7 channel slot of S3 is intersected the E1 output forwarding step that converges to the E1 output port, described E1 output port is connected with follow-up E1 high resistant head.
As preferred embodiment, described step S1 supports to gather simultaneously 64 road E1 input signals, 64 * 64 2M code streams are supported in time slot interconnection described in the step S2, it is the clog-free full intersection of 2048*2048 64K passage, passage among the step S3 detects and includes 32 road hdlc controllers, can detect 32 kinds of combination of channels simultaneously.This method can be monitored the signalling system No.7 in 64 road E1 signals simultaneously.
As preferred embodiment, the E1 output port described in the step S4 has 16 road E1 output ports.
With reference to Fig. 2, the idiographic flow of described step S2 is as follows:
S21, under the control of E1 signal frame lock-out pulse, the data of each time slot of multichannel E1 input signal of collecting are converted to the byte of 8bit, under the effect of controller, deposit in the datarams block RAM according to time-slot sequence;
S22, obtain output time solt after multichannel E1 input signal time slot rearranged combination by required interconnection status requirement, the time-gap number of the corresponding input time slot of output time solt that obtains is stored among the time slot connection relational table RAM successively;
S23, controller are read each time slot of output time solt in order from time slot connection relational table RAM annexation, and from the datarams block RAM, read out corresponding input data according to this annexation;
S24, the input data that obtain among the step S23 are carried out and go here and there conversion, obtain 2M serial output E1 link.
As preferred embodiment, described datarams block RAM and time slot connection relational table RAM all have 2048 memory spaces.
With reference to Fig. 3, the HDLC channel slot testing process of described step S3 is as follows:
S31, at first add an E1 link to be scanned, and check whether current E1 link has the circuit alarm,, and it is labeled as scans, continue to add an E1 link to be scanned if there is the circuit alarm then to skip this E1 link, otherwise, step S32 directly entered;
S32, from this E1 link 32 kinds of combination of channels of disposable selection, the order of combination of channels is followed successively by 2M link, 64K link, 2*64K link, 3*64K link to the 31*64K link, has 32 links;
S33, configure the parameter of the 32 paths combination of selecting, check whether the hdlc controller corresponding with described 32 paths receives correct signalling system No.7 bag behind the time-delay 300ms, if receive correct signalling system No.7 Bao Ze the signalling system No.7 channel parameters of this hdlc controller is write the scan chain circuit pond, and detect whether to also have the not E1 link of scanning, scan direct detection whether not next bar E1 link of scanning is arranged otherwise abandon this;
S34, if also have the not E1 link of scanning, then add this E1 link of scanning, otherwise, after all E1 links have scanned, the signalling system No.7 channel parameters that writes down in the above-mentioned scan chain circuit pond is write in the time slot connection relational table.
As preferred embodiment, the implementation that the described intersection of step S4 converges is, finishes signalling system No.7 and outputs to the E1 output port by reading the time slot connection relational table.
Signalling system No.7 passage checkout gear based on E1 comprises:
E1 imports acquisition module: be used to gather the multichannel E1 input signal that has signalling system No.7;
The PCM cross-connect module: the multichannel E1 input signal that is used for collecting carries out the time slot interconnection;
HDLC channel slot detection module: the signal slot that is used for obtaining after intersecting carries out passage and detects;
E1 exports sending module: be used for detected effective signalling system No.7 channel slot intersection is converged to the E1 output port, described E1 output port is connected with the signal collecting device by follow-up E1 high resistant head;
The input of described PCM cross-connect module and E1 input acquisition module join, and output joins with HDLC channel slot detection module and E1 output sending module respectively.
As preferred embodiment, described E1 input acquisition module has 64 road E1 input ports, described PCM cross-connect module is supported 64 * 64 2M code streams, it is the clog-free full intersection of 2048*2048 64K passage, described HDLC channel slot detection module includes 32 road hdlc controllers, can detect 32 kinds of combination of channels simultaneously, described E1 output sending module has 16 road E1 output ports.
As preferred embodiment, this device is used for parameter configuration by the extensive PFGA of a slice and a slice and realizes the cpu peripheral realization of network management function.
More than be that the preferable enforcement of the present invention is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite of spirit of the present invention, modification that these are equal to or replacement all are included in the application's claim institute restricted portion.
Claims (10)
1. signalling system No.7 passage detection method based on E1 is characterized in that: may further comprise the steps,
S1, the E1 input acquisition step that is used to gather the multichannel E1 input signal that has signalling system No.7;
S2, the multichannel E1 input signal that is used for collecting carry out the cross-coupled PCM interconnection of time slot step;
S3, the signal slot that obtains after being used for intersecting carry out the HDLC channel slot that passage detects and detect step;
S4, be used for the detected effective signalling system No.7 channel slot of S3 is intersected the E1 output forwarding step that converges to the E1 output port, described E1 output port is connected with follow-up E1 high resistant head.
2. a kind of signalling system No.7 passage detection method according to claim 1 based on E1, it is characterized in that: described step S1 supports to gather simultaneously 64 road E1 input signals, 64 * 64 2M code streams are supported in time slot interconnection described in the step S2, it is the clog-free full intersection of 2048*2048 64K passage, passage among the step S3 detects and includes 32 road hdlc controllers, can detect 32 kinds of combination of channels simultaneously.
3. a kind of signalling system No.7 passage detection method based on E1 according to claim 1, it is characterized in that: the E1 output port described in the step S4 has 16 road E1 output ports.
4. a kind of signalling system No.7 passage detection method according to claim 2 based on E1, it is characterized in that: the idiographic flow of described step S2 is as follows,
S21, under the control of E1 signal frame lock-out pulse, the data of each time slot of multichannel E1 input signal of collecting are converted to the byte of 8bit, under the effect of controller, deposit in the datarams block RAM according to time-slot sequence;
S22, obtain output time solt after multichannel E1 input signal time slot rearranged combination, the time-gap number of the corresponding input time slot of output time solt that obtains is stored among the time slot connection relational table RAM successively;
S23, controller are read each time slot of output time solt in order from time slot connection relational table RAM annexation, and from the datarams block RAM, read out corresponding input data according to this annexation;
S24, the input data that obtain among the step S23 are carried out and go here and there conversion, obtain 2M serial output E1 link.
5. a kind of signalling system No.7 passage detection method based on E1 according to claim 4, it is characterized in that: described datarams block RAM and time slot connection relational table RAM all have 2048 memory spaces.
6. a kind of signalling system No.7 passage detection method according to claim 2 based on E1, it is characterized in that: the HDLC channel slot testing process of described step S3 is as follows,
S31, at first add an E1 link to be scanned, and check whether current E1 link has the circuit alarm,, and it is labeled as scans, continue to add an E1 link to be scanned if there is the circuit alarm then to skip this E1 link, otherwise, step S32 directly entered;
S32, from this E1 link 32 kinds of combination of channels of disposable selection, the order of combination of channels is followed successively by 2M link, 64K link, 2*64K link, 3*64K link to the 31*64K link, has 32 links;
S33, configure the parameter of the 32 paths combination of selecting, check whether the hdlc controller corresponding with described 32 paths receives correct signalling system No.7 bag behind the time-delay 300ms, if receive correct signalling system No.7 Bao Ze the signalling system No.7 channel parameters of this hdlc controller is write the scan chain circuit pond, and detect whether to also have the not E1 link of scanning, scan direct detection whether not next bar E1 link of scanning is arranged otherwise abandon this;
S34, if also have the not E1 link of scanning, then add this E1 link of scanning, otherwise, after all E1 links have scanned, the signalling system No.7 channel parameters that writes down in the above-mentioned scan chain circuit pond is write in the time slot connection relational table.
7. a kind of signalling system No.7 passage detection method based on E1 according to claim 1 is characterized in that: the implementation that the described intersection of step S4 converges is, finishes signalling system No.7 and outputs to the E1 output port by reading the time slot connection relational table.
8. based on the signalling system No.7 passage checkout gear of E1, it is characterized in that: comprise,
E1 imports acquisition module: be used to gather the multichannel E1 input signal that has signalling system No.7;
The PCM cross-connect module: the multichannel E1 input signal that is used for collecting carries out the time slot interconnection;
HDLC channel slot detection module: the signal slot that is used for obtaining after intersecting carries out passage and detects;
E1 exports sending module: be used for detected effective signalling system No.7 channel slot intersection is converged to the E1 output port, described E1 output port is connected with the signal collecting device by follow-up E1 high resistant head;
The input of described PCM cross-connect module and E1 input acquisition module join, and output joins with HDLC channel slot detection module and E1 output sending module respectively.
9. the signalling system No.7 passage checkout gear based on E1 according to claim 8, it is characterized in that: described E1 input acquisition module has 64 road E1 input ports, described PCM cross-connect module is supported 64 * 64 2M code streams, it is the clog-free full intersection of 2048*2048 64K passage, described HDLC channel slot detection module includes 32 road hdlc controllers, can detect 32 kinds of combination of channels simultaneously, described E1 output sending module has 16 road E1 output ports.
10. it is characterized in that according to Claim 8 or 9 described signalling system No.7 passage checkout gears based on E1: this device is used for parameter configuration by the extensive PFGA of a slice and a slice and realizes that the cpu peripheral of network management function realizes.
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| CN104038369A (en) * | 2014-05-15 | 2014-09-10 | 国家电网公司 | Acquisition early-warning system and method for number-7 signaling network messages |
| CN104244119A (en) * | 2013-12-26 | 2014-12-24 | 深圳市邦彦信息技术有限公司 | Time slot exchange device and method based on FPGA |
| CN113037537A (en) * | 2021-02-04 | 2021-06-25 | 广州广哈通信股份有限公司 | Management system of E1 equipment |
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| CN102202243B (en) | 2014-04-09 |
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