CN102201815A - Binary operation decoding device with high operation frequency - Google Patents
Binary operation decoding device with high operation frequency Download PDFInfo
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Abstract
The invention provides a binary operation decoding device with high operation frequency. The binary operation decoding device comprises a first lookup table, a second lookup table, a third lookup table, a fourth lookup table, a first multiplexer and a second multiplexer, wherein the input ends of the first and second lookup tables are coupled with the output end of a first register to receive signals from the first register; the input end of the third lookup table is coupled with the output end of the first lookup table to receive the signals from the first lookup table; the input end of the fourth lookup table is coupled with the output end of the second lookup table to receive the signals from the second lookup table; the first multiplexer is provided with a first input end used for receiving the signals from the third lookup table, and a second input end used for receiving the signals from the fourth lookup table; and the second multiplexer is provided with the first input end used for receiving the signals from the third lookup table, and the second input end used for receiving the signals from the second lookup table.
Description
Technical field
The present invention relates to the in full position decoder of adaptive binary arithmetic coding of a multidigit, particularly relate to a kind of full text adaptive binary arithmetic coding decoder of two decision bit of the critical path with shortening.
Background technology
(Context-adaptive Binary ArithmeticCoding, CABAC) decoding algorithm is to utilize basic continuous computing to remove to calculate scope, skew and the look-up table that is used for situational variable to adaptive binary arithmetic coding in full.The data-dependent characteristic of full text adaptive binary arithmetic coding decoding, cause when handling high definition image in real time, in full the adaptive binary arithmetic coding decoding must be done the computing of per second 3,000,000,000 times, and therefore making in full, the adaptive binary arithmetic coding decoding is difficult to reach high-speed decoding.Basically, the position decoder of adaptive binary arithmetic coding comprises a decision bit decoder and a bypass position decoder in full, and by experiment, the 80%-90% position in all is encoded into decision bit as can be known, and all the other positions are encoded into the bypass position.Though inventors' such as Jahanghir United States Patent (USP) the 7th, 262, having disclosed for No. 722 to use utilizes parallel framework to improve the method for the usefulness of adaptive binary arithmetic coding in full, but in full the adaptive binary arithmetic coding decoding algorithm is unlike other video decoded instrument of standard H.264/AVC, utilize parallel framework to go to improve the usefulness of adaptive binary arithmetic coding in full and is not easy.Because the adaptive binary arithmetic coding decoding is to use the decoding of consecutive order in full,, the decoding of consecutive order becomes the H.264/AVC main bottleneck of standard yet can making the full text adaptive binary arithmetic coding decode.
Summary of the invention
One embodiment of the invention disclose a kind of multidigit position decoder of adaptive binary arithmetic coding in full, comprise one first look-up table, have the output that an input is coupled to one first register, in order to receive the signal of this first register output; One second look-up table has the output that an input is coupled to this first register, in order to receive the signal of this first register output; One the 3rd look-up table has the output that an input is coupled to this first look-up table, in order to receive the signal of this first look-up table output; One the 4th look-up table has the output that an input is coupled to this second look-up table, in order to receive the signal of this second look-up table output; One first multiplexer has the output that a first input end is coupled to the 3rd look-up table, and in order to receive the signal of the 3rd look-up table output, one second input is coupled to the output of the 4th look-up table, in order to receive the signal of the 4th look-up table output; And one second multiplexer, have a first input end and be coupled to the output of this first look-up table, in order to receive the signal of the 3rd look-up table output, one second input is coupled to the output of this second look-up table, in order to receive the signal of this second look-up table output; Wherein this first multiplexer and this second multiplexer are all controlled by one first signal.This decoder also comprises one second register, a first adder, a second adder and one first comparison module of coupled in series, and this first comparison module is in order to export this first signal.This decoder also comprises one the 3rd multiplexer, has a first input end and is coupled to the output of this second multiplexer by one the 3rd register, in order to receive the signal of this second multiplexer output; One the 5th look-up table has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal of the 3rd multiplexer output; One the 6th look-up table has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal of the 3rd multiplexer output; One the 7th look-up table has the output that an input is coupled to the 5th look-up table, in order to receive the signal of the 5th look-up table output; One the 8th look-up table has the output that an input is coupled to the 6th look-up table, in order to receive the signal of the 6th look-up table output; One the 4th multiplexer has the output that a first input end is coupled to the 7th look-up table, and in order to receive the signal of the 7th look-up table output, one second input is coupled to the output of the 8th look-up table, in order to receive the signal of the 8th look-up table output; And one the 5th multiplexer, have a first input end and be coupled to the output of the 5th look-up table, in order to receive the signal of the 5th look-up table output, one second input is coupled to the output of the 6th look-up table, in order to receive the signal of the 6th look-up table output; Wherein the 4th multiplexer and the 5th multiplexer are all controlled by one second signal; Wherein the input of this first register is coupled to the output of the 5th multiplexer, in order to store the signal of the 5th multiplexer output.This decoder also comprises one the 3rd adder, one the 4th adder and one second comparison module of coupled in series, and this second comparison module is in order to export this second signal.
Description of drawings
Fig. 1 is the schematic diagram of video signal processing system.
Fig. 2 is the schematic diagram of decision bit decoder of the video signal processing system of Fig. 1.
Fig. 3 is the critical path of the decision bit decoder of key diagram 2.
Fig. 4 is the schematic diagram of the decision bit decoder that discloses of one embodiment of the invention.
Fig. 5 and Fig. 6 are the detailed architecture of the decision bit decoder of key diagram 4.
Fig. 7 and Fig. 8 are the critical paths of the decision bit decoder of key diagram 5 and Fig. 6.
The reference numeral explanation
10 video signal processing systems
11 video signal sources
12 video signal processors
13 video display
20 decoders
25,40,405 registers
35 decision bit decoders
30 bypass position decoders
100,300,400 decoders
102,116,502 range registers
103,503,115,530 state indices registers
104,652 rLPS look-up tables
105,505,611 LPS look-up tables
106,506,612 MPS look-up tables
107,110,111,112,415,409,515,516,517,518,519,610,616,623,618,620,621,622 multiplexers
108,109,508,509,641,643 adders
113,513,630 comparison modules
114,514,635 ruleization modules again
117,501,101 offset registers
118,520 incoming bit streams
119,120 updating value
407,500,700 first decision bit decoders
420,600,800 second decision bit decoders
552,614 the one rLPS look-up tables
555,613 the 2nd rLPS look-up tables
550 rLPS registers
Embodiment
Fig. 1 is the schematic diagram of video signal processing system 10 of the position decoder (bin decoder) of decision multidigit.Video signal processing system 10 comprises a video signal source 11, a video signal processor 12 and a video display 13.Video signal source 11 can be to have utilized standard H.264/AVC to compress and/or the recasting of encoding or the video signal of transmission, wherein H.264/AVC standard is that employing full text adaptive binary arithmetic coding (context-based adaptive binary arithmetic coding, CABAC) compress and/or encode by technology.H.264/AVC video signal source 11 is exported signal to video signal processor 12 and is decoded and reassemble into original video signal, exports video display 13 to by video signal processor 12 again after finishing and watches for the user.
Fig. 2 is the position decoder 100 that every clock of video signal processing system 10 is handled a position (bin-per-cycle).Position decoder 100 can comprise an offset register 101, one range registers 102, one state indices register 103, one reference is possibility state (reference least probablestate least, rLPS) look-up table 104, least may state (least probable state, LPS) look-up table 105, one most probable state (most probable state, MPS) look-up table 106, a plurality of adders 108,109, a plurality of multiplexers 107,110,111,112, one comparison module 113, one ruleization module 114, one state indices registers 115, one range registers 116 again, one offset register 117 and an incoming bit stream 118.The information that is stored in offset register 101, range registers 102 and state indices register 103 can be by the output input of the register 25 of the decoder 20 of Fig. 1, or in certain embodiments, offset register 101, range registers 102 and state indices register 103 are part compositions of the register 35 of Fig. 1.
The input of the input of the input of rLPS look-up table 104, MPS look-up table 106 and LPS look-up table 105 is coupled to the output of state indices register 103, the present full text state (context state) of output output of state indices register 103, and present full text state can be used to from rLPS look-up table 104, MPS look-up table 106, the suitable value of LPS look-up table 105 acquisitions.The output of MPS look-up table 106 is coupled to the first input end of multiplexer 112, the output of LPS look-up table 105 is coupled to second input of multiplexer 112, and the first input end of multiplexer 112 is in order to receive the most probable state of MPS look-up table 106 outputs, the least possibility state that second input of multiplexer 112 is exported in order to receive LPS look-up table 105.The input of multiplexer 107 is coupled to the output of rLPS look-up table 104, the control input end of multiplexer 107 is coupled to the output of range registers 102, the input of multiplexer 107 is in order to receive the possible reference state that rLPS look-up table 104 is exported, the control input end of multiplexer 107 is in order to the signal of range of receiving register 102 outputs, and the signal of range registers 102 outputs is in order to control multiplexer 107.The output of multiplexer 107 is coupled to the first input end of adder 108 and the first input end of multiplexer 110, and second input of adder 108 is coupled to the output of range registers 102.In adder 108, the signal of range registers 102 outputs that second input of adder 108 is received will be deducted the signal from the output of the multiplexer that first input end received 107 of adder 108.The output of adder 108 is coupled to second input of multiplexer 110 and the first input end of adder 109, and second input of adder 109 is coupled to the output of offset register 101.In adder 109, the signal of offset register 101 outputs that second input of adder 109 is received will be deducted the signal from the output of the adder that first input end received 108 of adder 109.The first input end of multiplexer 111 is coupled to the output of offset register 101, second input of multiplexer 111 is coupled to the output of adder 109, the first input end of multiplexer 111 is in order to receive the signal of offset register 101 outputs, and second input of multiplexer 111 is in order to receive the difference of adder 109 outputs.
In addition, the output of adder 109 also is coupled to the input of comparison module 113, and the output of comparison module 113 is coupled to the control input end of multiplexer 111,110 and 112.Comparison module 113 is in order to receiving the difference of adder 109 outputs, and whether the difference output of judging adder 109 is less than zero.And the judged result of comparison module 113 outputs is in order to control multiplexer 111,110 and 112.In addition, the output of multiplexer 112 is coupled to the input of state indices register 115, and the signal of multiplexer 112 outputs is in order to update mode index register 115.
Again the first input end of ruleization module 114 is in order to receive incoming bit stream 118, again second input of ruleization module 114 is coupled to the output of multiplexer 111, in order to receive the signal of multiplexer 111 outputs, again the 3rd input of ruleization module 114 is coupled to the output of multiplexer 110, in order to receive the signal of multiplexer 110 outputs, again first output of ruleization module 114 is coupled to the input of offset register 117, again second input of ruleization module 114 is coupled to the input of range registers 116, wherein again the signal of ruleization module 114 output in order to upgrade offset register 117 and range registers 116 in turn.Offset register 117 output updating value 119 and range registers 116 output updating value 120.Wherein updating value 119, updating value 120 will be used in decode cycle next time simultaneously with the state indices register 115 that upgrades.
The position decoder 300 of Fig. 3 comprises the schematic diagram of critical path for the position decoder 100 of Fig. 2.In Fig. 3, how the critical path (critical path) that the every clock of position decoder 300 explanations is handled the position decoder of a position (bin-per-cycle) becomes a design subject under discussion.As shown in Figure 3, the every clock critical path of handling the position decoder 300 of a position (bin-per-cycle) begins through rLPS look-up table 104, multiplexer 107, adder 108, adder 109, comparison module 113, multiplexer 111, ruleization module 114 and the offset register 117 that arrives again from the output of state indices register 103.The signal of the range registers that the control input end received 102 outputs of multiplexer 107 in order to which signal in a plurality of signals of the output of decision rLPS look-up table 104 needs to be passed to adder 108 via multiplexer 107.In adder 108, the signal of range registers 102 outputs that second input of adder 108 is received will be deducted the signal of being exported from the multiplexer that first input end received 107 of adder 108.In adder 109, the signal of offset register 101 outputs that second input of adder 109 is received will be deducted the signal from the output of the adder that first input end received 108 of adder 109.The input of comparison module 113 is in order to receive the difference of adder 109 outputs, and the judged result of comparison module 113 is then in order to control multiplexer 111.The signal of multiplexer 111 output offers again ruleization module 114 in order to renewal offset register 117, and the updating value of being exported by offset register 117 119 will be used in next time in the decode cycle.Therefore, the critical path of the position decoder 300 of Fig. 3 ends at the output of offset register 117.Yet the disposal ability that every clock is handled the position decoder 300 of a position (bin-per-cycle) is that be not high enough to can be in order to real-time decoding video signal H.264/AVC, and particularly when handling high resolution image, the disposal ability of position decoder 300 is more inadequate.
In order to increase disposal ability, every clock is as shown in Figure 4 handled the position decoder 400 of two positions except being used to position of every clock decoding, also can two positions of every clock decoding.Fig. 4 is the schematic diagram that every clock that one embodiment of the invention disclose is handled the position decoder 400 of two positions.Position decoder 400 comprises a register 405, one first decision bit decoder 407, two multiplexers 415,409 and one second decision bit decoder 420.Register 405 is coupled to the first decision bit decoder 407 and multiplexer 409.The first decision bit decoder 407 is coupled to multiplexer 415, multiplexer 409 and the second decision bit decoder 420.The output of the first decision bit decoder 407 is exported Offset1, Range1 and is followed the RLPS1 signal of update mode, wherein Offset1 and Range1 are received by the second decision bit decoder 420, input to multiplexer 415 but the RLPS signal then is accompanied by outside CTX2 RLPS/CTX2 State signal.Multiplexer 415 is controlled and export selected results to the second decision bit decoder 420 by a Source select signal.Output output signal Offset2, Range2, RLPS2 and the NextST of the second decision bit decoder 420, wherein signal Offset2, Range2, RLPS2 and the NextST of the output of the second decision bit decoder 420 can with from the RLPS1 signal of the first decision bit decoder 407 input multiplexer 409 in the lump.The signal of multiplexer 409 outputs then passes back to register 405, therefore can begin another circulation.
Though, for the high-resolution video signal of standard H.264/AVC, the position decoder that every clock is handled two positions has the acceptable disposal ability, but its critical path remains the subject under discussion of design, but through rearranging decoding process and mobile look-up table can effectively shorten the position decoder of two positions of every clock processing to the mode of previous stage critical path.Can realize the position decoder of two positions of every clock processing according to the framework of Fig. 5.
Please refer to Fig. 5 and Fig. 6.Fig. 5 illustrates the first decision bit decoder 500, and Fig. 6 illustrates the second decision bit decoder 600, and the connection relationship between the first decision bit decoder 500 and the second decision bit decoder 600.In Fig. 5, the first decision bit decoder 500 comprises an offset register 501, a range registers 502, a rLPS register 550, a state indices register 503, a MPS state look-up table 506, a LPS state look-up table 505, one the one rLPS look-up table 552, one the 2nd rLPS look-up table 555, multiplexer 515-519, adder 508-509, a state indices register 530, a comparison module 513 and ruleization module 514 again.In Fig. 6, the second decision bit decoder 600 comprises a plurality of multiplexers 610,616,623,618,620,621,622, one ruleization module 635 again, a plurality of adder 641,643, one rLPS look-up tables 652, one MPS state look-up tables 612, one LPS state look-up table 611, one the one rLPS look-up table 614, the 2nd rLPS look-up table 613, and a comparison module 630.The input of the input of MPS state look-up table 506 and LPS state look-up table 505 is coupled to the output of state indices register 503, and MPS state look-up table 506 and LPS state look-up table 505 are in order to the current state of accepting state index register 503 outputs.The first input end of the input of the one rLPS look-up table 552 and multiplexer 515 is coupled to the output of MPS state look-up table 506, in order to receive MPS state look-up table 506 selected most probable states.The first input end of multiplexer 516 is coupled to the output of a rLPS look-up table 552, in order to receive one 32 signals of a rLPS look-up table 552 outputs.Second input of the input of the 2nd rLPS look-up table 555 and multiplexer 515 is coupled to the output of LPS state look-up table 505, in order to receive LPS state look-up table 505 selected least possibility states, second input of multiplexer 516 is coupled to the output of the 2nd rLPS look-up table 555, in order to receive one 32 signals of the 2nd rLPS look-up table 555 outputs.
The first input end of the first input end of adder 508 and multiplexer 517 is coupled to the output of rLPS register 550, second input of adder 508 is coupled to the output of range registers 502, the first input end of the first input end of multiplexer 517 and adder 508 is in order to receive the signal of rLPS register 550 outputs, and second input of adder 508 is in order to the signal of range of receiving register 502 outputs.In adder 508, the signal of range registers 502 outputs will be deducted the signal from 550 outputs of rLPS register, the output of adder 508 is coupled to second input of multiplexer 517 and second input of adder 509, and second input of adder 509 and second input of multiplexer 517 are in order to receive the signal of adder 508 outputs.The output of offset register 501 is coupled to the first input end of adder 509 and the first input end of multiplexer 518, and the first input end of the first input end of multiplexer 518 and adder 509 is in order to receive the signal of offset register 501 outputs.In adder 509, the signal of offset register 501 outputs will be deducted the signal from adder 508 outputs.Second input of multiplexer 518 is coupled to the output of adder 509, in order to receive the difference of adder 509 outputs.The output of adder 509 also is coupled to the input of comparison module 513, and the input of comparison module 513 is in order to the difference of reception adder 509 outputs, and comparison module 513 judges that whether the difference output of adder 509 is less than zero.The output of comparison module 513 is coupled to the control input end of multiplexer 518,517,516 and 515, and wherein the judged result of comparison module 113 is in order to control multiplexer 518,517,516 and 515.
In addition, the output of multiplexer 515 is coupled to the input of state indices register 530, and the signal of multiplexer 515 outputs is in order to update mode index register 530.State indices register 530 can be exported the first input end (as shown in Figure 6) of multiplexer 610 of state to the second decision bit decoder 600 of renewal in turn.Similarly, the first input end of multiplexer 519 is coupled to the output of multiplexer 516, second input of multiplexer 519 is coupled to another rLPS look-up table, after multiplexer 519 receives the signal of exporting from multiplexer 516 and another rLPS look-up table, will export the first input end of the multiplexer 616 of one 32 signal to the second decision bit decoders 600.Again the first input end of ruleization module 514 is in order to receive incoming bit stream 520, second input is in order to receive the signal of multiplexer 518 outputs, the 3rd input is in order to receive the signal of multiplexer 517 outputs, the first input end of the first input end of multiplexer 623 and adder 641 receives again the skew signal of first output output of ruleization module 514 then, second input of adder 643 receives again the scope signal of second output output of ruleization module 514, again ruleization module 635 receives again the shifted bits stream (shifted bitstream) of the 3rd output output of ruleization module 514, and the control input end of multiplexer 618 receives again 2 highest significant positions in the scope signal that second output of ruleization module 514 exports, and (Most Significant Bit is MSB) as its controlling signal (as shown in Figure 6).
Second input of multiplexer 610 and the input of rLPS look-up table 652 receive a StateIndex2 signal.Second input of multiplexer 616 is coupled to the output of rLPS look-up table 652, in order to the signal (first input end of multiplexer 616 is coupled to multiplexer 519, in order to receive the rLPS signal from multiplexer 519 outputs) that receives 652 outputs of rLPS look-up table.The control input end of multiplexer 610 and multiplexer 616 then receives a Stage2_Source_Se1 signal, and the Stage2_Source_Se1 signal is used for controlling signal as multiplexer 610 and multiplexer 616.
The input of the input of MPS state look-up table 612 and LPS state look-up table 611 is coupled to the output of multiplexer 610, in order to receive the signal of multiplexer 610 outputs.The first input end of the input of the one rLPS look-up table 614 and multiplexer 620 is coupled to the output of MPS state look-up table 612, in order to receive MPS state look-up table 612 selected most probable states.The first input end of multiplexer 621 is coupled to the output of a rLPS look-up table 614, in order to receive one 32 signals of a rLPS look-up table 614 outputs.Second input of the input of the 2nd rLPS look-up table 613 and multiplexer 620 is coupled to the output of LPS state look-up table 611, in order to receive LPS state look-up table 611 selected least possibility states.Second input of multiplexer 621 is coupled to the output of the 2nd rLPS look-up table 613, in order to receive 32 signals of the 2nd rLPS look-up table 613 outputs.
The input of multiplexer 618 is coupled to the output of multiplexer 616; Selection according to the Stage2_Source_Se1 signal, multiplexer 618 can receive 1 group of 8 signal of multiplexer 616 outputs, multiplexer 618 then is subjected to controlling from 2 highest significant position signals of ruleization module 514 again, exports 1 group of 8 signal to the first input end of adder 643 and the first input end of multiplexer 622.Second input of multiplexer 622 and second input of adder 641 are coupled to the output of adder 643.In adder 643, after adder 643 will be deducted 1 group of 8 signal exporting from multiplexer 618 from the scope signal of ruleization module 514 outputs again, the output difference was to multiplexer 622 and adder 641.In adder 641, adder 641 will be deducted the difference signal of exporting from adder 643 from the skew signal of ruleization module 514 outputs again.Second input of multiplexer 623 is coupled to the output of adder 641, in order to receive the difference of adder 641 outputs.The output of adder 641 also is coupled to the input of comparison module 630, and the input of comparison module 630 is in order to the difference of reception adder 641 outputs, and comparison module 630 judges that whether the difference output of adder 641 is less than zero.The output of comparison module 630 is coupled to the control input end of multiplexer 623,622,621 and 620, and wherein the judged result of comparison module 630 is in order to control multiplexer 623,622,621 and 620.Again the first input end of ruleization module 635 is in order to receive the shifted bits stream from the module of ruleization again 514 of the first decision bit decoder 500, second input is coupled to the output of multiplexer 623, in order to receive the signal of multiplexer 623 outputs, the 3rd input is coupled to the output of multiplexer 622, in order to receive the signal of multiplexer 622 outputs, the range registers 502 that the offset register 501 of first output output, one skew signal to the first decision bit decoder 500 and second output are exported scope signal to the first a decision bit decoder 500.And offset register 501 and range registers 502 will recycle from the skew signal and the scope signal of ruleization module 635 again at next.Similarly, the signal of multiplexer 621 output is delivered to the signal of rLPS register 550 and multiplexer 620 outputs and is delivered to state indices register 503, allows the first decision bit decoder 500 recycle at next.
Fig. 7 and Fig. 8 are the critical paths between detail bit decoder 500 and the position decoder 600.As shown in Figure 7 and Figure 8, position decoder 500 and position have between the decoder 600 critical path to begin output from range registers 502 through adder 508, output by adder 508 extends to adder 509 again, continuation extends to comparison module 513 from the output of adder 509, it is after the output of multiplexer 517, again via the output of ruleization module 514 again to adder 643, continue to extend to adder 641 from the output of adder 643, again then to comparison module 630, at last, by the signal of comparison module 630 output go to control multiplexer 623 via ruleization module 635 outputs again next circulate the skew signal of palpus.
In summary, compared with traditional design, every clock is handled the critical path of the position decoder of two positions and is handled the next length of position decoder of a position than every clock.But the mode of rearranging decoding process and mobile look-up table that the present invention proposes has reduced the length of critical path.Design of the present invention demonstrates on the time demand and reduces by 33%.For example, before the present invention's improvement, the frequency that every clock is handled the position decoder of two positions is 150MHz (a Fujitsu 90nm technology), but adopt proposed by the invention rearrange decoding process after, the frequency that every clock is handled the position decoder of two positions can be promoted to 225MHz.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. the binary arithmetic operation decoding device of a high computing frequency comprises;
One first look-up table has the output that an input is coupled to one first register, in order to receive the signal of this first register output;
One second look-up table has the output that an input is coupled to this first register, in order to receive the signal of this first register output;
One the 3rd look-up table has the output that an input is coupled to this first look-up table, in order to receive the signal of this first look-up table output;
One the 4th look-up table has the output that an input is coupled to this second look-up table, in order to receive the signal of this second look-up table output;
One first multiplexer has the output that a first input end is coupled to the 3rd look-up table, and in order to receive the signal of the 3rd look-up table output, one second input is coupled to the output of the 4th look-up table, in order to receive the signal of the 4th look-up table output; And
One second multiplexer has the output that a first input end is coupled to this first look-up table, and in order to receive the signal of this first look-up table output, one second input is coupled to the output of this second look-up table, in order to receive the signal of this second look-up table output;
Wherein this first multiplexer and this second multiplexer are all controlled by one first signal.
2. binary arithmetic operation decoding device as claimed in claim 1 also comprises one second register, a first adder, a second adder and one first comparison module of coupled in series, and this first comparison module is in order to export this first signal.
3. binary arithmetic operation decoding device as claimed in claim 1 also comprises:
One the 3rd multiplexer has a first input end and is coupled to the output of this second multiplexer by one the 3rd register, in order to receive the signal of this second multiplexer output;
One the 5th look-up table has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal of the 3rd multiplexer output;
One the 6th look-up table has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal of the 3rd multiplexer output;
One the 7th look-up table has the output that an input is coupled to the 5th look-up table, in order to receive the signal of the 5th look-up table output;
One the 8th look-up table has the output that an input is coupled to the 6th look-up table, in order to receive the signal of the 6th look-up table output;
One the 4th multiplexer has the output that a first input end is coupled to the 7th look-up table, and in order to receive the signal of the 7th look-up table output, one second input is coupled to the output of the 8th look-up table, in order to receive the signal of the 8th look-up table output; And
One the 5th multiplexer has the output that a first input end is coupled to the 5th look-up table, and in order to receive the signal of the 5th look-up table output, one second input is coupled to the output of the 6th look-up table, in order to receive the signal of the 6th look-up table output;
Wherein the 4th multiplexer and the 5th multiplexer are all controlled by one second signal.
4. binary arithmetic operation decoding device as claimed in claim 3, wherein the input of this first register is coupled to the output of the 5th multiplexer, in order to store the signal of the 5th multiplexer output.
5. binary arithmetic operation decoding device as claimed in claim 3 also comprises one the 3rd adder, one the 4th adder and one second comparison module of coupled in series, and this second comparison module is in order to export this second signal.
6. binary arithmetic operation decoding device as claimed in claim 5 also comprises:
One the 6th multiplexer has the output that a first input end is coupled to this first multiplexer, in order to receive the signal of this first multiplexer output.
7. binary arithmetic operation decoding device as claimed in claim 6 also comprises:
One the 7th multiplexer has the output that a first input end is coupled to the 6th multiplexer, and in order to receive the signal of the 6th multiplexer output, one second input is coupled to the output of one the 9th look-up table, in order to receive the signal of the 9th look-up table output; And
One the 8th multiplexer has the output that an input is coupled to the 7th multiplexer, in order to the signal of the output output that receives the 7th multiplexer.
8. binary arithmetic operation decoding device as claimed in claim 7, wherein the 3rd multiplexer is all controlled by the 3rd an identical signal with the 7th multiplexer.
9. binary arithmetic operation decoding device as claimed in claim 7, wherein the first input end of the 3rd adder is coupled to the output of the 8th multiplexer, in order to receive the signal of the 8th multiplexer output.
10. binary arithmetic operation decoding device as claimed in claim 7 also comprises:
One the 4th register has an output and is coupled to the first input end of this second adder and the first input end of one the 9th multiplexer, and wherein this second adder and the 9th multiplexer are in order to receive the signal of the 4th register output.
11. binary arithmetic operation decoding device as claimed in claim 10 also comprises:
One the 5th register has an output and is coupled to the first input end of this first adder and the first input end of 1 the tenth multiplexer, and wherein this first adder and the tenth multiplexer are in order to receive the signal of the 5th register output.
12. binary arithmetic operation decoding device as claimed in claim 11 also comprises:
One ruleization module again, has a first input end in order to receive an incoming bit stream, one second input is coupled to the output of the 9th multiplexer, in order to receive the signal of the 9th multiplexer output, one the 3rd input is coupled to the output of the tenth multiplexer, in order to receive the signal of the tenth multiplexer output, one first output is coupled to the first input end of the 4th adder, one second output is coupled to second input of the 3rd adder, and wherein second input of the first input end of the 4th adder and the 3rd adder is in order to receive this signal of rule module output again.
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| CN106817307A (en) * | 2015-11-27 | 2017-06-09 | 佛山市顺德区顺达电脑厂有限公司 | For the method for routing of cluster type stocking system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6574651B1 (en) * | 1999-10-01 | 2003-06-03 | Hitachi, Ltd. | Method and apparatus for arithmetic operation on vectored data |
| CN1773868A (en) * | 2004-11-08 | 2006-05-17 | 联发科技股份有限公司 | Path equity operating method and related apparatus for fast witt ratio detector |
| CN101145790A (en) * | 2006-12-08 | 2008-03-19 | 威盛电子股份有限公司 | Decoder, addition-comparison-selection unit and its method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6574651B1 (en) * | 1999-10-01 | 2003-06-03 | Hitachi, Ltd. | Method and apparatus for arithmetic operation on vectored data |
| CN1773868A (en) * | 2004-11-08 | 2006-05-17 | 联发科技股份有限公司 | Path equity operating method and related apparatus for fast witt ratio detector |
| CN101145790A (en) * | 2006-12-08 | 2008-03-19 | 威盛电子股份有限公司 | Decoder, addition-comparison-selection unit and its method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106817307A (en) * | 2015-11-27 | 2017-06-09 | 佛山市顺德区顺达电脑厂有限公司 | For the method for routing of cluster type stocking system |
| CN106817307B (en) * | 2015-11-27 | 2020-09-22 | 佛山市顺德区顺达电脑厂有限公司 | Method for establishing route for cluster type storage system |
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