CN1021862C - Semiconductor device with device separation structure - Google Patents

Abstract

A semiconductor device has a device region, and a device separation region formed on a semiconductor substrate doped with impurities. And, the device separation region has a metal wiring formed on the surface of the device region or the back surface of the substrate. An aluminum region extending in the longitudinal direction connected to the metal wiring is formed within the device separation region.

Description

Semiconductor device with device separation structure

The present invention relates to be contained in semiconductor circuit devices such as memory on the various electronic equipments, electrooptical device, signal processor, particularly the semiconductor device that is improved of metal wiring structure and component isolation structure.

In the past, the component isolation structure in the semiconductor device is shown in Figure 1A.Among the figure, the 1st, metal line, the 2, the 3rd, form the element area of transistor, resistance, electric capacity, light-sensitive element etc., what make these element mutually insulateds is element isolation zone, i.e. the Si layer 5 of Si substrate 4 of Can Zaing and identical doping etc.The current potential of element isolation zone 4,5 is fixed by metal line 1 and 6.

For example, fixedly the element isolation zone of photography element constitutes shown in Figure 1B like that.Among the figure, 4 is P type substrate, 5 ' for n ⁺Buried regions, 2 is n ^-Epitaxially grown layer, 5 is n ⁺Layer.Described n ^- Epitaxial loayer 2 is photoelectric conversion regions, n ⁺Buried regions 5 ' and n ⁺Layer 5 is an element area.

n ^- Epitaxial loayer 2 passes through n ⁺Buried regions 5 ' and n ⁺ Layer 5 keeps positive potential.Because n ^- Epitaxial loayer 2 and n ⁺Layer 5 is in conjunction with the internal electric field that produces, and the electronics that generates under rayed attracted to n ⁺Buried regions 5 ' and n ⁺ Layer 5, and be closed in the pixel that they cross can not be to the pixel diffusion of adjacency in the hole, thus can prevent to interfere with each other.

But prior art also exists the following problem that needs solution.

1. the impedance of element isolation zone 5 reaches number+to hundreds of Ω/.Therefore, if electric current inflow region 5, current potential rise, the parasitic transistor conducting between the element area 2,3 becomes the reason of self-locking and function shakiness etc.

2. because zone 5 impedance, become that element area 2,3 disturbs, the reason of job insecurity.

Particularly for solid camera component,

3. obtain high-octane hole has spread to the zone of adjacency because of being heated.

4. element isolation zone also is a semiconductor, so charge carrier has just taken place in light one irradiation.

5. n ⁺The width of the element isolation layer of silicon can not be top narrow, and this obstacle ， And that has just become to dwindle picture element becomes the obstacle of the high-resolution of solid camera component.

On the other hand, as the metal wiring structure in the highly integrated semiconductor device, for example, shown in Fig. 2 A, be on the surface of Semiconductor substrate such as silicon 51, formation forms the metal wiring layer 53 that Al, Al-Si etc. constitute by the interlayer dielectric 52 that silica etc. constitutes on this interlayer dielectric 52.

In the semiconductor device of metal line with structure like this, strengthen the width of each wiring, the cross section of wiring is increased, the necessary permission magnitude of current of having guaranteed thus respectively to connect up, the area of plane of wiring has just increased, thereby want not increase size of component and the density that improves wiring, just be restricted.

Therefore, in order to improve wiring density, having proposed each the cloth line overlap that makes shown in Fig. 2 B is the semiconductor device of Miltilayer wiring structure.

In this semiconductor device, the double layer of metal wiring stacks by means of insulating film layer.

The manufacture method of the semiconductor device shown in following brief description Fig. 2 B.

At first, on a part of surface of Semiconductor substrate 1, form various necessary function elements such as bipolar transistor, MOS transistor, MOS diode, afterwards, on that part of surface of Semiconductor substrate 51 remainders, form first interlayer dielectric 52 that constitutes by phosphorosilicate glass (PSG) etc. with the atmospheric pressure cvd method, its thickness is 0.5～1.0 micron, then this first interlayer dielectric 52 is annealed.

Then, on described first interlayer dielectric 52, apply photoresist, produce figure, form the opening 52a that above-mentioned each function element extraction electrode is used.Then, use the sputtering method handle, for example, the wiring material that Al-Si constitutes is deposited on the surface of first interlayer dielectric 52 and in the opening 52a, after this forms first wiring layer 53 by the graphic making operation of using photoresist.

Forming thickness with the atmospheric pressure cvd method on first wiring layer 53 and first interlayer dielectric 52 is 0.5～1.0 micron, second interlayer dielectric that is made of PSG.Afterwards, be connected with the upper wiring layer of narrating below, on suitable with it that part of second interlayer dielectric 54 on first wiring layer, 53 tops, form opening 54a by photoetching composition in order to make first wiring layer.

With sputtering method on second interlayer dielectric 54 and in the opening 54a in the deposit by, for example, the wiring material that Al-Si constitutes.Afterwards, form second wiring layer 55 that links to each other with first wiring layer 52 by opening 54a by the photoetching composition method.

After this, on second interlayer dielectric 54 and second wiring layer 55, form thick 0.5～1.0 micron passivating film 56 that constitutes by silicon nitride or silicon dioxide etc. with plasma CVD method, just can produce the semiconductor device of the double layer of metal wire structures that has shown in Fig. 2 B.

So the semiconductor device of the Miltilayer wiring structure that constitutes can be realized the much higher wiring density of semiconductor device than the wire structures of individual layer shown in Fig. 2 A.

But in the semiconductor device of above-mentioned Miltilayer wiring structure, owing to be provided with interlayer dielectric between the wiring on bottom wiring and top, along with the lamination number becomes many, the Surface Vertical dislocation that is formed by wiring portion becomes big.Therefore, wiring portion has just limited the design freedom of wire structures with respect to the shape that connects necessary contact hole between the migration of the position of Semiconductor substrate, each insulating barrier etc.This situation has also limited the raising of wiring density, and wiring density is difficult to surpass certain level.

In addition, in the semiconductor device of Miltilayer wiring structure, owing to get over material layer up, its concave-convex surface is big more, make wiring laminated again and make when carrying out mask alignment in the process of figure, it is big that alignment error just becomes, and therefore wiring can not be precisely defined on the assigned position with respect to Semiconductor substrate very much, and the reliability of wiring has become problem.

Main purpose of the present invention provides the semiconductor device that a kind of wire structures is better than prior art.

Another main purpose of the present invention provides the semiconductor device that a kind of element separation performance is better than prior art.

Another purpose of the present invention provides a kind of semiconductor device, the component isolation structure that this device has is to form element area on doped substrate, in this zone, form the element isolation zone that has mixed with the identical impurity of described substrate, form metal line on the surface of described element area and the back side of described substrate, the feature of this device forms with described metal line the aluminium illuvium that links to each other, vertically extends in described element isolation zone.

Another object of the present invention provides a kind of semiconductor device, this semiconductor device can reduce the element isolation zone of semiconductor device impedance, prevent self-locking and interference etc., obtain stability.

Even a further object of the present invention provides a kind of little semiconductor device that also can guarantee to allow the magnitude of current of the area of plane that can connect up with high positional precision formation wire structures that has.

Another purpose of the present invention provides a kind of semiconductor device, the feature of this device is first element isolation zone that forms a plurality of doping on substrate in the formation element area between substrate and element area, in described element area, formation is the channel metal layer of main component along the aluminium of conduct second element isolation layer of its longitudinal extension or with aluminium, one end of this layer is connected to the two ends of the 1st element isolation layer, and the other end exposes the surface of described element area.

In addition, other purpose of the present invention provides a kind of semiconductor device, the feature of this device is to form element area on dielectric substrate, in this element area, form aluminium that extend longitudinally out, that become element isolation zone or be the channel metal layer of main component with aluminium, this metal level one end contacts with described dielectric substrate, and the other end exposes the surface of described element area.

A further object of the invention provides a kind of semiconductor device, this device deposit aluminium or be the metal of main component selectively in the raceway groove that will form element isolation layer with aluminium, constitute the channel metal layer, this metal level as element isolation zone, can be eliminated the interference between the pixel and can be improved the density of pixel.

Further object of the present invention provides a kind of semiconductor device, this device since can use the channel metal layer as the wiring lead, thereby can dwindle its profile.

Another object of the present invention provides a semiconductor device, and the feature of this device is to be provided with to connect the metal wiring layer of described at least two function element at least in having the semiconductor substrate of two function element.

Below in conjunction with description of drawings the present invention.

Figure 1A, 1B, 2A, 2B are the structure chart of the semiconductor device of explanation prior art.

Fig. 3 is the structure chart of the semiconductor device critical piece of expression first embodiment of the invention.

Fig. 4 is the structure chart of the semiconductor device critical piece of the expression second embodiment of the present invention.

Fig. 5 is the structure chart that is applicable to semiconductor device critical piece of the present invention.

Fig. 6 A is the structure chart that is applicable to semiconductor device critical piece of the present invention, and Fig. 6 B is this manipulated or operated apparatus.

Fig. 7 A～D is applicable to the manufacturing process flow diagram of the manufacture method of semiconductor device of the present invention for expression.

Fig. 8 is the structure chart of the semiconductor device critical piece of expression the present invention the 3rd embodiment.

Fig. 9 is the structure chart of the semiconductor device critical piece of expression the present invention the 4th embodiment.

Figure 10 A, 10B are the schematic diagram of explanation according to logical circuit of the present invention.

Figure 11 is the top plane view of expression according to logical circuit of the present invention.

Figure 12 is for illustrating to apply the constructed profile that positive potential is the wire structures of purpose.

Figure 13 is for illustrating to apply the constructed profile that negative potential is the wire structures of purpose.

Figure 14 is the constructed profile of the embodiment of Miltilayer wiring structure in the explanation semiconductor device of the present invention.

Figure 15 A～15C is the schematic diagram of the wire structures manufacture method of explanation Figure 14.

Figure 16,17 schematic diagrames of example for a film formation device of signal, this device are used for implementing being suitable for forming the film build method according to semiconductor device wiring layer of the present invention.

Figure 18 is the planar structure sketch of Figure 16,17 shown devices.

Matrix moves structure diagram in proper order by arrow to Figure 19 among Figure 18 in order to replenish.

Figure 20 A to 20D is that explanation is suitable for forming the used schematic diagram of the film build method of wiring layer in the semiconductor device according to the invention.

A suitable form of implementation of the present invention is the buried district that the lengthwise that is formed by metal is set in element isolation zone.

For the regulation zone and the situation that the buried district of the lengthwise of metal is electrically connected that are a semiconductor substrate part, take following form of implementation.

For example,, can sidewall all be covered with dielectric film only in trench bottom and the situation that the regulation zone is electrically connected for metal. And for the structure that the sidewall of metal and raceway groove and the part of bottom surface etc. insulate, only cover this part with dielectric film.

Embodiment 1

Fig. 3 is the best figure of expression embodiments of the invention 1 feature.Among the figure, 1 for the element separation that longitudinally forms in element isolation zone 5 with Al-CVD method described later connects up, and 2 is the 1st element area, and 3 is the 2nd element area, and 4 are doping Si substrate, the 5th, doping type and substrate components identical isolated area.

As shown in the figure, owing to make element separation wiring 1 longitudinally go deep into deposit, its asperratio is more than 1.0, and is better more than 2.0, preferably more than 3.0, so can not cause chip area to increase and can reduce the impedance of element area 5.Since impedance is reduced, so can obtain following effect:

1. prevent self-locking

2. the function reduction that mutual interference causes for the interelement phase has improvement (reduce and disturb).

Below, the manufacture method of the semiconductor device of the component isolation structure with said structure is described.

1), for example, forms the opposite Doped n- type epitaxial loayer 2,3 of conduction type and substrate 4 with epitaxial growth method on the P type Si substrate 4 in a kind of Semiconductor substrate of conduction type.

2) then, on the surface of described epitaxial loayer 2,3, form the oxide-film of 0.5～1.0 micron thickness by thermal oxidation, afterwards, is that mask ion in element isolation zone 5 injects the impurity (for example P type) with epitaxial loayer 2,3 conductivity type opposite by means of forming technology with described oxide-film, and this diffusion layer reaches following Semiconductor substrate 4 always.

3) then, remove the oxide-film on epitaxial loayer 2,3 surfaces, form the oxide-film of thick 100～1000 dusts again.After this, in described element isolation zone 5, form the hole, as the mask Si of corrosion oxidation film and epitaxial loayer in two steps, form a raceway groove with photoresist by the photoresist figure.The degree of depth of ditch will arrive following Semiconductor substrate 4.Corrosion is removed photoresist after finishing.

4) last, resemble and use DMAH and hydrogen the above-mentioned Al-CVD method, epitaxial loayer 2,3 in, imbed Al in the ditch of setting.The material of imbedding in the ditch is not limited only to Al, all can as metal material with aforesaid Al-Si, Al-Ti etc.

Embodiment 2

Fig. 4 is the best drawing of expression embodiment 2 features.Among the figure, 1 is the big flush type element separation wiring of aspect ratio, and 2 is the 1st element area, and 3 is the 2nd element area, and 4 are doping Si substrate, and 5 are and substrate 4 doping type components identical isolated areas, and 6 are the back metal wiring.

If the current potential of element isolation zone 5 is fixing by element separation wiring 1 and back metal wiring 6, and then chip front side does not need wiring, thereby has reduced area of chip.

The following describes the manufacture method of semiconductor device with said elements isolation structure.

Technical process 1) with 2) step is the same with previous embodiment 1, so omit explanation.

3) then, form oxide-film at the back side of Semiconductor substrate 4, with the only back side perforate of the Semiconductor substrate 4 below described element isolation zone 5 of figure of photoresist formation by thermal oxidation.

After this, be mask with the photoresist from the back side corrosion oxidation film of Semiconductor substrate 4, then corrode Semiconductor substrate 4, offer raceway groove at the back side of Semiconductor substrate 4.The depth penetration Semiconductor substrate 4 of this ditch reaches the described diffusion layer of using as element separation 5 always.

4) next, press the Al-CVD method, equally with embodiment 1 only aluminium is deposited on channel part selectively, aluminium is imbedded in the ditch.Afterwards, the sputtering method by no preference pattern forms the aluminium film at the back side of Semiconductor substrate 4 comprehensively.

At last, make the aluminium at the back side form figure, formed the back metal wiring.

Embodiment 3

Below, the semiconductor function element of formation in element area 2 or 3 with Fig. 5 and Fig. 6 explanation.The feature of this function element is to use the Al-CVD method, for this bottom-gate (back gate) (the P type trap 10 of n-MOS and the n of P MOS with MOS transistor ^-Extension or n type trap 11) be fixed on arbitrarily that the big element wiring 12 of needed aspect ratio longitudinally is formed on P type trap 10 and n on the current potential ^-In extension or the n type trap 11.

Embodiment 4

Fig. 6 a is the sectional structure chart of another semiconductor function element, and Fig. 6 b is the circuit diagram of this element.The feature of this element is at the P of the reverse grid of MOS transistor type trap 10 and n ^-When extension or n type trap and source region (or drain region) are idiostatic,, in source region (or drain region) 13, form element separation wiring 12 with above-mentioned Al-CVD method for the resistance that makes reverse grid reduces.

In the MOS transistor of prior art, the resistance components of reverse grid becomes the reason of self-locking and function reduction etc., in addition, owing to increasing element area and wiring zone etc. in order to reduce this problem, has just caused the long-pending increase of element cross-section.

In contrast, shown in Fig. 5 and Fig. 6 a, because said elements makes element wiring 12 longitudinally go deep into deposit with the Al-CVD method, so with less wiring area, the resistance components of reverse grid is reduced, thereby can improve problems such as the self-locking that becomes problem in the past and function reduction.Particularly in logical circuit shown in Figure 6 (for example phase inverter), the zone when power supply and source (or leakage) equipotential can image pattern shows like that and connects up, because with less wiring area, so can improve the problems of the prior art.

Next, the manufacture method of element shown in Figure 5 is described with reference to Fig. 7 a～d.

At first, (Fig. 7 a) to forming contact hole state before device fabrication with known C-MOS manufacturing technology

Then with the n of the photoetching process of using photoresist at the P of n-MOS type trap part 10, P-MOS ^-Form on epitaxial loayer or the n type trap part 11 and should form 0.8 micron corresponding photoresist image of square perforate (Fig. 7 b).

Then, use CHF ₃-C ₂F ₅The dry corrosion of series forms the perforate 22 that makes interlayer insulating film 20 and field oxide film 21 break-through.Afterwards, under the situation of not removing photoresist, use CL ₂-CBrF ₃The dry etching of series goes about 1 micron (Fig. 7 C) to the silicon substrate corrosion vertically downward.

After this, press the Al-CVD method, as embodiment 1, aluminium 12 is embedded on the interlayer dielectric always.Total amount of imbedding adds up to 2.5 microns, and wherein the silicon substrate ditch depth is 1 micron, and field oxide film 21 is 8000 dusts, and interlayer insulating film 20 is 7000 dusts (Fig. 7 d).

At last, form contact hole, aluminium wiring etc., just finished sample with known technology.

The making of embodiment shown in Figure 6 can with make device shown in Figure 5 with same step.Difference just is that the perforate position is the source (or leakage) of MOS transistor, not break-through interlayer insulating film-field oxide film when forming perforate, break-through interlayer insulating film-grid oxidation film.

So above-mentioned element has according to component isolation structure of the present invention, can well isolate.

As mentioned above, owing to aluminium longitudinally is deposited in the element isolation zone, compare with the situation of need not this isolated area and obtaining effect same with the Al-CVD method, the area of chip minimizing, the Al wiring portion has also reduced, and the result has reduced manufacturing cost.

Embodiment 5

Fig. 8 is the best figure of expression present embodiment feature.The 4th, P type substrate, 5 ' be n ⁺Buried regions, 2 is n ^-Epitaxial loayer, 1 is the channel metal layer that is formed by the CVD method.One end of described channel metal layer 1 exposes at described n ^-On the surface of epitaxial loayer 2, the other end and described n+ buried regions join.

n ^-Epitaxial loayer 2 is photoelectric conversion region (element areas or claim active region), n+ buried regions 5 ' and channel metal layer 1 be element isolation zone.In addition, channel metal layer 1 also is a metal line.

n ^-Epitaxial loayer 2 remain on by n+ buried regions 5 ' and the positive potential of channel metal layer 1 on.

In said structure, the electronics that rayed generates mainly by n+ buried regions 5 ' with n ^-The internal electric field that the knot of epitaxial loayer 2 forms be attracted to n+ buried regions 5 '.The hole is enclosed in the pixel by internal electric field.

The hole that will spread to the pixel of adjacency has all been absorbed by channel metal layer 1, so can eliminate the interference between pixel.

Element isolation zone 1 is to form raceway groove with etch, and the metal that is main component aluminium or with aluminium with described selection CVD method is deposited to and forms in the ditch again, thereby can must can make the pixel densification to the reduced width of element isolation zone than the Xiao ， And of prior art.

In addition,, also can be used as the wiring lead, therefore element profile is dwindled because channel metal layer 1 is a low resistance.

Below, the manufacture method of the semiconductor device with said elements isolation structure is described.

1). in a kind of Semiconductor substrate of conduction type, for example form shallow and wide ditch on the part of P type Si substrate 4.By the epitaxial growth of using mask in this ditch, form be mixed with the n+ buried regions 5 of the impurity of substrate 4 conductivity type opposite '.

2). form n+ buried regions 5 ' substrate 4 on epitaxial growth form the n that will become photoelectric conversion region ^-Epitaxial loayer 2.

3). then, by thermal oxidation in said n ^-Form thick 0.5～1.0 micron oxide-film on the surface of epitaxial loayer 2, afterwards, described n+ buried regions 5 ' two ends by means of the photoresist figure in said n ^-Epitaxial loayer 2 open interiors form raceway groove with photoresist as mask etch.This moment raceway groove the degree of depth reach the n+ buried regions 5 of bottom '.Corrosion is removed photoresist after finishing.

4). next,, the substrate surface temperature is remained on 270 ℃, aluminium is imbedded be located at n with DMAH and hydrogen as selecting the CVD method ^-In the raceway groove in the epitaxial loayer 2.Here, the material of imbedding in the raceway groove is not limited only to aluminium, and is good as metal material with foregoing Al-Si, Al-Ti.

Embodiment 6

Fig. 9 is the example that the present invention is used to have the semiconductor device of dielectric substrate.The 1st, the channel metal layer, 4 ' be dielectric substrate, 2 is semiconductor layer.

Described semiconductor layer 2 is photoelectric conversion regions, and channel metal layer 1 is an element isolation zone, also is the wiring lead.Owing to channel metal layer 1 is arranged, just may obtain noiseless, highdensity semiconductor device.

The following describes the manufacture method of semiconductor device with said elements isolation structure.

1). the dielectric substrate 4 that constitutes by sapphire ' on form the semiconductor layer 2 that will become photoelectric conversion regions (element area) by epitaxial growth.

2). on the surface of described semiconductor layer 2, form thick 0.5～1.0 micron oxide-film by thermal oxidation, afterwards, at described semiconductor layer 2 open interiors, carry out burn into photoresist as mask and form raceway groove by means of the photoresist figure.At this moment, the degree of depth of raceway groove to reach the dielectric substrate 4 of bottom '.Corrosion is removed photoresist after finishing.

3). as selecting the CVD method, the substrate surface temperature is remained on 270 ℃, imbed aluminium in the raceway groove in semiconductor layer 2 with DMAH and hydrogen.Here the used material of imbedding is not limited to aluminium, and it is good that above-mentioned Al-Si, Al-Ti etc. make metal material.

As mentioned above, use the channel metal layer as element isolation zone, so can obtain the semiconductor device noiseless between pixel, that PEL (picture element) density is high, chip size dwindles.

Embodiment that other is fit to of the present invention is that the part that will connect the metal line of a plurality of elements is formed in the raceway groove that is arranged on the semiconductor substrate, rather than is formed on the dielectric film on the semiconductor substrate.

Embodiment 7

Figure 10 A is the circuit diagram of the partial logic circuit that is made of CMOS of expression, and Figure 10 B is the illustraton of model of its exterior contour of expression.

Power line VCC and ground wire GND are the settings of each units shared.These leads are for reducing impedance, avoid misoperation, avoiding the reliability decrease institute special requirement that cause because of migration.Therefore,, except that increasing function, also have the improvement of physical property, reduce vertical dislocation etc. as reducing occupied area if make these leads with buried wiring.

Equally, the buried wiring of the present invention clock line that is used for transmit clock signal also is effective.At this moment, as follows after the formation ditch becomes the raceway groove of wiring on the semiconductor substrate, the whole upward insulating barriers that cover of the inner surface of ditch.Then semi-conducting material or electric conducting material are deposited in this ditch, form the basis that metal is selected deposit.After this metal is imbedded in the ditch, formed the semiconductor device of present embodiment.

Figure 11 is the illustraton of model than further explanatory drawings 10B.The 63rd, the phase inverter same with the CMOS of Fig. 6.

Herein, each root all is the buried regions wiring that links to each other with source region and the well region of two MOSFET among lead VCC and the GND, becomes the shared lead in two adjacent unit 61,63.

A is the input of phase inverter, is polygate electrodes, and the phase inverter outside is its output, is the lead-in wire of drain electrode.This example unlike the prior art, power line VCC and ground wire GND all are wirings of the more following one deck of grid a.

In the semiconductor device of present embodiment, because metal wiring layer is arranged on matrix inside, although the area of plane of metal wiring layer is little, because its degree of depth increasing, so can guarantee the permission electric current of regulation.Because can be limited in the concavo-convex of device surface in the minimum zone,, the accuracy of the formation position of wiring layer is improved simultaneously so wiring layer does not move with respect to matrix.

Embodiment 8

Figure 12 and Figure 13 are the figure of the characteristic of wire structures in the expression semiconductor device of the present invention.Wherein, it is the wire structures that purpose constitutes that Figure 12 shows as power line to add positive voltage, and it is the wire structures that purpose constitutes that Figure 13 shows as power line to add negative voltage.These two kinds of wire structures except because of the relevant material category that forms each component part with applied voltage different, technological thought according to the present invention constitutes, and all is embodiments of the invention.Therefore, the former formation and manufacture method thereof has been described after, the latter's formation and manufacture method just are described with the former difference again.

Among Figure 12,710 is matrix, for example, is the P that is made of silicon etc. ^-The N-type semiconductor N substrate.Form ditch 711 by conventional method such as corrosion on the surface of this substrate 710, on except the inner surface on the surface of the bottom surface of ditch 711 and substrate 710 with thermal oxidation method or the CVD method insulating barrier 712 that constitutes by silicon dioxide etc. of formation continuously.Diffuse to form n from the bottom surface of above-mentioned ditch 711 to the internal heat of substrate 710 ⁺ Type diffusion layer 713, this diffusion layer are conduction type and the different doped semiconductor zones such as silicon that form substrate 710.

Inside at the ditch 711 that forms like this is provided with the metal wiring layer 714 that is made of metals such as aluminium.These metal wiring layer 714 usefulness bias sputtering method conventional methods such as (bias sputtering) form and get final product, and also can form with Al-CVD method described later.This Al-CVD method does not form metal films such as Al on the insulating barrier 712 that is formed by silicon dioxide, but metal film is formed on the substrate 710 that is made of silicon, promptly be can be selectively only metal films such as Al to be formed on the good film build method of reproducibility on the bottom surface of ditch 711.

The wiring membrane of Xing Chenging is continuously at least two function element like this, or is connected between the electrode terminal of regulation of the function element more than three forming circuit in case of necessity.For example, be suitable for as the source of two MOSFET, leak between and the line between the collector electrode of bipolar transistor, or as the connecting wiring between MOSFET and bipolar transistor etc. and the diffusion resistance, between MOSFET and bipolar transistor etc. and the capacity cell.

The following describes the example of manufacture method of the wire structures of formation like this.

At first, as shown in figure 12, prepare P ^- Type silicon substrate 710 is as semiconductor substrate.

Next form figure with photoresist on substrate 710 surfaces, afterwards, corrode and form the ditch 711 that the formation wiring layer is used.

Then, form thick 0.5～1.0 micron insulating barrier 712 with thermal oxidation method or CVD method on the surface of substrate 710 and the inner surface of ditch 711.

Then, except the bottom surface of ditch 711, on all surface of substrate 710, form figure, afterwards, use the RIE(rie with photoresist) etc. anisotropic etch remove the oxide layer that is formed on ditch 711 bottom surfaces, expose that part of silicon of substrate 710.

After this, form n+ type diffusion layer 713 on that part of silicon that exposes in ditch 711 bottoms with ion implantation or thermal diffusion method, this diffusion layer doping diffusion types is opposite with substrate 710.

Then, with conventional film build method such as sputter or Al-CVD method at n ⁺Form the metal wiring layer 714 that constitutes by Al etc. on the type diffusion layer 713.The upper surface that the insulating barrier 712 that forms is gone up on substrate 710 surfaces around the upper surface of this metal wiring layer 714 and the ditch 711 forms a plane, and this is to realize that the semiconductor device surface planarization is desirable.In such metal wiring layer 714 owing to form the n that forms as the insulating barrier 712 of dielectric film and in the bottom surface of ditch 711 as the P-N separator at the inner surface of ditch 711 ⁺So type diffusion layer 713 is and P ^-Therefore type silicon substrate 710 electric insulations, can not take place from the electric leakage of this metal wiring layer 714 to substrate 710.

If, as aforementioned, the Al film is deposited on the n that is made of silicon selectively with selecting the Al-CVD method ⁺On the type diffusion layer 713, and be not deposited on the insulating barrier 712 that constitutes by silicon dioxide.Therefore, use this Al-CVD method, have to resemble the advantage that to carry out forming steps such as figure when using conventional film build method such as sputter with photoresist.In addition, the depth ratio width of above-mentioned ditch 711 will be grown, although width is very little, also can form the aluminium film of high-quality from the bottom surface of ditch 711 effectively.Therefore, can be applicable to that aspect ratio is the fine structure more than 1.0, aspect ratio is also no problem more than 1.5, and is also applicable on 2.0.Because easily at the zanjon 711 inner aluminium films that form high-quality, even do not increase the width of metal wiring layer 714, by increasing the permission magnitude of current that its degree of depth also can easily strengthen metal wiring layer 714.

Below, Wiring structure shown in Figure 13 is described.In Figure 13, the part identical with Figure 12 structure used identical symbol, therefore omitted explanation.

Among Figure 13, the 720th, as matrix, for example, the n that constitutes by silicon ^-The N-type semiconductor N substrate.On the surface of substrate 720, form ditch 711, the insulating film layer 712 that the surface of the inner surface of ditch 711 (removing its bottom surface) and substrate 720 is made of silicon dioxide etc. with continuous formation such as thermal oxidation method or CVD method with conventional method such as corrosion.Form p from the bottom surface of ditch 711 to substrate 720 inner doping, thermal diffusion as semiconductor regions ⁺ Type diffusion layer 721, the conductivity type opposite of the semi-conducting material of its doping type and formation substrate.

The metal wiring layer 714 that metals such as aluminium constitute is set in this ditch 711 by for example.The metal wiring layer 714 that so forms is owing to have in the formation of ditch 711 inner surfaces as the insulating barrier 712 of dielectric film and the P that plays the effect of P-N separator that forms in ditch 711 bottom surfaces ⁺ Type diffusion layer 721, and and n ^- Type silicon substrate 720 electric insulations.Therefore, take place hardly from the electric leakage of metal wiring layer 714 to substrate 720.

The wire structures that the present invention so constitutes can be used in all function element, i.e. field-effect transistor, bipolar transistor, diffusion resistance etc.

Figure 14 is an example of wire structures of the present invention.It is the model profile of expression double layer of metal wire structures.

Among Figure 14,730 serve as reasons, for example, and the n that silicon constitutes ^-The N-type semiconductor N substrate.On the surface of substrate 730, form ditch 731 with conventional methods such as corrosion, except the bottom surface in the ditch 731, on the surface of all the other inner surfaces of ditch 731 and substrate 730, form the oxidation film layer 732 that constitutes by silicon dioxide etc. continuously with thermal oxidation or CVD method etc.Form the opposite P of semiconductor of conduction type and formation substrate 730 to substrate 730 inner doping, thermal diffusion from the bottom surface of described ditch 731 ⁺Type thermal diffusion layer 733.

Form with the inside of selecting the Al-CVD method at ditch 731, for example, the 1st metal wiring layer 734 that forms by Al etc.Its upper surface becomes a plane with the surface of substrate 730.

In addition, form the perforate 735 that the semiconductor element extraction electrode is used on the part of above-mentioned oxidation film layer 732, this perforate one is through to the surface of substrate 730.

Form the 2nd metal wiring layer 736 that constitutes by metals such as Al in the ditch 731 on the inside of this perforate 735, the 1st metal wiring layer 734 tops and on the surface of oxidation film layer 732.On the 2nd metal wiring layer 736 and oxidation film layer 732, form, for example, the passivating film 737 that constitutes by silicon nitride etc.

Below, have the manufacture method of the semiconductor device of wire structures shown in Figure 14 with reference to figure 15A～15C explanation.

At first, shown in Figure 15 A, prepare n ^- Type silicon substrate 730 is as Semiconductor substrate.

Next, using photoresist after forming figure on the surface of substrate 730,, be formed for forming the ditch 731 that first metal wiring layer is used by corroding.

Then, on the inner surface of the surface of substrate 730 and ditch 731, form thick 0.5～1.0 micron oxidation film layer 732 with thermal oxidation method.

Then, on all surfaces of substrate 730 except ditch 731 bottom surfaces, apply photoresist, use the RIE(rie again) anisotropic etch remove the oxidation film layer that forms on ditch 731 bottom surfaces, expose substrate 730 that part of silicon.

After this, on that part of silicon that exposes at ditch 731 bottom surfaces places with ion implantation is mixed, diffusion conduction type and substrate 730 are opposite B(boron) and formation P ⁺ Type diffusion layer 733.

By selecting the Al-CVD method at P ⁺Form first metal wiring layer 734 that constitutes by aluminium etc. on the type diffusion layer 733.Substrate 730 upper surface flush around the upper surface of this first metal wiring layer 734 and the ditch 731.This first metal wiring layer 734 by be formed on ditch 731 inner surfaces as the oxidation film layer 732 of dielectric film and be formed on ditch 731 bottoms, play the P of p-n junction effect ⁺ Type diffusion layer 733 is with n ^-Type Si substrate electric insulation.Therefore, can be sure of almost not have electric current to leak to substrate 730 from first metal wiring layer 734.

After this, on the surface of oxidation film layer 732, form figure, on the part of oxidation film layer 732, form the perforate 735(Figure 15 B that semi-conducting electrode is used that draws that leads to substrate 730 surfaces with etch again) with photoresist.

Then, press the Al-CVD method, with DMAH and hydrogen the matrix surface temperature is remained on 270 ℃, deposit forms second metal wiring layer that is made of Al in the ditch 731 on the inside of perforate 735 and first metal wiring layer, 734 tops.The upper surface of the 736a of lower floor of this second metal wiring layer becomes a plane with the upper surface of oxidation film layer 732.Then, at each upper surface and the oxidation film layer 732 lip-deep assigned positions of second 736a of metal wiring layer lower floor, form the second metal wiring layer upper strata 736b(Figure 15 C that constitutes by aluminium with sputtering method).

On second metal wiring layer 736 and oxidation film layer 732, form thick 0.5～1.0 micron passivating film 737 that constitutes by silicon nitride with plasma CVD method again, just obtained to possess the semiconductor device of double layer of metal wire structures shown in Figure 14.

In the semiconductor device that so constitutes, because the P that has located the effect of Pn separator as the bottom surface of the oxidation film layer 732 of ditch 731 inner surface dielectric films and ditch 731 is arranged ⁺ Type diffusion layer 733 is located at n ^-First metal wiring layer 734 and the n in the type substrate 730 ^- Type silicon substrate 730 electric insulations produce leakage current to substrate 730 hardly from first metal wiring layer 730.On first metal wiring layer 734,, but also can guarantee the needed permission magnitude of current by strengthening the degree of depth even do not increase the area of plane.In addition, because can be the concavo-convex limit on the semiconductor device surface built in minimum, so first metal wiring layer 734 does not relatively move for substrate 730, the position that can improve first metal wiring layer 734 forms precision, can also increase the lamination number of multilayer wiring simultaneously in the component thickness scope that is limited.Because between first metal wiring layer and second metal wiring layer, do not need interlayer dielectric, when later each wiring layer of the 3rd metal wiring layer is set, can reduce the vertical dislocation on surface, thereby can improve the reliability of the 3rd layer of later wiring layer.

As mentioned above, according to the present invention, even the area of plane of wiring is very little, also can guarantee the necessary permission magnitude of current, and can obtain the Wiring structure of high position accuracy.

Be applicable to that film build method of the present invention is to use the gas and the hydrogen of the hydride (alkyl aluminium hydride) of alkyl aluminum, forms deposited film (promptly being called the Al-CVD method) by surface reaction on alms giver's (donates electrons) mold base.

With the hydride (dimethyl aluminium hydride) of the hydride (monomethyl aluminium hydride) of monomethyl aluminium or dimethyl aluminium as raw material, with hydrogen as reacting gas, with such mist heating matrix surface, can obtain the deposit aluminium film of high-quality.When deposit aluminium, by direct heating or indirect the surface temperature of matrix remained on more than the decomposition temperature of hydride of alkyl aluminum, be gratifying below 450 ℃, remain on more than 260 ℃, even more ideal below 440 ℃.

Make matrix snead process and indirect method be arranged as far as possible, but, matrix is remained on said temperature, can form the aluminium film of high-quality with high deposition speed with snead process in the method for said temperature scope heating.For example, when remaining in comparatively ideal 260 ℃～440 ℃ temperature range when forming the aluminium film, can obtain the film of high-quality by the 300 dusts～5000 dusts/minute taller deposition speed with than resistance heating the time to the matrix surface temperature.As this direct heating means (energy being directly passed to matrix and matrix self heating), for example, can enumerate heating with lamps such as Halogen lamp LED, xenon lamps by heater.In addition, resistance heating is arranged, can heat with being arranged on to supporting the heater that the matrix will form deposited film is configured on the matrix holding components that forms in the space that deposited film uses as the indirect method.

In this way, if the CVD method is used on the matrix of alms giver's property surface and the coexistence of non-alms giver (not donates electrons) property surface, just can be on that part of alms giver's property matrix surface selectivity form the monocrystalline of Al well.This Al monocrystalline is as all superior material of needed all characteristics of electrode/wiring material.That is, can reach the incidence of reduction hillock and the incidence at alloy tip.

Can think that its reason is, can form the aluminium of high-quality on by the surface that constitutes as the semiconductor on alms giver's property surface and conductor etc. selectively, and the crystal property of aluminium is superior, so almost can't see or little based on the alloy spike that forms with eutectic reaction as the silicon etc. on basis.And, adopt such aluminium to make the electrode of semiconductor device, surpassed the notion of thinkable in the past aluminium electrode, can obtain beyond thought effect in the prior art.

Illustrated above that on alms giver's property surface the aluminium that for example is formed on deposit in the perforate of exposing the semiconductor-based surface on the dielectric film becomes the situation of mono-crystalline structures.If but use the Al-CVD method, also following those of deposit are the metal film of main component with Al selectively, and the quality of this film also shows superior characteristic.

For example, the gas of the hydride of alkyl aluminum and hydrogen are added following gas and are suitably mixed environmental gas as mist, and electric conducting materials such as deposit Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, Al-Si-Cu also can form electrode selectively.Above-mentioned added gas is:

SiH ₄, Si ₂H ₆, Si ₃H ₈, Si(CH ₃) ₄, SiCl ₄, SiH ₂Cl ₂, SiHCl ₃Etc. the gas of silicon atoms,

TiCl ₄, TiBr ₄, Ti(CH ₃) ₄Deng the gas that contains titanium atom,

Cu(C ₅H ₇O ₂), Cu(C ₁₁H ₁₉O ₂) ₂, Cu(C ₅HF ₆O ₂) ₂Deng the gas that contains copper atom.

In addition, because above-mentioned Al-CVD method is that selectively superior film build method can make the surface property of deposited film good again, so use non-selective film build method in the later depositing technics, by the aluminium film that obtains in above-mentioned selection deposit and as the SiO of dielectric film ₂Deng on also form Al or be the metal film of main component with Al, just can obtain the high metal film of using as semiconductor device wire of versatility.

This metal film specifically is exemplified below: the combination of Al, the Al-Si of Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, Al-Si-Cu and the non-selective deposit of selection deposit, Al-Ti, Al-Cu, Al-Si-Ti, Al-Si-Cu.

The film build method that non-selective deposit is used has CVD method beyond the above-mentioned Al-CVD method and sputtering method etc.

Below, the film formation device that is suitable for forming electrode of the present invention is described.

Figure 16-Figure 18 illustrates the typical metal film that is suitable for above-mentioned film build method and forms device continuously.

This metal film forms device continuously, as shown in figure 16, by charging gate (load lock) chamber 311, as first film forming room CVD reative cell 312, Rf corroding chamber 313, constitute as the sputtering chamber 314 and the charging lock air chamber 315 of second film forming room, these chambers can be connected when mutually being cut off with outside atmosphere by sluice valve 310a～310f with interconnecting, the decompression of can bleeding by gas extraction system 316a～316e separately of each chamber.Here, described charging lock air chamber 311 is in order to improve throughput, change to the used chamber of hydrogen atmosphere after the substrate atmosphere before the deposit to be discharged.CVD reative cell 312 is to carry out selectively deposited chamber with above-mentioned Al-CVD method under normal pressure or decompression situation on substrate, its structure is the inner substrate holder 318 with the heat generating components 317 that can heat matrix surface to be filmed at least in 200 ℃～450 ℃ scopes that is provided with, with unstrpped gas conduit 319 unstrpped gas is imported indoor (these unstrpped gases have the hydride of the alkyl aluminum that is gasified by hydrogen process bubbling bottle 319-1 bubbling etc.), gas conduit 319 ' import indoor to reacting gas hydrogen by CVD simultaneously.Below Rf corroding chamber 313 are the chambers that in Ar atmosphere, form figure (corrosion) on the matrix surface after selectively deposited, be provided with in it and can be heated to substrate holder 320 and the Rf corrosion electrode 321 that heats in 100 ℃ of-250 ℃ of scopes to matrix, also be connected with Ar gas supplying duct 322 simultaneously.The sputtering chamber 314 of back be in argon atmospher with sputtering method in the matrix surface chamber of depositing metal film non-selectively, be provided with the substrate holder 323 that in 200 ℃～250 ℃ scopes, heats at least in it and the target electrode 324 that sputtering target material 324a uses is installed, also be connected with argon gas feed conduit 325 simultaneously.Last charging gate chamber 315 is the adjustment chambers before the matrix after metal film deposition is finished is got in the extraneous air, and its formation is to replace reaction atmosphere gas with nitrogen.

Figure 17 represents that the metal film of suitable above-mentioned film build method forms the another formation example of device continuously.The part identical with Figure 16 all used identical symbol.The device of Figure 17 and Figure 16 device different are to be provided with as the direct Halogen lamp LEDs 330 of heater, can directly heat matrix surface, therefore, are provided with clamp 331, are used for matrix is remained on the state that is suspended on the substrate holder 312.

The actual form that the metal film of said structure forms device continuously as shown in figure 18.To transport chamber 326 as in the second wife, this and foregoing charging lock air chamber 311, CVD reative cell 312, Rf corroding chamber 313, sputtering chamber 314, charging lock air chamber 315 interconnective structures equivalence in fact.By such structure, charging lock air chamber 311 double as charging lock air chambers 315 usefulness.Described transporting in the chamber 326, as shown in the figure, be provided with as rotating in clockwise, counter clockwise direction, and the arm 327 of the feeding device that can on the BB direction, stretch, such shown in arrow among Figure 19, by moving this arm 327, can make matrix move to CVD chamber 312, Rf corroding chamber 313, sputtering chamber 314, charging lock air chamber 315 continuously from charging lock air chamber 311, and not be exposed in the atmosphere along the sequence of steps ground of technical process.

Directly heat matrix surface with such structure, can more improve a step to deposition speed as described above thus.

The following describes the film forming step of formation according to electrode of the present invention and wiring.

Figure 20 is the signal oblique view of explanation formation according to the film forming step of electrode of the present invention and wiring.

At first do the explanation of summary.Preparation has formed the semiconductor substrate of perforate on dielectric film, matrix is put into film forming room, its surface is remained on 260 ℃～450 ℃, according to hot CVD method with the mist of the DMAH gas of the hydride of alkyl aluminum and hydrogen, deposit Al selectively on that part of semiconductor that in perforate, exposes.Certainly, as aforementioned, import contain the Si atom gas selectively deposit Al-Si etc. be that the metal film of main component is good with Al.Then with sputtering method at the Al of deposit selectively and on dielectric film, be non-selectively formed Al or be the metal film of main component with Al.Thereafter, the composition needed wiring shape that is shaped just can form electrode and wiring on the metal film that non-selectively deposit forms.

Below, make specific description with reference to Figure 17 and Figure 20.At first prepare matrix.As matrix, prepare exactly, for example, form the insulating barrier of the perforate that is provided with various apertures on the silicon single crystal wafer.

Figure 20 A is the schematic diagram of this matrix part of expression.Wherein, 401 is the single crystal silicon substrate as conductive base, the 402nd, and as the thermal oxidation silicon film of dielectric film.403 and 404 is perforate (exposed portions serve), and its aperture has nothing in common with each other.410 expose the substrate portion of Si.

On matrix, form Al film forming procedure, if be following situation according to Figure 17 as the electrode of first wiring layer.

At first, above-mentioned matrix is put into charging gate chamber 311, as described above hydrogen is imported in the chamber 311 as hydrogen atmosphere.After this, with gas extraction system 316b reative cell 312 is vacuumized and reach about 1 * 10 ^-8Torr.Even the vacuum degree in the reative cell 312 is than 1 * 10 ^-8Torr is a little bit poorer, and Al also can film forming.

Therefore, the DMAH gas of supplying with through bubbling from gas conduit 319.The gas that carries in the DMAH conduit is hydrogen.

The 2nd gas conduit 319 ' confession reacting gas hydrogen is used, and hydrogen is the 2nd gas conduit 319 ' flow through from then on, adjusts the switch degree of not shown slow leak valve, the pressure in the reative cell 312 is adjusted to the value of regulation.At this moment typical pressure is about 1.5 torrs and gets final product.Through the DMAH conduit DMAH is imported in the reaction tube.Total pressure is about 1.5 torrs, and the dividing potential drop of DMAH is about 5.0 * 10 ^-3To the Halogen lamp LED energising, directly add wafer afterwards.Deposit aluminium so selectively.

Stop to supply with DMAH after the deposition time through regulation.The predetermined deposition time of the Al film that deposit obtains in this process is to make Si(monocrystalline substrate 401) on the Al film thickness reach and SiO ₂The time that the film thickness of (heat oxide film 402) equates, this can obtain in advance according to experiment.

By at this moment direct heating the matrix surface temperature is controlled at 270 ℃.By step so far, shown in Figure 20 B, in perforate and in the ditch selectively deposit Al film 405.

More than be called the first film-forming process step that in contact hole, forms electrode.

After the above-mentioned steps, the CVD reative cell is evacuated down to 5 * 10 by gas extraction system 316b ^-3The vacuum degree that torr is following.Simultaneously, Rf corroding chamber 313 is evacuated down to 5 * 10 ^-6Below the torr.After confirming that above-mentioned two Room have reached above-mentioned vacuum degree, the valve 310C that opens the sluices is transplanted on the Rf corroding chamber to matrix from the CVD reative cell with feeding device, closed shutter valve 310C.Matrix is conveyed into Rf corroding chamber 313, by gas extraction system 316C Rf corroding chamber 313 is vacuumized and reach 10 ^-6Torr or lower vacuum degree.After this, supply with argon with the conduit 322 of argon, the argon atmospher of Rf corroding chamber is remained on 10 by supplying with the Rf corrosion ^-1～10 ^-3Torr.The Rf corrosion is remained on 200 ℃ with substrate holder 320, to the Rf electrical power of Rf corrosion, make and produce the argon discharge in the Rf corroding chamber 313 in the time about 60 seconds with electrode 321 supply 100W.So, by argon ion etched the matrix surface, can remove the superficial layer that does not need the CVD illuvium.At this moment corrosion depth and oxide quite are about 100 dusts.Here, the surface corrosion of CVD deposited film is carried out in the Rf corroding chamber, because the cvd film superficial layer on the matrix that transports does not in a vacuum contain the oxygen in the atmosphere, therefore, even it is good not carry out the Rf corrosion.At this moment, Rf corroding chamber 313 plays the effect of the temperature change chamber of carrying out variations in temperature at short notice when the temperature difference of CVD reative cell 312 and sputtering chamber 314 is big.

In Rf corroding chamber 313, Rf corrosion stops to import argon after finishing, and extracts argon gas in the Rf corroding chamber 313 out, Rf corroding chamber 313 is evacuated to 5 * 10 ^-6Tuo ， And and sputtering chamber 314 is being evacuated down to 5 * 10 ^-6After torr was following, valve 310d opened the sluices.After this, matrix is moved to sputtering chamber 314 from Rf corroding chamber 313, closed shutter valve 310d with feeding device.

Matrix is transported to after the sputtering chamber 314, make sputtering chamber 314 become with Rf corroding chamber 313 same 10 ^-1～10 ^-3The argon gas atmosphere of torr is set in 200～250 ℃ with the temperature of the substrate holder 323 of bearing substrate.Carrying out argon discharge then under the dc electric power of 5～10KW, is 5% with argon ion bombardment Al-Si(Si) etc. target, with 10000 dusts/minute deposition speed metal such as deposit Al or Al-Si on matrix, be carried out to membrane process.This step is non-selective deposition process steps.Be referred to as to form the 2nd film-forming process step of the wiring that is connected with electrode.

After having formed the thick metal film of 5000 dusts on the matrix, stop to supply with argon gas and apply dc electric power.The gate chamber 311 of will feeding is evacuated down to 5 * 10 ^-3Below the torr, the valve 310e that opens the sluices moves matrix.Behind the closed shutter valve 310e, infeed oxygen and reach an atmospheric pressure in charging gate chamber 311, the valve 310f that opens the sluices again takes out matrix.

According to the 2nd above aluminium film deposition step, can be as Figure 20 SiO that c is shown in ₂ Form aluminium film 406 on the film 402.

And, as Figure 20 D on this aluminium film 406 photoetching formation, just can obtain the wiring of required form.

Embodiment

Below, according to experimental result, the chromatic effect that goes out of above-mentioned Al-CVD method is described, and thus method to be deposited on aluminium in the perforate be the film of high-quality how.

At first, at SiO as n type silicon single crystal wafer surface heat oxidation formation 8000 dusts of matrix ₂,, expose following Si monocrystalline with the perforate that photoetching formation is prepared out a plurality of 0.25 micron * 0.25 micron～100 microns * 100 microns square various sizes.(sample 1-1)

The Al-CVD method following according to condition forms the Al film in these perforates.Be unstrpped gas with DMAH, hydrogen is reacting gas, and total pressure is 1.5 torrs, and the DMAH partial pressure is 5.0 * 10 ^-3Under the common conditions of torr, adjust electrical power, directly heat, the matrix surface temperature is set in 200～490 ℃ the scope, carry out film forming by Halogen lamp LED.

It the results are shown in table 1.

As can be seen from Table 1, directly heat the matrix surface temperature more than 260 ℃ the time, Al divides so high deposition speed to be deposited in the perforate selectively with 3000～5000 dusts.

Have a look at matrix surface temperature Al membrane property in the perforate in 260 ℃～440 ℃ scope the time, can be clear that the characteristic of aluminium film is good.Carbon content rate is zero, and resistivity is 2.8～3.4 micro-ohms centimetre, and reflectivity is that the hillock density more than 90～95%, 1 micron is 0～10/square centimeter, does not almost have spike (failure probability of 0.15 micron knot) to occur.

Relative therewith, when the matrix surface temperature was in 200 ℃～250 ℃ scopes, membranous viewpoint from prior art was pretty good, but had compared then poor a lot with 260 ℃～440 ℃ situation.And deposition speed can only reach 1000～1500 dusts/minute, not talkatively reached very high.

In addition, if matrix surface is to more than 450 ℃, and then the hillock density that drops to more than 60%, 1 micron of reflectivity reaches every square centimeter 10～10 ⁴, the alloy spike reach 0～30%, the Al membrane property in the perforate has reduced.

Below, be illustrated as any said method and can be applicable to the perforate that is called contact hole or through hole.

Contact hole/the through-hole structure that is made of following material can obtain gratifying use.

In above-mentioned sample 1-1 with under the condition identical when forming the Al film, go up at the matrix (sample) that forms by following step and to form the aluminium film.

As the oxide-film of using the formation of CVD method as the 2nd matrix surface material on the monocrystalline silicon of the first matrix surface material, carry out figure by photoetching process and be shaped the exposed portions serve monocrystalline silicon surface.

At this moment thermal oxidation SiO ₂The thickness of film is 8000 dusts, exposes the part of monocrystalline silicon, and promptly the size of opening is 0.25 micron * 0.25 micron～100 microns * 100 microns.Be ready to sample 1-2 like this.(following usefulness " CVDDSiO ₂" or abbreviation " SiO ₂"/monocrystalline silicon " represent the sample that so forms).

Sample 1-3 is boron-doping oxide-film (following abbreviation the BSG)/monocrystalline silicon with atmospheric pressure cvd method film forming,

Sample 1-4 be with atmospheric pressure cvd method film forming mix phosphorus oxidation film (following abbreviation PSG)/monocrystalline silicon,

Sample 1-5 is with the oxide-film of mixing phosphorus and boron of atmospheric pressure cvd method film forming (following abbreviation BSPG)/monocrystalline silicon,

Sample 1-6 is with the nitride film of plasma CVD method film forming (to call P-SiN in the following text)/monocrystalline silicon,

Sample 1-7 is hot nitride film (following abbreviation T-SiN)/monocrystalline silicon,

Sample 1-8 is nitride film (following abbreviation the LP-SiN)/monocrystalline silicon with decompression CVD method film forming,

Sample 1-9 is by the nitride film of ECR device film forming (following abbreviation ECR-SiN)/monocrystalline silicon,

Using the full combination of first matrix surface material (18 kinds) shown in following and the second matrix surface material (9 kinds) to make sample 1-11～1-179(again notes: lack following sample number 1-10,20,30,40,50,60,70,80,90,100,110,120,130,140,150,160,170).Use single crystalline Si, polycrystalline Si, amorphous Si, W, Mo, Ta, WSi, TiSi, Al, Al-Si, Al-Ti, Ti-N, Cu, Al-Si-Cu, Al-Pd, Ti, Mo-Si, Ta-Si as the first matrix surface material.As the second matrix surface material is T-SiO ₂, SiO ₂, BSG, PSG, BPSG, P-SiN, T-SiN, LP-SiN, ECR-SiN.All can form the high-quality Al film suitable for above all samples with sample 1-1.

In above deposit selectively on the matrix of Al with the non-selectively deposit of above-mentioned sputtering method aluminium, make figure again.

As a result, because the surface property of the Al film in the perforate is good, so the aluminium film of selecting deposit to form in aluminium film that sputter forms and the perforate reaches contact condition electric, that mechanical performance is all excellent and the life-span is high.

Manufactured experimently the sample of semiconductor device with embodiment 1～8 illustrated method, experimental result has obtained the superperformance of expection.

Claims (4)

1, a kind of semiconductor device has: many element areas that form on semiconductor substrate, the semiconductor substrate and make the described element area electricity isolated area of isolating mutually; It is characterized in that: above-mentioned isolated area comprises that side surface that forms element from matrix that is formed by aluminum single crystal begins the conduction region of filling groove, and described conductive region at least with the said elements zone in 2 function element electrically contact.

2, semiconductor device according to claim 1 is characterized in that: described semiconductor substrate has a dielectric substrate.

3, semiconductor device according to claim 1 is characterized in that: described semiconductor device contains logical circuit.

4, semiconductor device according to claim 1 is characterized in that: described conductive region adjacent semiconductor is material doped and be provided with.

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