CN102185807B - Equalizer and equalization signal method - Google Patents
Equalizer and equalization signal method Download PDFInfo
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- CN102185807B CN102185807B CN201110092519.3A CN201110092519A CN102185807B CN 102185807 B CN102185807 B CN 102185807B CN 201110092519 A CN201110092519 A CN 201110092519A CN 102185807 B CN102185807 B CN 102185807B
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Abstract
The invention discloses an equalizer and an equalization signal method. The equalizer comprises a super-sampling logical unit, a DC setting unit and an AC setting unit. The super-sampling action of the data from a channel is executed according to a super-sampling clock pulse by the super-sampling logical unit and a plurality of DC items and a plurality of AC items are generated. A plurality of DC items and a plurality of AC items are outputted related to an output clock pulse according to the output clock pulse. A plurality of DC items are inputted according to a first setting time by the DC setting unit and the DC setting of the equalizer is adjusted. A plurality of AC items are inputted according to a first setting time by the AC setting unit and the AC setting of the equalizer is adjusted.
Description
Technical field
The present invention relates to a kind of method of equalizer and equalizing signal, espespecially a kind of DC terms producing according to oversampling logical block and exchanges, to adjust the direct current setting of equalizer and to exchange the equalizer of setting and the method for equalizing signal.
Background technology
Please refer to Fig. 1, Fig. 1 is the schematic diagram of DESCRIPTION OF THE PRIOR ART equalizer 100.Equalizer 100 comprises a direct current estimation unit 102, a direct current logic processor 104, interchange estimation unit 106 and an alternating current logic processor 108.When equalizer 100 is from a channel receives data, by the data that receive from channel in average one first scheduled time T1 of direct current estimation unit 102, to produce a DC parameter, and exchange estimation unit 106 to carrying out a discrete cosine transform (discrete cosine transform from the data of channel reception in the first scheduled time T1, and discrete sine conversion (discrete sine transform DCT), DST), to produce an alternating-current parameter.DCL processor 104 is coupled to direct current estimation unit 102, and according to the multiple DC parameters in one second scheduled time T2, judges whether to adjust the direct current setting of equalizer 100.Alternating current logic processor 108 is coupled to and exchanges estimation unit 106, and according to the multiple alternating-current parameters in the second scheduled time T2, judges whether to adjust the interchange setting of equalizer 100.
In the prior art, the operation principle of equalizer 100 is pinned based on clock pulse data return signal phase place, but actual conditions are in the time that clock pulse data return signal phase place is not yet pinned, and received the data from channel.In addition, direct current estimation unit 102 and the frequency that exchanges estimation unit 106 and must be operated at received data, the frequency of for example received data is 10GHz, direct current estimation unit 102 with exchange estimation unit 106 and also must be operated at 10GHz.In addition,, if the data that just receive within a period of time are all interchange values, direct current estimation unit 102 can think that D. C. value is inadequate in received data, sets to such an extent as to tendency increases the direct current of equalizer 100.But actual conditions may be that to only have the data that time receives be all interchange value, and other periods are really not so, cause the direct current of equalizer 100 to set mistake.
Summary of the invention
One embodiment of the invention provide a kind of equalizer.This equalizer comprises an oversampling logical block, a direct current setup unit and exchanges setup unit.This oversampling logical block is in order to according to an oversampling (oversampling) clock pulse, to carry out an oversampling action from the data of a channel, to produce multiple DC terms (DC term) and multiple interchange (AC term), and according to an output clock pulse, from the plurality of DC terms output and multiple DC terms of this output clock pulse correlation and from the plurality of exchanges multiple items that exchange of output and this output clock pulse correlation; This direct current setup unit, in order to according to multiple DC terms of being inputted by this oversampling logical block in one first scheduled time, adjusts a direct current of this equalizer and sets; And this interchange setup unit, in order to according to multiple interchanges of being inputted by this oversampling logical block in this first scheduled time, adjust one of this equalizer and exchange setting.
Another embodiment of the present invention provides a kind of method of equalizing signal.The method comprises according to an oversampling clock pulse, to carry out an oversampling action from the data of a channel, to produce multiple DC terms and multiple interchange item; According to an output clock pulse, from the plurality of DC terms output and multiple DC terms to direct current setup units of this output clock pulse correlation and from the plurality of exchanges the multiple Xiang Zhiyi of interchange interchange setup units of output and this output clock pulse correlation; Be pursuant to multiple DC terms of output in one first scheduled time, adjust the direct current of an equalizer and set; And be pursuant to multiple interchanges of exporting in this first scheduled time, adjust the interchange of this equalizer and set.
The method of a kind of equalizer provided by the present invention and equalizing signal, moves to carry out an oversampling from the data of a channel according to an oversampling logical block, to produce multiple DC terms and multiple interchange item.And this oversampling logical block can be according to an output clock pulse, multiple Xiang Zhiyi that exchange of multiple DC terms to direct current setup units of output and this output clock pulse correlation and output and this output clock pulse correlation exchange setup unit.Therefore, equalizer of the present invention needn't operate situation about being lockable in clock pulse data return signal phase place, and this direct current estimation unit exchanges estimation unit and do not need to operate in a high-frequency clock pulse with this.In addition, this oversampling logical block is to carry out this oversampling action from the data of this channel, to produce multiple DC terms and multiple interchange item.Therefore, be all the situation that exchanges item or DC terms for the data that receive within certain a period of time, the present invention maintains the last time direct current of equalizer and sets or exchange setting, so as to improving the wrong situation that direct current is set or interchange is set of equalizer.
Brief description of the drawings
Fig. 1 is the schematic diagram of DESCRIPTION OF THE PRIOR ART equalizer;
Fig. 2 is the schematic diagram of one embodiment of the invention explanation equalizer;
Fig. 3 A is explanation oversampling the logical block DC terms of exporting and the schematic diagram that exchanges item with Fig. 3 B;
Fig. 4 is for explanation oversampling logical block is according to output clock pulse, the DC terms of output and output clock pulse correlation and exchange the schematic diagram of item;
Fig. 5 is the flow chart of the method for another embodiment of the present invention explanation equalizing signal.
Wherein, Reference numeral
100,200 equalizer 102,2042 direct current estimation units
104,2044 DCL processors 106,2062 exchange estimation unit
108,2064 alternating current logic processor 202 oversampling logical blocks
204 direct current setup units 206 exchange setup unit
500-512 step
Embodiment
Please refer to Fig. 2, Fig. 2 is the schematic diagram of one embodiment of the invention explanation equalizer 200.Equalizer 200 comprises an oversampling logical block 202, a direct current setup unit 204 and exchanges setup unit 206.Oversampling logical block 202 is in order to according to an oversampling (over sampling) clock pulse Cov, to carry out an oversampling action from the data of a channel, to produce multiple DC terms (DC term) and multiple interchange (AC term), and according to an output clock pulse Co, multiple DC terms that output and output clock pulse Co are relevant from multiple DC terms and multiple items that exchange that output is correlated with output clock pulse Co from multiple exchanges.In addition, the frequency of oversampling clock pulse Cov must be greater than two times of frequency of data.In the present embodiment, oversampling clock pulse Cov is 10GHz, and the frequency of data is 2.5GHz, is 10GHz but the present invention is not limited to oversampling clock pulse Cov, and the frequency of data is 2.5GHz.
Please refer to Fig. 3 A and Fig. 3 B, Fig. 3 A is explanation oversampling logical block 202 DC terms of exporting and the schematic diagrames that exchange item with Fig. 3 B.Because the frequency that oversampling clock pulse Cov is 10GHz and data is 2.5GHz, so the DC terms that oversampling logical block 202 is exported must be 4 bit term (10GHz/2.5GHz=4) with exchanging item.When 4 bit term are not " 0 " or entirely when " 1 " entirely, to record this 4 bit term be an interchange item to oversampling logical block 202.As shown in Figure 3A, 4 bit term are " 0111 ", and to record 4 bit term " 0111 " be an interchange item to oversampling logical block 202.In like manner, when 4 bit term are " 0 " or complete during for " 1 " entirely, to record this 4 bit term be a DC terms to oversampling logical block 202.As shown in Figure 3 B, 4 bit term are " 1111 ", and to record 4 bit term " 1111 " be a DC terms to oversampling logical block 202.
Please refer to Fig. 4, Fig. 4 is for explanation oversampling logical block 202 is according to output clock pulse Co, the DC terms of output and output clock pulse correlation and exchange the schematic diagram of item.Oversampling logical block 202 is constantly utilized oversampling (over sampling) clock pulse Cov, to carry out an oversampling action from the data of a channel, to produce multiple DC terms and multiple interchange item.But oversampling logical block 202 is only in the time of output clock pulse Co rising edge, and output is 4 bit term of record (being likely DC terms, is likely also to exchange item) recently.But the present invention is not limited to output clock pulse Co rising edge, oversampling logical block 202 also can be in the time of output clock pulse Co trailing edge, and output is 4 bit term of record recently.Therefore, oversampling logical block 202 can be according to output clock pulse Co, and the relevant multiple DC terms of output and output clock pulse Co are to direct current setup unit 204 and output multiple items that exchange relevant with output clock pulse Co to exchanging setup unit 206.
Direct current setup unit 204 comprises a direct current estimation unit 2042 and a direct current logic processor 2044.Direct current estimation unit 2042 is coupled to oversampling logical block 202, in order to multiple DC terms of being inputted by oversampling logical block 202 in average the first scheduled time T1, to produce a DC parameter DCP; DCL processor 2044 is coupled to direct current estimation unit 2042, in order to according to the multiple DC parameter DCP in the second scheduled time T2, judges that whether the D. C. value of equalizer 200 is enough, adjusts according to this direct current of equalizer 200 and sets DCS.Exchange setup unit 206 and comprise an interchange estimation unit 2062 and an alternating current logic processor 2064.Exchange estimation unit 2062 and be coupled to oversampling logical block 202, in order to the multiple interchanges of being inputted by oversampling logical block 202 in the first scheduled time T1, carry out a discrete cosine transform (discrete cosine transform, and discrete sine conversion (discrete sine transform DCT), DST), to produce an alternating-current parameter ACP; Alternating current logic processor 2064 is coupled to and exchanges estimation unit 2062, in order to according to the multiple alternating-current parameter ACP in the second scheduled time T2, judges that whether the interchange value of equalizer 200 is enough, adjusts according to this interchange of equalizer 200 and sets ACS.
Please refer to Fig. 5, Fig. 5 is the flow chart of the method for another embodiment of the present invention explanation equalizing signal.The method of Fig. 5 utilizes the equalizer 200 of Fig. 2 to illustrate, detailed step is as follows:
Step 500: start;
Step 502: according to oversampling clock pulse Cov, the data from a channel are carried out to oversampling action, to produce multiple DC terms and multiple interchange item;
Step 504: according to output clock pulse Co, multiple DC terms that output is relevant with output clock pulse Co from multiple DC terms are to direct current setup unit 204, carry out step 506, and export multiple the exchange items relevant with output clock pulse Co to exchanging setup unit 206 from multiple interchange item, carry out step 510;
Step 506: multiple DC terms of being inputted by oversampling logical block 202 in average the first scheduled time T1 of direct current estimation unit 2042, to produce DC parameter DCP;
Step 508: DCL processor 2044, according to the multiple DC parameter DCP that receive in the second scheduled time T2, is adjusted the direct current of equalizer 200 and set DCS, rebound step 502;
Step 510: exchange estimation unit 2062 to multiple interchanges of being inputted by oversampling logical block 202 in the first scheduled time T1, carry out discrete cosine transform and discrete sine conversion, to produce alternating-current parameter ACP;
Step 512: alternating current logic processor 2064, according to the multiple alternating-current parameter ACP that receive in the second scheduled time T2, is adjusted the interchange of equalizer 200 and set ACS, rebound step 502.
In step 502, oversampling logical block 202, according to oversampling clock pulse Cov, is carried out oversampling action to the data from a channel, to produce multiple DC terms and multiple interchange item.The frequency of oversampling clock pulse Cov must be greater than two times of frequency of data.In the embodiment of Fig. 5, oversampling clock pulse Cov is 10GHz, and the frequency of data is 2.5GHz, is 10GHz but the present invention is not limited to oversampling clock pulse Cov, and the frequency of data is 2.5GHz.In step 504, oversampling logical block 202 can be according to rising edge or the trailing edge of output clock pulse Co, and the relevant multiple DC terms of output and output clock pulse Co are to direct current setup unit 204 and output multiple exchange items relevant with output clock pulse Co to exchanging setup unit 206.In step 508, DCL processor 2044, according to the multiple DC parameter DCP in the second scheduled time T2, judges that whether the D. C. value of equalizer 200 is enough, adjusts according to this direct current of equalizer 200 and sets DCS.In step 512, alternating current logic processor 2064, according to the multiple alternating-current parameter ACP in the second scheduled time T2, judges that whether the interchange value of equalizer 200 is enough, adjusts according to this interchange of equalizer 200 and sets ACS.
In sum, the method for equalizer provided by the present invention and equalizing signal, carries out oversampling action according to oversampling logical block to the data from a channel, to produce multiple DC terms and multiple interchange item.And oversampling logical block can be according to output clock pulse, multiple DC terms of output and output clock pulse correlation are to multiple items that exchange of direct current setup unit and output and output clock pulse correlation to exchanging setup unit.Therefore, equalizer of the present invention needn't operate situation about being lockable in clock pulse data return signal phase place, and direct current estimation unit with exchange estimation unit and do not need to operate in high-frequency clock pulse.In addition, oversampling logical block is carried out oversampling action to the data from a channel, to produce multiple DC terms and multiple interchange item, and not direct D. C. value and the interchange value of obtaining from data as prior art.Therefore, be all the situation that exchanges item or DC terms for the data that receive within certain a period of time, the present invention maintains the last time direct current of equalizer and sets or exchange setting, causes the mistake that direct current is set or interchange is set of equalizer so as to improving prior art.
Certainly; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (8)
1. an equalizer, is characterized in that, comprises:
One oversampling logical block, in order to according to an oversampling clock pulse, to carry out an oversampling action from the data of a channel, to produce multiple DC terms and multiple interchange item, and according to an output clock pulse, from the plurality of DC terms output and multiple DC terms of this output clock pulse correlation and from the plurality of exchanges multiple items that exchange of output and this output clock pulse correlation;
One direct current setup unit, in order to according to multiple DC terms of being inputted by this oversampling logical block in one first scheduled time, adjusts a direct current of this equalizer and sets; And
One exchanges setup unit, in order to according to multiple interchanges of being inputted by this oversampling logical block in this first scheduled time, adjusts one of this equalizer and exchanges setting.
2. equalizer according to claim 1, is characterized in that, this direct current setup unit comprises:
One direct current estimation unit, is coupled to this oversampling logical block, in order to multiple DC terms of being inputted by this oversampling logical block in average this first scheduled time, to produce a DC parameter; And
One direct current logic processor, is coupled to this direct current estimation unit, in order to according to the multiple DC parameters in one second scheduled time, adjusts this direct current and sets.
3. equalizer according to claim 1, is characterized in that, this interchange setup unit comprises:
One exchanges estimation unit, is coupled to this oversampling logical block, in order to multiple interchanges of being inputted by this oversampling logical block in this first scheduled time, carries out a discrete cosine transform and discrete sine conversion, to produce an alternating-current parameter; And
One alternating current logic processor, is coupled to this interchange estimation unit, in order to according to the multiple alternating-current parameters in one second scheduled time, adjusts this interchange and sets.
4. equalizer according to claim 1, is characterized in that, the frequency of this oversampling clock pulse is greater than two times of frequency of these data.
5. a method for equalizing signal, is characterized in that, comprises:
According to an oversampling clock pulse, to carry out an oversampling action from the data of a channel, to produce multiple DC terms and multiple interchange item;
According to an output clock pulse, from the plurality of DC terms output and multiple DC terms to direct current setup units of this output clock pulse correlation and from the plurality of exchanges the multiple Xiang Zhiyi of interchange interchange setup units of output and this output clock pulse correlation;
Be pursuant to multiple DC terms of output in one first scheduled time, adjust the direct current of an equalizer and set; And
Be pursuant to multiple interchanges of output in this first scheduled time, adjust the interchange of this equalizer and set.
6. method according to claim 5, is characterized in that, is pursuant to multiple DC terms of output in this first scheduled time, and the direct current setting of adjusting this equalizer comprises:
Average multiple DC terms of inputting within this first scheduled time, to produce a DC parameter; And
According to the multiple DC parameters in one second scheduled time, adjust this direct current and set.
7. method according to claim 5, is characterized in that, is pursuant to multiple interchanges of output in this first scheduled time, and the interchange setting of adjusting this equalizer comprises:
To the plurality of interchange in this first scheduled time, carry out a discrete cosine transform and discrete sine conversion, to produce an alternating-current parameter; And
According to the multiple alternating-current parameters in one second scheduled time, adjust this interchange and set.
8. method according to claim 5, is characterized in that, the frequency of this oversampling clock pulse is greater than two times of this data frequency.
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| US35002910P | 2010-06-01 | 2010-06-01 | |
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| WO2006106473A2 (en) * | 2005-04-06 | 2006-10-12 | Nxp B.V. | Multi-user equalization method and device for wireless communication system |
| CN101019393A (en) * | 2004-07-12 | 2007-08-15 | 艾利森电话股份有限公司 | Equalizers for multi-branch receiver |
| CN101310493A (en) * | 2005-11-15 | 2008-11-19 | 高通股份有限公司 | Equalizer for a receiver in a wireless communication system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101019393A (en) * | 2004-07-12 | 2007-08-15 | 艾利森电话股份有限公司 | Equalizers for multi-branch receiver |
| WO2006106473A2 (en) * | 2005-04-06 | 2006-10-12 | Nxp B.V. | Multi-user equalization method and device for wireless communication system |
| CN101310493A (en) * | 2005-11-15 | 2008-11-19 | 高通股份有限公司 | Equalizer for a receiver in a wireless communication system |
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Effective date of registration: 20160203 Address after: Taipei City, Taiwan, China Patentee after: ETRON TECHNOLOGY, INC. Address before: China Taiwan Hsinchu Science Park, Hsinchu Patentee before: Etron Technology, Inc. |