CN102163158A - Method for starting system-on-a-chip by NAND flash memory - Google Patents
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- CN102163158A CN102163158A CN2011101111722A CN201110111172A CN102163158A CN 102163158 A CN102163158 A CN 102163158A CN 2011101111722 A CN2011101111722 A CN 2011101111722A CN 201110111172 A CN201110111172 A CN 201110111172A CN 102163158 A CN102163158 A CN 102163158A
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Abstract
The invention discloses a method for starting a system-on-a-chip by a NAND flash memory. The method is characterized by comprising the following steps of: reading startup header information from the NAND flash memory, reading startup codes in the NAND flash memory according to the startup header information, and executing the startup codes. According to the method provided by the invention, specification information of the NAND flash memory can be marked with low cost, and the system-on-a-chip can start from any novel NAND flash memory and still can synchronously protect the information marked by the user with enough ECC (Error Correction Code) intensity, so that reliability of the method is high.
Description
Technical field
The present invention relates to the method that a kind of system level chip utilizes nand flash memory to start.
Background technology
Nand flash memory is a kind of of flash internal memory, and it is inner to adopt non-linear macroelement pattern, for the realization of solid-state large-capacity internal memory provides cheap effective solution.It is bigger that the NAND-flash storer has a capacity, advantages such as rewriting speed is fast, be applicable to the storage of mass data, thereby in the industry cycle obtained application more and more widely, as comprising USB flash disk that digital camera, MP3 walkman memory card, volume are small and exquisite etc. in the embedded product.
Yet general support of current system level chip-SoC (System on Chip) directly starts from nand flash memory, and supports nand flash memory as much as possible.But because the nand flash memory technical development is very fast, nand flash memory device provider is also more and more, and the sign of nand flash memory does not have unified standard, causes the SoC that had solidified originally might not all support up-to-date nand flash memory.
SoC starts some specification informations that need read nand flash memory in advance from nand flash memory, comprises data-bus width, address width, page or leaf size, free area big or small, ECC (bug check and correction) strength information and erase block sizes.NAND-Flash block structural diagram as shown in Figure 1.Among Fig. 1, page or leaf size (Page Size) can be little page or leaf 512B and big page or leaf 2048B, 4096B, 8192B (byte); The free area size can be 16B, 64B, 128B, 218B, 216B, 224B or following other byte number, and the free area comprises ECC strength information and bad piece mark in order to storage; Nand flash memory is that unit reads and writes data with the page or leaf, and is the unit obliterated data with the piece, and in order to skip unreliable or bad piece, erase block sizes need be identified, and erase block sizes comprises 64 pages of pieces or 128 pages of pieces or more.
Nand flash memory specification information identification method commonly used at present has following several:
1, increases start-up mode pin (Boot Mode Pins), for example the start-up mode of the S3C6410 chip of Samsung is supported nand flash memory 512B-3,512B-4,2KB-5,5KB-5, be respectively 3 addresses of big or small 512 bytes of page or leaf, 4 addresses of 512 bytes, 5 addresses of 2048 bytes, 5 addresses of 4096 bytes.Its shortcoming is the nand flash memory of only supporting the NAND of 8 bit data bus width and not supporting 16 bit widths.Two of and for example middle Freescale i.MX31 start pins and represent page big or small 512 or 2048 bytes respectively, data-bus width 8 or 16.But this method dirigibility is relatively poor, will increase extra pin to SoC, and the nand flash memory kind of being supported is limited.
2, by reading the IDs of nand flash memory, comprise manufacturer's sign indicating number, device code, extended code is discerned the specification of nand flash memory.Supported by all nand flash memory flash memories as Read ID (90H) order (without any need for parameter).The OMAP3430 of TI adopts the method, but silicon chip (die) begins not follow in the past coding regulation at 4GB and above nand flash memory thereof.ONFI (Open Nand flash Interface) though standard N AND flash memory has unified coding, almost is not applied, especially ONFI1.X.
3, the positive JZ4760/Xburst650 of monarch has used a kind of method sign nand flash memory of complexity, accomplished substantially and can start from any one nand flash memory, but the shortcoming of this method is:
(1) though, identification information has the ECC protection of response, starts when reading these identification informations in reality, and is useless and can't carry out bug check and correction with ECC.Redundancy bytes that can only utilization itself is evaded the read error of nand flash memory;
(2), toggle speed is slow, trial and error to read repeatedly just may obtain identification information since little page or leaf (512 byte) and big page nand flash memory to read sequence different; Address width need repeatedly be attempted obtaining; The fixedly 24-bit ECC that is adopted carries out bug check and corrects influencing toggle speed.
(3), lack erase block sizes information, do not possess the functional characteristics of skipping unreliable or bad piece.
Summary of the invention
The identification method that the purpose of this invention is to provide a kind of low cost, reliability height and wieldy nand flash memory is so that quick start system level chip.
For achieving the above object, the invention provides the method that a kind of system level chip utilizes nand flash memory to start, it is characterized in that: read header (Boot Header) information that starts from nand flash memory, read start-up code in the nand flash memory, carry out start-up code according to starting header information.
The method according to this invention can identify the specification information of NAND with less cost, makes system level chip to start from novel arbitrarily NAND, still keeps using the information of enough ECC intensity protection user ID simultaneously, the reliability height.System level chip always can be read according to the mode sequence of big page or leaf and start header and ECC sign indicating number thereof, and according to starting the information that header identified, system level chip can normally be read the start-up code in the main areas, and carries out start-up code.
Description of drawings
After specific embodiments of the present invention being described in detail with way of example below in conjunction with accompanying drawing, other features of the present invention, characteristics and advantage will be more obvious.
In the accompanying drawing:
Fig. 1 is the nand flash memory block structural diagram;
Fig. 2 is the nand flash memory structural drawing of one embodiment of the invention;
Fig. 3 is the startup leader structural drawing of the nand flash memory of one embodiment of the invention;
Fig. 4 is the startup leader structural drawing of the nand flash memory of another embodiment of the present invention;
Fig. 5 is the startup leader structural drawing of the nand flash memory of another embodiment of the present invention.
Embodiment
Fig. 2 is the nand flash memory structural drawing of one embodiment of the invention.In Fig. 2, first half in first page of first of NAND is used to deposit header (Boot Header) information that starts, bug check and correction (ECC) sign indicating number, startup header and its ECC sign indicating number have fixing length, for example start header and adopt 512byte, and the ECC sign indicating number adopts 16-byte.Preferably, the ECC sign indicating number adopts the BCH algorithm of 8-bit error correction, and second page of first of NAND is used to deposit start-up code (Boot loader code), and corresponding free area part is used to deposit the corresponding ECC sign indicating number of start-up code.
Start page or leaf size information, free area size information, erase block sizes information, address width information, ECC pattern information, obligate information and ECC strength information that header is used to identify nand flash memory.Data-bus width in the nand flash memory specification information does not need sign, because data-bus width extensively uses the 8-bit nand flash memory, if will support the 16-bit nand flash memory can obtain device code or manufacturer's sign indicating number of nand flash memory, because the coding of manufacturer's sign indicating number, device code is well followed by the method for Read ID.
During startup, system level chip reads the startup header information from the NAND-Flash flash memory, reads start-up code in the NAND-Flash flash memory according to starting header information, carries out start-up code.
Have in the NAND-Flash flash memory storage under the situation of ECC sign indicating number of described startup header information, read the ECC sign indicating number from the NAND-Flash flash memory, and according to the ECC sign indicating number to starting the header information error correction.Have in the NAND-Flash flash memory storage under the situation of ECC sign indicating number of start-up code, from the NAND-Flash flash memory, read the ECC sign indicating number and according to the ECC sign indicating number to the start-up code error correction.
According to the present invention, can adopt the startup leader of different nand flash memories, to be suitable for dissimilar nand flash memories.
Fig. 3 is the startup leader structural drawing of the nand flash memory of one embodiment of the invention.Fig. 3 has illustrated that length is the startup header of 512-byte and the ECC sign indicating number that length is 16-byte.The page or leaf size that starts in the header adopts 4-byte length to come identification information, every page as nand flash memory is that 2048-byte is defined as big page or leaf, need be identified in starting header, little page or leaf (512-byte) nand flash memory need not sign, distinguishes by the method for Read ID; The free area size adopts 4-byte length to come identification information, needs sign (different ECC intensity need take the free area of different sizes) when needs calculate ECC intensity automatically.Erase block sizes adopts 4-byte length to come identification information, and nand flash memory is to be that unit reads and writes data with the page or leaf, and is the unit obliterated data with the piece, so that skip unreliable or bad piece; Address width adopts 1-byte length to come identification information, early stage nand flash memory is only accepted the address width fixed, 3 or 4 byte addresses, but the nand flash memory in while in that period has the coded system of standard, can distinguish address width by the mode of Read ID.Up-to-date nand flash memory always can be accepted the address width of 5 bytes, though unnecessary, the last column that also can be left in the basket, thus address width can identify out, to accelerate toggle speed.The ECC pattern adopts 1-byte length to come identification information, selects the ECC algorithm of reading that start-up code adopted, and for example the value of ECC is 0xFF, then selects the ECC algorithm of intensity according to the value of page or leaf size and free area size.The 498-byte that starts in the header is standby as reserving.Start the corresponding ECC of header and adopt 3-byte standby, adopt 13-byte length to identify the ECC strength information, use the ECC algorithm of user's appointment in order to accelerate toggle speed,, need identify as specifying the BCH algorithm of 8-bit as reserving.
Fig. 4 is the startup leader structural drawing of the nand flash memory of another embodiment of the present invention.Fig. 4 has illustrated that length is that startup header and the length of 512-byte is the ECC of 256-byte.The page or leaf size that starts in the header adopts 4-byte length to come identification information; The free area size adopts 4-byte length to come identification information; Erase block sizes adopts 4-byte length to come identification information; Address width adopts 1-byte length to come identification information; The ECC pattern adopts 1-byte length to come identification information, selects the ECC algorithm of reading that start-up code adopted; The 498-byte that starts in the header is standby as reserving.Start the corresponding ECC of header and adopt 217-byte standby, adopt 39-byte length to identify the ECC strength information, use the ECC algorithm of user's appointment in order to accelerate toggle speed,, need identify as specifying the BCH algorithm of 24-bit as reserving.
Fig. 5 is the startup leader structural drawing of the nand flash memory of another embodiment of the present invention.Fig. 5 has illustrated that length is that startup header and the length of 256-byte is the ECC of 256-byte.The page or leaf size that starts in the header adopts 4-byte length to come identification information; The free area size adopts 4-byte length to come identification information; Erase block sizes adopts 4-byte length to come identification information; Address width adopts 1-byte length to come identification information; The ECC pattern adopts 1-byte length to come identification information, selects the ECC algorithm of reading that start-up code adopted; The 242-byte that starts in the header is standby as reserving.Start the corresponding ECC of header and adopt 220-byte standby, adopt 36-byte length to identify the ECC strength information, use the ECC algorithm of user's appointment in order to accelerate toggle speed,, need identify as specifying the BCH algorithm of 24-bit as reserving.
Obviously, under the prerequisite of true spirit that does not depart from patent of the present invention and scope, patent of the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.Patent of the present invention scope required for protection is only limited by described claims.
Claims (8)
1. a system level chip utilizes the method that nand flash memory starts, and it is characterized in that: read the startup header information from nand flash memory, read start-up code in the nand flash memory according to starting header information, carry out start-up code.
2. startup method according to claim 1, it is characterized in that nand flash memory stores the ECC sign indicating number of described startup header information, described from nand flash memory read the step that starts header information comprise read the ECC sign indicating number and according to the ECC sign indicating number to starting the header information error correction.
3. startup method according to claim 2 is characterized in that the space size of ECC sign indicating number is different because of algorithm.
4. startup method according to claim 1 is characterized in that nand flash memory stores the ECC sign indicating number of described start-up code, the described step that reads the start-up code in the nand flash memory comprise read the ECC sign indicating number and according to the ECC sign indicating number to the start-up code error correction.
5. according to the described method of one of claim 2-4, it is characterized in that: described ECC sign indicating number comprises the BCH algorithm.
6. startup method according to claim 1 is characterized in that: the ECC sign indicating number of described startup header information and/or described startup header information is arranged on the first half in first page of first of nand flash memory.
7. startup method according to claim 1 is characterized in that: described startup header information comprises that page or leaf size, free area are big or small, in erase block sizes, address width and the ECC pattern one or several.
8. method according to claim 1 is characterized in that: comprise by the mode that reads ID and obtain one or more in data-bus width, address width and the little page information.
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Cited By (8)
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| CN102279763A (en) * | 2011-08-30 | 2011-12-14 | 福州瑞芯微电子有限公司 | Method for optimizing boot read-only memory (BOOTROM) |
| CN102610279A (en) * | 2012-01-19 | 2012-07-25 | 苏州希图视鼎微电子有限公司 | Method for executing NAND flash memory by solidifying code |
| CN102609282A (en) * | 2012-01-19 | 2012-07-25 | 苏州希图视鼎微电子有限公司 | Execution method for NAND flash curing codes |
| CN102623066A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Saving and acquisition method for solidification code parameter table |
| CN102622243A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Method for executing solidified codes supporting various NAND flash memories |
| CN102622305A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Method for processing width parameters of hardware access addresses in NAND flash memory |
| CN107273233A (en) * | 2017-05-24 | 2017-10-20 | 浙江大华技术股份有限公司 | A kind of method for reading data and device |
| CN109976815A (en) * | 2019-03-20 | 2019-07-05 | 深圳忆联信息系统有限公司 | A kind of method and its system accelerating Nandboot |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279763A (en) * | 2011-08-30 | 2011-12-14 | 福州瑞芯微电子有限公司 | Method for optimizing boot read-only memory (BOOTROM) |
| CN102610279A (en) * | 2012-01-19 | 2012-07-25 | 苏州希图视鼎微电子有限公司 | Method for executing NAND flash memory by solidifying code |
| CN102609282A (en) * | 2012-01-19 | 2012-07-25 | 苏州希图视鼎微电子有限公司 | Execution method for NAND flash curing codes |
| CN102623066A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Saving and acquisition method for solidification code parameter table |
| CN102622243A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Method for executing solidified codes supporting various NAND flash memories |
| CN102622305A (en) * | 2012-01-19 | 2012-08-01 | 苏州希图视鼎微电子有限公司 | Method for processing width parameters of hardware access addresses in NAND flash memory |
| CN107273233A (en) * | 2017-05-24 | 2017-10-20 | 浙江大华技术股份有限公司 | A kind of method for reading data and device |
| CN107273233B (en) * | 2017-05-24 | 2020-06-19 | 浙江大华技术股份有限公司 | Data reading method and device |
| CN109976815A (en) * | 2019-03-20 | 2019-07-05 | 深圳忆联信息系统有限公司 | A kind of method and its system accelerating Nandboot |
| CN109976815B (en) * | 2019-03-20 | 2022-03-29 | 深圳忆联信息系统有限公司 | Method and system for accelerating Nandboot |
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