CN102162122A - Preparation method of P-type medium-low-resistance silicon core carrier - Google Patents
Preparation method of P-type medium-low-resistance silicon core carrier Download PDFInfo
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- CN102162122A CN102162122A CN2011100370607A CN201110037060A CN102162122A CN 102162122 A CN102162122 A CN 102162122A CN 2011100370607 A CN2011100370607 A CN 2011100370607A CN 201110037060 A CN201110037060 A CN 201110037060A CN 102162122 A CN102162122 A CN 102162122A
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Abstract
The invention relates to a preparation method of a P-type medium-low-resistance silicon core carrier, and in particular relates to a preparation method of a P-type medium-low-resistance silicon core carrier which is required in a process for preparing high-purity polysilicon with a chemical vapor deposition method. The method is characterized by comprising the following steps: selecting a high-purity raw-material silicon ingot; drilling a cylindrical hole on the end of the raw-material silicon ingot, cleaning and drying the hole; placing the processed raw-material silicon ingot into a zone melting furnace and fixing; rapidly taking a proper amount of high-purity metallic gallium from the inside of a freezer into the cylindrical hole on the end of the raw-material silicon ingot, and sealing; and carrying out an operation of zone melting and drawing to prepare a silicon core to obtain the P-type medium-low-resistance silicon core carrier. The carrier prepared with the method is uniform is doping, the phenomenon of photoinduced attenuation of a crystal silicon photovoltaic battery can be decreased or basically inhibited, and the problem of resistance nonuniformity and extra compensation of an N-type silicon core carrier for polysilicon chemical vapor deposition is solved.
Description
Technical field
The present invention relates to a kind of making method of P type medium or low resistance silicon core carrier, especially a kind ofly prepare in the high-purity polycrystalline silicon process making method of needed P type medium or low resistance silicon core carrier with chemical gaseous phase depositing process.
Background technology
The chemical gaseous phase depositing process in reduction furnace is generally adopted in the production of high purity polycrystalline silicon, be that carrier silicon core resistive is heated to the temperature (about 1100 ℃) that is fit to crystal growth, feed suitable high-purity intermediate gas (as trichlorosilane, hydrogen, or silane), at the continuous high-purity crystal of growing and making new advances of carrier surface, thereby obtain polysilicon product.Can avoid other electro-conductive material carrier to polysilicon pollution and carrier and problems such as polysilicon separates owing to use the silicon core of homogeneity, being used for the interior sedimentary main carrier of polycrystalline silicon reducing furnace at present is the silicon core of Φ 6mm～Φ 15mm, and the HIGH-PURITY SILICON core resistivity is very high at normal temperatures, can reach thousands of Ω cm, more do not have resistive heating and make silicon wicking surface reach 1100 ℃ left and right sides high temperature if applying conventional power supply silicon core can not conduct electricity this moment.In order to address the above problem, generally adopt two kinds of schemes at present: 1. connect conventional power supply after the high-voltage breakdown; 2. adopt the external placed type pre-heaters to be preheated to and connect conventional power supply about 600 ℃.The shortcoming of high-voltage breakdown is high-pressure electric control system and heating starting program complexity, the performance requriements height of counter electrode insulating material, easily generating electrodes electric discharge phenomena; The shortcoming of external placed type preheater preheating is to need extra increase equipment and device, the heating starting program is more complicated also, after preheating end, need to open the pre-heaters joint flange and take out the external placed type pre-heaters, can cause the furnace air displacement security incident not exclusively and easily to occur.
Comparatively ideal silicon core heating starting mode is that middle straightening connects conduction heating, utilization promptly can realize such Starting mode to the doping of silicon core with the resistivity (about 10～100 Ω cm) that reduces the silicon core, and industrial production has adopted N type phosphorus doping to reach the requirement that reduces silicon core resistivity at present.And photovoltaic cell mostly uses the P-type conduction type, by polycrystalline silicon raw material pulling monocrystal silicon ingot or casting polycrystalline silicon ingot and make and must carry out extra P type compensation in the process of silicon chip.If directly adopt P type silicon core deposit spathic silicon, will reduce P/N type compensativity, help to improve the polysilicon product quality.In addition because N type phosphorus doping adopts raw material silicon rod surface brush to be coated with doping agent, the operation poor reproducibility, the longitudinal resistivity skewness of silicon core might cause silicon core local temperature too high and cause the fusing of silicon core when high-voltage breakdown; Carry out N type phosphorus doping and adopt neutron irradiation to change silicon isotope into phosphorus, its cycle is long, cost is high.P type silicon core belongs to hole conduction, general in its preparation process the III A family element in the doping element periodictable to reach suitable conduction type and resistivity value.Boron commonly used mixes can effectively reduce silicon core resistivity, also is to adopt the boron-doping silicon chip substantially in the conventional solar cell manufacturing technology.But the displacement boron in the boron-doping crystal silicon and the Sauerstoffatom of crystal silicon mid gap state can form boron oxygen complex body under illumination or current carrier injection, become the deep energy level deathnium, and life-span and diffusion length that this can reduce minority carrier cause the efficient of photovoltaic cell to reduce.
Summary of the invention
The objective of the invention is to overcome the defective of prior art, a kind of making method of P type medium or low resistance silicon core carrier is provided.
Technical scheme of the present invention is: the characteristics of this method are to comprise following steps:
A. choose the high pure raw material silicon ingot;
B. bore a cylindrical hole in raw material silicon ingot end, clean and dry this hole;
C. the raw material silicon ingot after will handling is placed in the zone melting furnace and fixes;
D. take out an amount of high purity metal gallium in the refrigerator rapidly and put in the cylindrical hole of raw material silicon ingot termination, seal;
Gallium consumption M
GaMethod of calculation be:
M
Ga=?C
S*m
Ga*V
R?/?N
A*K
o
C
s(cm
-3) be the expection concentration of doped gallium element in the silicon, m
GaBe the nucleidic mass of Ga, N
ABe Avogadro constant, V
R(cm
3) be the melting zone volume of Qu Rongshi, K
0Be the equilibrium segregation coefficient of gallium, K
0=0.008.
E. distinguish the operation of melting and pulling silicon core.
The present invention has following advantage and effect: 1, because the segregation coefficient of gallium element in silicon only is 0.008, an amount of high purity gallium is placed the termination of silicon rod, utilize gallium element less segregation coefficient in silicon, the trace gallium element is along with moving of melting zone can evenly enter in the solid silicon core, and on whole silicon core length uniform distribution, thereby obtain the P type medium or low resistance silicon core that uniform resistivity distributes.2, owing to the employing gallium mixes, thereby avoid the introducing of boron, can reduce or suppress substantially the photo attenuation phenomenon of crystal silicon photovoltaic battery.3, solved the problem of chemical vapor deposition of polysilicon and extra compensation inhomogeneous with N type silicon core carrier resistivity.
Description of drawings
Fig. 1 is raw material silicon ingot termination bore position and the method synoptic diagram of placing gallium.
Embodiment
This method may further comprise the steps:
The raw material silicon ingot is classified according to conduction type and resistivity size, the raw material silicon ingot is cut arrangement, make diameter D=30mm, length L=400mm, bore a cylindrical hole (as shown in Figure 1), the about 1cm of volume in raw material silicon ingot termination
3, to silicon ingot clean, drying, will clean, the dried raw material silicon ingot is placed in the zone melting furnace and fixing; In refrigerator, take out gallium M rapidly
Ga, put into the cylindrical hole (M of raw material silicon ingot termination
GaMethod of calculation be: M
Ga=C
S* m
Ga* V
R/ N
A* K
0
Wherein, K
0=0.008, the expection concentration C s of doped gallium element is 10 in this example
15Cm
-3, the nucleidic mass of Ga is 69.7, melting zone volume V
RBe 15cm
3, K
0=0.008, as calculated, M in this example
GaBe 0.21mg), the silico briquette (lid) of prior excision forming is placed on cylindrical hole place, silicon ingot termination, size is advisable to cover gallium; Regulate high frequency electric source, make the silicon and the gallium fusing of silicon ingot end and form eutectic, distinguish the molten silicon core operation of drawing; At last, obtain P type medium or low resistance silicon core carrier.Silicon core resistivity is about 15 Ω cm.
Among Fig. 1,1-raw material silicon ingot, 2-cylindrical hole, 3-lid, 4-gallium.
Even flat zone melting method mixes and makes the signal of silicon core head and the tail impurity concentration
Smear zone melting method and carry out P
2
O
5
Mix and make the signal of silicon core head and the tail impurity concentration
Vertical pulling method is mixed and is made the signal of silicon core head and the tail impurity concentration
Claims (1)
1. the making method of a P type medium or low resistance silicon core carrier is characterized in that the method includes the steps of:
A. choose the high pure raw material silicon ingot;
B. bore a cylindrical hole in raw material silicon ingot end, clean and dry this hole;
C. the raw material silicon ingot after will handling is placed in the zone melting furnace and fixes;
D. take out an amount of high purity metal gallium in the refrigerator rapidly and put in the cylindrical hole of raw material silicon ingot termination, seal;
Gallium consumption M
GaMethod of calculation be:
M
Ga=?C
S*m
Ga*V
R?/?N
A*K
o
C
s(cm
-3) be the expection concentration of doped gallium element in the silicon, m
GaBe the nucleidic mass of Ga, N
ABe Avogadro constant, V
R(cm
3) be the melting zone volume of Qu Rongshi, K
0Be the equilibrium segregation coefficient of gallium, K
0=0.008;
E. distinguish the operation of melting and pulling silicon core.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100370607A CN102162122A (en) | 2010-11-26 | 2011-02-14 | Preparation method of P-type medium-low-resistance silicon core carrier |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010560030 | 2010-11-26 | ||
| CN201010560030.X | 2010-11-26 | ||
| CN2011100370607A CN102162122A (en) | 2010-11-26 | 2011-02-14 | Preparation method of P-type medium-low-resistance silicon core carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102162122A true CN102162122A (en) | 2011-08-24 |
Family
ID=44463566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100370607A Pending CN102162122A (en) | 2010-11-26 | 2011-02-14 | Preparation method of P-type medium-low-resistance silicon core carrier |
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| CN (1) | CN102162122A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106191994A (en) * | 2016-07-08 | 2016-12-07 | 亚洲硅业（青海）有限公司 | A kind of method eliminating silicon core exception |
| CN107653491A (en) * | 2016-07-26 | 2018-02-02 | 新特能源股份有限公司 | A kind of high resistivity silicon core and its growing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101148777A (en) * | 2007-07-19 | 2008-03-26 | 任丙彦 | Method and device for growing gallium-mixing silicon monocrystal by czochralski method |
| CN101812726A (en) * | 2010-04-13 | 2010-08-25 | 上海太阳能电池研究与发展中心 | Method for preparing gallium-doped p-type crystalline silicon |
-
2011
- 2011-02-14 CN CN2011100370607A patent/CN102162122A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101148777A (en) * | 2007-07-19 | 2008-03-26 | 任丙彦 | Method and device for growing gallium-mixing silicon monocrystal by czochralski method |
| CN101812726A (en) * | 2010-04-13 | 2010-08-25 | 上海太阳能电池研究与发展中心 | Method for preparing gallium-doped p-type crystalline silicon |
Non-Patent Citations (2)
| Title |
|---|
| HIROSHI KIMURA ET.AL.: "Improved uniformity in float zone Si:Ga", 《SPIE：INFRARED DETECTOR MATERIALS》 * |
| 杨启基 等: "氢气保护FZ硅掺杂镓研究", 《激光与红外》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106191994A (en) * | 2016-07-08 | 2016-12-07 | 亚洲硅业（青海）有限公司 | A kind of method eliminating silicon core exception |
| CN106191994B (en) * | 2016-07-08 | 2018-06-29 | 亚洲硅业（青海）有限公司 | A kind of method for eliminating silicon core exception |
| CN107653491A (en) * | 2016-07-26 | 2018-02-02 | 新特能源股份有限公司 | A kind of high resistivity silicon core and its growing method |
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Application publication date: 20110824 |