CN102158232A - LDPC (low-density parity-check) storage use method as well as LDPC decoding method and device - Google Patents
LDPC (low-density parity-check) storage use method as well as LDPC decoding method and device Download PDFInfo
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Abstract
The invention relates to an LDPC (low-density parity-check) storage use method as well as an LDPC decoding method and device, and the methods and device provided by the invention are suitable for a decoding process in a wireless receiver. The LDPC storage use method comprises the following steps: firstly, confirming a variable node process (VNP) or check node process (CNP) to be performed in the same period of time in the decoding process; secondly, distributing the VNP or CNP to be performed in the same period of time into different VNP groups or CNP groups; then, choosing the folding factors of storage units according to an expected data throughout; and finally, serially connecting the storage units into a plurality of parallel processing storage modules, according to the folding factors and the distributed VNP groups or CNP groups.
Description
Technical field
The present invention relates to the low density parity check code memory using method of (Low Density Parity Check Code is called LDPC again), particularly relate to a kind of memory using method, LDPC coding/decoding method and device thereof at LDPC.
Background technology
Low density parity check code (Low Density Parity Check Code is designated hereinafter simply as LDPC) is widely used in the wireless communication technology gradually at present, and the performance of LDPC is not worse than the rich sign indicating number of the spy who is widely used at present (Turbo code).For example, at (the European Telecommunications Standards Institute of ETSI, abbreviate ETSI as) second generation digital video broadcast system (the Digital VideoBroadcasting Second Generation that formulated, abbreviate DVB-S2 as) in the standard, promptly adopt LDPC in a large number on chnnel coding.
Though LDPC has relative good channel error checking and checking feature on chnnel coding, the decoding process of LDPC is to adopt the mode of soft-decision (soft-decision) to carry out, and in general needs the loop computation of repeatability to obtain decoded result.In addition, the decoding process of LDPC needs the parity matrix of large-size (Parity check matrix) to assist the computing of decoding, and then needs the memory module of larger capacity to realize its decoding process.So on the integrated circuit of the decoding device of LDPC, the most chip space of memory usage usually.
The coding/decoding method of traditional LDPC or decoding device can disclose the technology contents of case 2008/0104474A1 in early days with reference to the U.S., wherein mention similar use variable node flow process (Variable node process, abbreviate VNP as) and the compute mode of check-node flow process (Checknode process abbreviates CNP as) finish decoding process.And be to adopt a kind of amphicheirality's figure (bipartite graph is called Tanner graph again) to link VNP flow process and CNP flow process and corresponding temporary storage unit between VNP flow process and the CNP flow process.
Figure 1A is a kind of schematic diagram of parity matrix 110, and Figure 1B is the schematic diagram of relation between variable node in the parity matrix 110 (Variable nodes) and the check-node (Check nodes).Shown in Figure 1A, 7 row of parity matrix 110 correspond to variable node x separately
1, x
2, x
3, x
4, x
5, x
6, x
7And 3 row of parity matrix 110 correspond to check-node c separately
1, c
2, c
3The probability information (probability information) that the decoding process of LDPC is relevant with LDPC is carried out matrix multiplication operation with parity matrix 110 and is tried to achieve decoded result.In fact, the LDPC decoding device be with the probability information temporary storage in the memory cell that corresponds in the parity matrix 110 to the position of " 1 ", in turn these probability information are carried out computing by variable node and check-node again.
Shown in Figure 1B, when between variable node and the check-node line being arranged in the parity matrix 110, just can carry out computing in turn by variable node and check-node.After having the variable node of corresponding relation and check-node (the line relation is arranged each other) shown in Figure 1B in Figure 1B computing being finished separately, all operation result separately can be temporarily stored into to identical memory cell or memory location.Variable node and check-node take turns computing and once just finish computing circulation (computation cycle) at last.If correspond to when not having corresponding relation between the variable node of parity matrix 110 and the check-node, then do not need to carry out any computing.When the computing circulation was more repeatedly counted, obtained LDPC decoded result also can be got over the correct result of convergence.
Fig. 1 C is a kind of memory architecture 130 of LDPC decoding device.This memory architecture 130 is handled the memory architecture of framework for using part parallel (partially parallel).In Fig. 1 C, memory cell 132,134,136,138 all is identical memory cell, and memory architecture 130 is corresponding to the parity matrix (Paritycheck matrix) of LDPC, and memory architecture 130 has at least (m+1) * (n+1) individual memory cell.The binding of each memory cell and other memory cells, or also comprise clock pulse port Clock, FPDP Data, addressing port Addr, WE port Wren and data-out port Q at least with the binding of VNP flow process or CNP flow process.Therefore, in the decoding process of LDPC, especially utilize large-sized parity matrix to assist under the situation of decoding process, the memory architecture 130 that part parallel is handled obviously has crowded (routing congestion) problem of cabling.For example the DVB-S2 standard-required must have 64,800 resource block size to carry out decoding process.If each information is to adopt 6 positions to represent, then 64,800 blocks have about 1.7 hundred ten thousand positions altogether and need be temporarily stored in the memory module.Though can being divided into the memory module that corresponds to parity matrix the memory cell of reduced size, memory architecture 130 carries out computing, but when the quantity of memory cell becomes huge (for example, tens thousand of memory cells), the space between the adjoining memory cell can diminish.Solve the cabling congested problem even utilize to widen between the memory cell, cabling complexity still quite high (because involve between memory cell, VNP processing unit and the CNP processing unit connection relationship), and the memory area that is caused can be quite big.
Another kind of traditional LDPC coding/decoding method or decoding device is that the memory cell that will correspond to identical VNP flow process or CNP flow process is connected in the distinct group group.When carrying out LDPC decoding computing, adopt the mode of information in the serial read/write memory cell to carry out computing to each group.But, the decoder architecture or the coding/decoding method of the serial read/write of this collocation VNP flow process or CNP flow process, only solve the problem of the crowded or cabling complexity of cabling, the decoding arithmetic speed that is provided is slow excessively, and then reduces overall data throughput (Data throughput).
Summary of the invention
Example embodiment of the present invention provides the memory application method of a kind of low density parity check code (LDPC), a kind of decoding method of low density parity check codes and device thereof.
Example embodiment of the present invention provides the memory using method of a kind of low density parity check code (LDPC), is applicable to the decode procedure in the wireless receiver.The memory using method of low density parity check code may further comprise the steps.At first, variable node flow process (VNP) or the check-node flow process (CNP) that will carry out at identical time phase in the decision decode procedure.Then, will be distributed in different variable node flow process groups or the check-node flow process group in variable node flow process or the check-node flow process that identical time phase carries out.Moreover, according to the folding factor of anticipatory data throughput selection memory unit.Then, according to folding factor and the variable node flow process group or the check-node flow process group that are distributed, a plurality of memory cells are connected into a plurality of parallel processing memory modules.
Example embodiment of the present invention provides a kind of decoding method of low density parity check codes, is applicable to the decode procedure of radio receiver.Decoding method of low density parity check codes may further comprise the steps.At first, in the first memory module with the second memory module in probability information carry out a variable node flow process or a check-node flow process.Then, judge in the first memory module with the second memory module in probability information whether satisfy a decoding end condition.In addition, hard decision of probability information via of first memory module is converted to a low density parity check code dateout, and carries out a rearrangement by the second memory module.
Example embodiment of the present invention provides a kind of decoding low-density parity-check (ldpc) code device, is applicable to the decode procedure of radio receiver.The decoding low-density parity-check (ldpc) code device comprises that variable node processing module, code check node processing module, computing stop judge module and slicer.The variable node processing module, in order to in the first memory module with the second memory module in probability information carry out a variable node flow process.The code check node processing module, in order to in the first memory module with the second memory module in probability information carry out a check-node flow process.Computing stops judge module, in order to judge in the first memory module with the second memory module in probability information whether satisfy the end condition of decoding.Slicer in order to the probability information with the first memory module, is converted to a low density parity check code dateout through a hard decision, and resequences by the second memory module.
Hereinafter will describe example embodiment of the present invention in conjunction with the accompanying drawings in detail, so that above-mentioned feature and advantage can become apparent.
Description of drawings
Figure 1A is a kind of schematic diagram of parity matrix.
The schematic diagram of Figure 1B for concerning between variable node in the parity matrix and the check-node.
Fig. 1 C is a kind of memory architecture of LDPC decoding device.
Fig. 2 is the system block diagrams of a kind of LDPC decoding device of being illustrated of an example embodiment according to the present invention.
Fig. 3 A is the schematic diagram of the parity matrix of an example embodiment of the present invention.
Fig. 3 B is the schematic diagram of a submatrix of an example embodiment of the present invention.
Fig. 3 C is the schematic diagram of a parity matrix through rearranging according to an example embodiment of the present invention.
Fig. 3 D is the schematic diagram of a parity matrix through dividing into groups according to another example embodiment of the present invention.
Fig. 4 is the schematic diagram of the memory architecture handled of a kind of improvement type part parallel that an example embodiment according to the present invention is illustrated.
Fig. 5 is the flow chart of a kind of LDPC memory using method of being illustrated of an example embodiment according to the present invention.
Fig. 6 is the flow chart of a kind of LDPC coding/decoding method of being illustrated of an example embodiment according to the present invention.
Fig. 7 is the system block diagrams of the another kind of LDPC decoding device that illustrates according to another example embodiment of the present invention.
[main element symbol description]
110,310: parity matrix 312,314: diagonal
130,400: memory architecture 500:LDPC memory using method
132,134,136,138: memory list S502～S510, S602～S610: step
The 600:LDPC of unit coding/decoding method
200, the 700:LDPC decoding device is handled network element at 742: the first
202: the information-storing device module is handled network element at 744: the second
The variable node processing module was handled network element in 746: the three in 204: the first
206: the first memory module is everywhere managed network element at 748: the
208: the second variable node processing modules 320,330,340, A, B: submatrix
210: second memory module c
1, c
2, c
3: check-node
212: code check node processing module S1, S2, S3, S4: cell matrix
214: memory addressing memory module x
1, x
2, x
3, x
4, x
5, x
6, x
7: variable
216: the slicer node
218: computing stops judge module
220: control module
Embodiment
Now will be in detail with reference to disclosed example embodiment, described example embodiment mostly illustrates in the accompanying drawings, and subsidiary one what carry is that identical Reference numeral is used to represent same or analogous element in the whole accompanying drawing.
Example embodiment of the present invention provides the memory application method of a kind of LDPC, a kind of LDPC coding/decoding method and device thereof.The memory application method of LDPC is to use in the decoding process of LDPC.Below will utilize Fig. 2 and Fig. 7 to introduce LDPC decoding device 200, and utilize Fig. 5 to introduce the memory using method of LDPC, and utilize Fig. 6 to introduce the LDPC coding/decoding method.
Fig. 2 is the system block diagrams of a kind of LDPC decoding device 200 of being illustrated of an example embodiment according to the present invention.LDPC decoding device 200 can be configured in the radio communication receiver, for example: the receiver that uses the DVB-S2 standard.In this example embodiment, LDPC decoding device 200 comprises information (information) memory module 202 at least, first variable node is handled (Variable node process, abbreviate VNP as) module 204, first memory module 206, second variable node is handled (VNP) module 208, second memory module 210, code check node processing (Check node process abbreviates CNP as) module 212, memory addressing memory module 214, slicer (Slicer) 216, computing stops judge module (computation termination determination module) 218 and control module (control module) 220 (not shown)s.
In this example embodiment, memory module for example: first memory module 206 can be in order to the stored program module with second memory module 210.Described program module when carrying out, is being carried out one or more process that produces media program by processor module (for example: a VNP module 204, the 2nd VNP module 208 and CNP module 212).In addition, first memory module 206 can be one or more storage arrangement with second memory module 210, in order to storage data, operation result or probability information.In this example embodiment, first memory module 206 for example can comprise with the storage arrangement of second memory module 210, magnetic storage apparatus, optical storage apparatus, static RAM (StaticRandom Access Memory, be called SRAM again), one of them or its combination of phase transition storage (Phase changememory is called PCM again) or flash memory (FLASH memory) device.In addition, first memory module 206 and second memory module 210 in other embodiments of the invention, can also combine is a memory module.In this example embodiment, a VNP module 204, the 2nd VNP module 208 can comprise a plurality of processor units, processor device or processor chips separately with CNP module 212.
Please refer to Fig. 2, in this example embodiment, control module 220 is electrically connected to information-storing device module 202, a VNP module 204, first memory module 206, the 2nd VNP module 208, second memory module 210, CNP module 212, memory addressing memory module 214, slicer 216 and computing termination judge module 218.In addition, control module 220 (is for example imported flow process in order to the outside of controlling whole LDPC decoding device 200, reception LDPC input) beginning and end, outside output flow process are (for example, output LDPC output) beginning and end, and control signal transmission between above-mentioned each element, or control beginning and the end that each element is carried out the computing flow process separately.
Please refer to Fig. 2; information-storing device module 202 is in order to temporary probability information (probabilityinformation) by leading portion demodulating equipment (demodulator) the LDPC decoding device 200 that offers; and probability information is converted into log-likelihood ratio (Log-LikelihoodRatio usually; abbreviate LLR as) pattern, be beneficial to subsequent operation.LDPC decoding device 200 will be in a fixed cycle or Preset Time threshold value, for example: in the frame period (frameduration), finish the LDPC decoding process.The one VNP module 204 and the 2nd VNP module 208 can be integrated into same node processing module in other example embodiment of the present invention.In this example embodiment, say clearly operation principles in order to separate, so adopt the mode separately illustrate a VNP module 204 and the 2nd VNP module 208, but a VNP module 204 and the 2nd VNP module 208 can be divided the work running synchronously, or work in coordination with (collaboratively) and operate.The one VNP module 204 and the 2nd VNP module 208 are coupled to information-storing device module 202, and be electrically connected to first memory module 206 and second memory module 210 respectively, in order to the probability information in the information-storing device module 202, temporary respectively to first memory module 206 and second memory module 210.In addition, above-mentioned probability information corresponds to the position for " 1 " of numerical value in the parity matrix.
Fig. 3 A is the schematic diagram of the parity matrix 310 of an example embodiment of the present invention.Parity check matrix H (being the parity matrix 310 among Fig. 3 A) is of a size of that n * (n-k), wherein n＞k, and n and k are positive integer.When parity check matrix H is applied in the LDPC decoding process usually, have the irregular characteristic that repeats accumulation (Irregular RepeatAccumulate abbreviates IRA as), also be IRA-LDPC.In other embodiments of the invention, parity check matrix H can also have the characteristic of accurate circulation (Quasi-Cyclic abbreviates QC as), also is QC-LDPC.In actual LDPC decoding process,, parity check matrix H can be divided into a sub-matrix A and a sub-matrix B for the convenience of decoding process.As shown in Figure 3A, submatrix A is of a size of k * (n-k), and submatrix B is of a size of (n-k) * (n-k).In addition, among the submatrix A distribution of " 1 " more irregular, and among the submatrix B distribution of " 1 " the rule.Fig. 3 B is the schematic diagram of a submatrix B of an example embodiment of the present invention.Submatrix B is a square matrix, and submatrix B is a kind of special unit matrix (identitymatrix), and it has the diagonal 312,314 that is all " 1 ", and a fixing skew (offset) is arranged between the diagonal 312,314.
Therefore, further specify with reference to Fig. 2 and Fig. 3 A, the one VNP module 204 will correspond to the probability information temporary storage of submatrix A to first memory module 206, and the 2nd VNP module 208 will correspond to the probability information temporary storage of submatrix B to second memory module 210.In addition, CNP module 212 is electrically connected to first memory module 206 and second memory module 210.The one VNP module 204 and CNP module 212 are carried out computing to the probability information of first memory module 206 respectively in turn, carry out computing in turn according to the corresponding relation (line among Figure 1B concerns) of variable node shown in similar Figure 1B and check-node.After the one VNP module 204 is finished computing separately with CNP module 212, all operation result separately can be temporarily stored into identical memory location to the first memory module 206, and a VNP module 204 and CNP module 212 in turn computing once just finish a computing circulation at last.Similar ground, the 2nd VNP module 208 and CNP module 212 carried out computing to the probability information of second memory module 210 respectively in turn.After the 2nd VNP module 208 is finished computing separately with CNP module 212, all operation result separately can be temporarily stored into identical memory location to the second memory module 210, and the 2nd VNP module 208 and CNP module 212 in turn computing once just finish a computing circulation at last.
Please refer to Fig. 2, CNP module 212 also is coupled to computing and stops judge module 218.Whenever finish a computing circulation, CNP module 212 is with the probability information of first memory module 206 with second memory module 210, be sent to computing and stop judge module 218, stop judge module 218 by computing and judge whether resulting probability information meets the condition of following equation (1):
VH
T=0 ... equation (1)
Wherein, v is a vector, the LDPC input that on behalf of LDPC decoding device 200, it received, that is the LDPC code word (codeword) through being received after the wireless transmission, and H
TTransposed matrix (Transpose matrix) for above-mentioned parity check matrix H.
If during the condition of the equation (1) that the probability information conforms in first memory module 206 and the second memory module 210 is above-mentioned, then computing stops judge module 218 and notifies a VNP module 204, the 2nd VNP module 208 and the present computing of CNP module 212 time-outs by control module 220.At this moment, slicer 216 will correspond to the probability information of submatrix A in the first memory module 206, and is temporary to second memory module 210, that is overrides the content of (overwrite) second memory module 210.Probability information via hard decision in the first memory module 206 and after producing LDPC output, rearrangement (re-ordering) or rearrangement (re-organization) in second memory module 210 are by the 210 output LDPC outputs of second memory module.Slicer 216 is electrically connected to first memory module 206 and second memory module 210, and the probability information temporary storage that corresponds to submatrix A in first memory module 206 is during to second memory module 210, the probability information of antithetical phrase matrix A is carried out hard decision (hard-decision), to produce definite decoded result.After rearrangement or rearranging, the position that corresponds to the LDPC input that LDPC decoding device 200 received that puts in order, the position of the LDPC output that is produced puts in order.Probability information among the submatrix B is in the stage of output LDPC output, also is the characteristic of block coding (Block code) for redundant (redundant) and this at last.So present embodiment is resequenced by second memory module 210 or is rearranged definite decoded result.
If a VNP module 204, the 2nd VNP module 208 surpass a Preset Time threshold value with the time that CNP module 212 is spent, for example control module 220 confirms to have reached a Preset Time threshold value, and then control module 220 is suspended the present computing of a VNP module 204, the 2nd VNP module 208 and CNP module 212.Described Preset Time threshold value can be a frame period (frame duration).Then, control module 220 notice slicers 216 are with the probability information in the first memory module 206, after being converted to LDPC output through hard decision, temporary to second memory module 210 with rearrangement or rearrange, again by the 210 output LDPC outputs of second memory module.
If the probability information of first memory module 206 and second memory module 210 does not meet the condition of above equation (1), and the spent time of computing at present, then a VNP module 204, the 2nd VNP module 208 were proceeded next computing circulation with CNP module 212 when not surpassing the Preset Time threshold value.In addition, memory addressing memory module 214 is coupled to first memory module 206, and when the probability information of 212 pairs of first memory modules 206 of CNP module is carried out the CNP flow process, provide suitable memory addressing, read or write correct memory location to guarantee to CNP module 212.
Fig. 3 C is the schematic diagram of a submatrix A through rearranging according to an example embodiment of the present invention.Suppose that submatrix A (being submatrix 320) is the part of an IRA-LDPC matrix, it comprises the unit matrix (maybe can be divided into submatrix A1 and A2) of translation (shifted) with the skew of a plurality of reduced sizes, and the per unit matrix has the pattern (Randomly repeated patterns) that repeats at random each other.LDPC decoding device 200 can also comprise a matrix conversion unit 230, in order to submatrix A (comprising capable i, ii, iii, iv, v, vi and row a, b, c, d, e, f) process is rearranged, be converted to the submatrix A ' of the part of another kind of QC-LDPC matrix.
Fig. 3 D is the schematic diagram of a submatrix A through dividing into groups according to another example embodiment of the present invention.Suppose that in addition matrix conversion unit 230 can also be divided into four cell matrixs (block) S1, S2, S3, S4 shown in Fig. 3 D further with submatrix A ' process grouping (grouping).From another angle, cell matrix S1, S2, S3, S4 can be stored by memory cell independently, and, carry out VNP flow process or CNP flow process by a VNP module 204 and the CNP module 212 access memory cell that corresponds to cell matrix S1, S2, S3, S4 respectively.But, Fig. 3 D is illustrated only is the usefulness of signal, in actual LDPC decoding process, submatrix A ' can be grouped into the more junior unit matrix that is different from size 3 * 3, and the needed number memory cells of corresponding submatrix A or submatrix A ' may be tens thousand of or hundreds thousand of.In addition, in order to reduce the hardware cost of LDPC decoding device 200, and under the principle of keeping the parallel processing memory cell, processor unit does not equate with number memory cells.So the processor unit in a VNP module 204, the 2nd VNP module 208 and the CNP module 212 is with the probability information of time in only can the memory cell of processing section.Therefore, the required time of whole LDPC decoding process can improve, but can moderately reduce whole hardware cost and the shared area of circuit in view of the above.
In order to reduce cabling number, cabling complexity or memory cell and other peripheral devices between each memory cell, for example: the cabling complexity between a VNP module 204, the 2nd VNP module 208 and CNP module 212 and the memory cell, and the principle of keeping the part parallel processing, present embodiment is with needed parity matrix in the LDPC decoding process, (this promptly to be divided into first submatrix, submatrix A) with second submatrix (this promptly, submatrix B).In addition, will correspond to the first memory module 206 of the first submatrix A, adopt improvement type (modified) part parallel memory architecture.That is, a plurality of memory cells in the first memory module 206 are suitably divided into groups and connect, to reduce the whole shared area of storage arrangement simultaneously.Thus, can reduce between the memory cell simultaneously, and the cabling complexity between memory cell and other devices of periphery.In addition, with corresponding to the second memory module 210 of the second submatrix B, in different phase, the resequence decoded result of probability information of first memory module 206 of the computing or be used for of being used for decoding.
Fig. 4 is the schematic diagram of the memory architecture 400 handled of a kind of improvement type part parallel that an example embodiment according to the present invention is illustrated.Memory architecture 400 can be used in the first memory module 206.In memory architecture 400, originally the memory cell shown in Fig. 1 C is suitably divided into groups, and the memory cell that is distributed in same group can be connected on together.So the storage arrangement after each series connection (for example, storage arrangement 410 with memory cell 132,134,136 ..., 138 be cascaded) only have one group of input port, it for example comprises: clock pulse port Clock, FPDP Data, addressing port Addr and WE port Wren.In addition, the storage arrangement after each series connection only has one group of output port, and it comprises data-out port Q at least.In view of the above, reduce the port number of memory cell significantly, reduce cabling quantity and complexity between the memory cell, and reduce added burden.Introduced after the memory architecture 400, below will further specify the function of memory addressing memory module 214 with above-mentioned Fig. 3 C, Fig. 3 D and Fig. 4.
The one VNP module 204 and CNP module 212 are handled the probability information of first memory module 206 in turn, and the 2nd VNP module 208 and CNP module 212 are handled the probability information of second memory module 210 in turn.See also Fig. 3 C, Fig. 3 D and Fig. 4, because the probability information of second memory module 210 corresponds to the second submatrix B (all probability information are all on two diagonal 312,314) that has rule and put in order, so second memory module 210 does not need memory addressing memory module 214 that a VNP module 204 or CNP module 212 needed memory locations are provided, only need find a present VNP module 204 or CNP module 212 handled probability information to correspond to the relevant probability information of the second submatrix B, be beneficial to the carrying out of CNP flow process or VNP flow process.But, the probability information of first memory module 206 corresponds to the more erratic first submatrix A, so between a VNP module 204 and CNP module 212, during switch operation, need memory addressing memory module 214 to provide the CNP module 212 needed memory locations.
In general, through rearranging with divide into groups after the first submatrix A, its inner cell matrix for example: cell matrix S1, S2, S3, S4 resequence according to the needed order of a VNP module 204 computings.Can be cascaded carrying out the VNP computing simultaneously so correspond to the memory cell of cell matrix S1, S2, and the memory cell of cell matrix S3, S4 can be cascaded to carry out the VNP computing simultaneously.But switch to CNP module 212 when carrying out the CNP computing by a VNP module 204, check-node between the memory cell of cell matrix S1, S2 order (checknodes ordering) or memory location access sequence may be inequality, and the order of the check-node between the memory cell of cell matrix S3, S4 or memory location access sequence may be inequality.In Fig. 3 D, the memory cell of cell matrix S1, S2 check-node order separately is just identical, is all order according to row i, ii, iii (that is, memory addressing 1,2,3) and reads and write corresponding memory location; Read and write corresponding memory location and the check-node between the memory cell of cell matrix S3 is order according to ii, iii, i (that is, memory addressing 2,3,1) in proper order; Read and write corresponding memory location and the check-node between the memory cell of matrix S 4 is order according to iii, i, ii (that is, memory addressing 3,1,2) in proper order.
Therefore when CNP module 212 is carried out the CNP flow process, need memory addressing memory module 214 to provide needed memory addressing to CNP module 212.Because the first submatrix A is through rearrangement and grouping, each submatrix has the characteristic of cycling element matrix, and the memory location that in fact only needs to provide initial is to CNP module 212.The memory location of supposing not provide initial is to CNP module 212, and the result of last decoding process must be wrong.
Fig. 5 is the flow chart of a kind of LDPC memory using method 500 of being illustrated of an example embodiment according to the present invention.Described LDPC memory using method 500 (being designated hereinafter simply as method 500) is cascaded after memory cell is divided into groups, and also can be described as folding (folding) memory for a person skilled in the art.Method 500 is begun by step S502, in step S502, determines the above-mentioned needed number of memory cells of parity check matrix H computing.In other words, after this promptly calculated parity check matrix H and is divided into the first submatrix A and the second submatrix B, the first submatrix A and the second submatrix B carried out the sum total of the number of VNP flow process and the needed memory cell of CNP flow process.In addition, the first submatrix A is grouped into a plurality of unit matrixs of repeat pattern at random (randomlyrepeated pattern identity matrix), and the part of needed a plurality of memory cells and these at random the repeat pattern unit matrix man-to-man corresponding relation is arranged.After step S502, proceed step S504.
In step S504, VNP flow process or CNP flow process that decision will be carried out together at identical time phase, and will be distributed in different VNP flow process groups or the CNP flow process group in VNP flow process or the CNP flow process that identical time phase carries out.With reference to Fig. 3 D with before described demonstration example, have 2 processing units in the CNP module 212 respectively in the memory cell that corresponds to unit matrix S1, S2 and unit matrix S3, S4, so can divide 2 time phases to carry out the CNP flow process.Or rather, when first time phase, first processing unit of CNP module 212, earlier the memory cell to matrix S 1 carries out the CNP flow process, and second processing unit of CNP module 212, the memory cell of matrix S 3 is carried out the CNP flow process with the time.When second time phase, first processing unit of CNP module 212 carries out the CNP flow process to the memory cell of matrix S 2, and second processing unit of CNP module 212, the memory cell of matrix S 4 is carried out the CNP flow process with the time.Yet, the present invention is not limited to this, in other example embodiment of the present invention, CNP module 212 can comprise above 2 processing units, the first submatrix A can comprise above 4 submatrixs, and the group's total number that is grouped can surpass 2, and CNP module 212 also can be handled the probability information in the memory cell of same group one by one in surpassing 2 time phases.After step S504, proceed step S506.
In step S506,, determine the memory location access sequence of each memory cell according to VNP flow process of carrying out or CNP flow process at identical time phase.The memory location access sequence of memory cell thus, can obtain the initial access site of memory cell, and behind the serial memory unit, can store in the memory addressing memory module 214, between in due course, offer a VNP module 204 or CNP module 212.After step S506, proceed step S508.
In step S508, come the folding factor (folding factor) of selection memory according to the data throughout (Data throughput) of expection.In general, data throughout can be weighed with the LDPC bit quantity of being decoded in each frame period, that is the unit is bits per second (bits/second) or every framing bit number (bits/frame).In addition, the performed soft-decision cycle-index of LDPC decoding process is many more, and then decoded result is correct more.But folding factor of every increase, decoding VNP flow process or CNP flow process in the computing just needs many time phases, but relatively needed processing unit can reduce, and the cabling complexity of memory cell also can reduce simultaneously.So this step S508 need make a trade-off (tradeoff) according to the needs of practical wireless communication systems in data throughout and cabling feasibility (routibility).After step S508, proceed step S510.
In step S510,, memory cell is connected into a plurality of parallel processing memory modules according to folding factor and the VNP flow process group or the CNP flow process group that are distributed.In other words, be dispensed on that pairing memory cell can be connected on together in the same group.After the memory cell series connection, each parallel processing memory module only has first memory cell to comprise an input port group, and only has last memory cell to comprise an output port group.In addition, each memory cell is in order to probability information of access, each memory cell is circulated to carry out a computing by VNP flow process and the access of CNP flow process, and all finish a computing circulation time in pairing each memory cell of parity matrix, decode procedure is just finished a decode cycle.After step S510, finish entire method 500.The order of each step is not in order to restriction the present invention among Fig. 5, can carry out the step of part simultaneously yet.In addition, the memory architecture that the first memory module in the LDPC decoding device 200 of Fig. 2 206 and second memory module 210 can 500 construction of using method.Introduced after the LDPC memory using method 500, introduced a kind of LDPC coding/decoding method hereinafter with reference to Fig. 2 and Fig. 6.
Fig. 6 is the flow chart of a kind of LDPC coding/decoding method 600 of being illustrated of an example embodiment according to the present invention.Please be simultaneously with reference to Fig. 2 and Fig. 6, in this example embodiment, described LDPC coding/decoding method 600, S602 begins by step, in step S602, LDPC coding/decoding method 600 with the pairing probability information temporary storage of the first submatrix A of parity check matrix H to first memory module 206, and simultaneously with the pairing probability information temporary storage of the second submatrix B of parity check matrix H to second memory module 210.In addition, the first submatrix A is grouped into a plurality of unit matrixs of repeat pattern at random.First memory module 206 comprise a plurality of memory cells with these at random the repeat pattern unit matrix man-to-man one corresponding relation is arranged.After step S602, proceed step S604.
Then, in step S604,600 pairs of first memory modules of LDPC coding/decoding method 206 are carried out VNP flow process or CNP flow process with the probability information in the second memory module 210.After the step S604, proceed step S606.In step S606, LDPC coding/decoding method 600 judges whether the probability information in first memory module 206 and the second memory module 210 satisfies the decoding end condition, and this promptly satisfies the situation of aforesaid equation (1).If satisfy the decoding end condition, then after step S606, proceed step S608.If do not satisfy the decoding end condition, then after step S606, proceed step S610.
In step S608, LDPC coding/decoding method 600 confirms whether to have reached the Preset Time threshold value.In general, above-mentioned Preset Time threshold value can be set at a frame period.But the present invention is defined in aforesaid way, can also select the Preset Time threshold value that is fit to according to the needs of wireless communication system.If then after step S608, proceed step S610.If not, then after step S610, return and carry out step S604.In step S610, LDPC coding/decoding method 600 is converted to the LDPC dateout with the probability information via hard decision of first memory module 206, and by 210 rearrangements of second memory module.This promptly, obtained LDPC dateout after the probability information translation of second memory module 210 rearrangement by first memory module 206.Then, export the LDPC dateout after the rearrangement to next stage, for example source decoding (source decoding) stage.After step S610, finish whole LDPC coding/decoding method 600.The order that is noted that each step of Fig. 6 is not in order to restriction the present invention, can carry out the step of part simultaneously yet.
Fig. 7 is the system block diagrams of the another kind of LDPC decoding device 700 that illustrates according to another example embodiment of the present invention.LDPC decoding device 700 is similar with the LDPC decoding device 200 of Fig. 2 haply, but comprises that first handles network (dealernetwork) unit 742, second and handle network element the 744, the 3rd and handle network element 746 and the and manage network element 748 everywhere.The first processing network element 742 and second is handled network element 744 and is coupled to separately between a VNP module 204 and the first memory module 206.The 3rd handles network element 746 and the manages network element 748 everywhere and is coupled to separately between the 2nd VNP module 208 and the first memory module 210.First handles network element 742, second handles network element the 744, the 3rd and handles network element 746 and the and manage network element 748 everywhere in LDPC decoding device 700, and the co-ordination of different code checks (code rate) is provided.For example, in the DVB-S2 standard, the LDPC decoding device need be handled the LDPC coding of about 11 kinds of different code checks, and the pairing parity matrix of each code check is neither identical.If do not having suitable adjustment to read or write the mode of probability information between a VNP module 204 and the first memory module 206 or between the 2nd VNP module 208 and the first memory module 210, then when changing, can cause code check LDPC decoded result mistake.
In this example embodiment, first handles network element 742, second handles network element the 744, the 3rd and handles network element 746 and the and manage network element 748 everywhere and can realize with multiplexer (multiplexer) separately.But the present invention is not limited thereto, and in other example embodiment of the present invention, first handles network element 742, second handles network element the 744, the 3rd and handle network element 746 and the and manage network element 748 everywhere and can realize with other modes separately.In addition, the memory architecture that the first memory module in the LDPC decoding device 700 of Fig. 7 206 and second memory module 210 can 500 construction of using method.
In sum, a plurality of example embodiment of the present invention provides memory application method, LDPC coding/decoding method and the device thereof of LDPC.The memory application method of LDPC is to use in the decoding process of LDPC, and the parity matrix that it is required with decoding LDPC is divided into first submatrix and second submatrix.At the first memory module that corresponds to first submatrix, adopt improvement type (modified) part parallel memory architecture, a plurality of memory cells are suitably divided into groups and connect, reducing shared area of storage arrangement and added burden simultaneously, and reduce between the memory cell, other cabling complexities between installing of memory cell and periphery.In addition, will correspond to the second memory module of second submatrix, the resequence decoded result of probability information of first memory module of the computing or be used for of being used for decoding in different phase is to improve the memory service efficiency.
Though disclosed example embodiment of the present invention; but it is not in order to limit embodiment of the present invention; any those skilled in the art are under the situation of the spirit and scope that do not break away from the embodiment that is disclosed; can carry out some and change and retouching, so protection range should be as the criterion with claims institute restricted portion.
Claims (26)
1. the memory using method of a low density parity check code is applicable to comprise the decode procedure of radio receiver:
Determine in this decode procedure one or more variable node flow process or one or more check-node flow process that will carry out together at an identical time phase;
To be distributed in different variable node flow process groups or the check-node flow process group in this variable node flow process or this check-node flow process that this identical time phase carries out;
Select a folding factor of described memory cell according to an anticipatory data throughput; And
According to this folding factor and this variable node flow process group or this check-node flow process group that are distributed, described memory cell is connected into a plurality of parallel processing memory modules.
2. the memory using method of low density parity check code according to claim 1 also comprises:
Determine a sum of a plurality of memory cells that a parity matrix computing in this decode procedure is required; And
According to this variable node flow process of carrying out or this check-node flow process, determine a memory location access sequence of each memory cell at this identical time phase.
3. the memory using method of low density parity check code according to claim 1, wherein each parallel processing memory module only has a first memory unit to comprise an input port group, and only has a last memory cell to comprise an output port group.
4. the memory using method of low density parity check code according to claim 2 determines that wherein this sum of a plurality of memory cells that this parity matrix computing is required is further comprising the steps of:
This parity matrix is converted to circular matrix surely;
Should be divided into one first submatrix and one second submatrix by accurate circular matrix, wherein this second submatrix is a square matrix, and this second submatrix comprises two diagonal, and all comprises a numerical value " 1 " on this two diagonal; And
This first submatrix is grouped into a plurality of unit matrixs of repeat pattern at random, and wherein, the part of described memory cell has man-to-man one corresponding relation with the described unit matrix of repeat pattern at random.
5. the memory using method of low density parity check code according to claim 2, wherein the numerical value of this folding factor is big more, then the included described memory cell of each parallel processing memory module is many more, the cabling complexity of described memory cell is low more, and resulting actual data throughput is low more.
6. the memory using method of low density parity check code according to claim 1, wherein each memory cell is in order to access one probability information; Each memory cell is circulated to carry out a computing by this variable node flow process or this check-node flow process access; And on pairing each memory cell of this parity matrix, all finish this computing circulation time, this decode procedure is finished a decode cycle.
7. a decoding method of low density parity check codes is applicable to the decode procedure in the radio receiver, and this decoding method of low density parity check codes comprises:
To in the first memory module with a second memory module in probability information carry out a variable node flow process or a check-node flow process;
Judge in this first memory module with this second memory module in probability information whether satisfy a decoding end condition;
Probability information via one hard decision of this first memory module is converted to a low density parity check code dateout, and carries out a rearrangement by this second memory module.
8. decoding method of low density parity check codes according to claim 7 wherein in this decode procedure, uses a parity matrix to come related this variable node flow process or this check-node flow process, and this decoding method of low density parity check codes also comprises:
This parity matrix is divided into one first submatrix and one second submatrix; And
With the pairing probability information of this first submatrix and the pairing probability information of this second submatrix temporary respectively to the first memory module with a second memory module in.
9. decoding method of low density parity check codes according to claim 7, wherein should decoding end condition be in this first memory module with this second memory module in the condition of the following equation of probability information conforms (1):
VH
T=0 ... equation (1)
Wherein, v is a vector, the low density parity check code input that its representative is received, or the low density parity check code code word of representative through being received after the wireless transmission, and H
TTransposed matrix for needed this parity check matrix H in this decode procedure.
10. decoding method of low density parity check codes according to claim 7 also comprises:
Confirm whether reached a Preset Time threshold value, wherein,
If not, then return in this first memory module with this second memory module in probability information carry out this variable node flow process or this check-node flow process; And
If this hard decision of probability information via of this first memory module is converted to this low density parity check code dateout, and carries out this rearrangement by this second memory module.
11. decoding method of low density parity check codes according to claim 10, wherein this Preset Time threshold value is a frame period.
12. decoding method of low density parity check codes according to claim 7 also comprises:
In computing circulation, in this first memory module with this second memory module in whole probability information carry out this variable node flow process and this check-node flow process;
After probability information in this first memory module carried out this variable node flow process, one first operation result of this variable node flow process is kept in back in this first memory module, carry out this check-node flow process again; And
After probability information in this second memory module carried out this variable node flow process, one second operation result of this variable node flow process is kept in back in this second memory module, carry out this check-node flow process again.
13. decoding method of low density parity check codes according to claim 8 is after being divided into this parity matrix this first submatrix and this second submatrix, this decoding method of low density parity check codes also comprises:
This first submatrix is grouped into a plurality of unit matrixs of repeat pattern at random, comprises in this first memory module that wherein a plurality of memory cells have man-to-man one corresponding relation with the described unit matrix of repeat pattern at random.
14. decoding method of low density parity check codes according to claim 7, wherein this second submatrix is a unit matrix, and it comprises that two cornerwise numerical value are all " 1 ", and between this two diagonal a constant offset is arranged.
15. decoding method of low density parity check codes according to claim 7, wherein a plurality of memory cells of first memory module have a part of parallel processing framework.
16. a decoding low-density parity-check (ldpc) code device is applicable to the decode procedure in the radio receiver, this decoding low-density parity-check (ldpc) code device comprises:
One variable node is handled (VNP) module, in order to in the first memory module with a second memory module in probability information carry out a variable node flow process;
One code check node processing (CNP) module, in order to in the first memory module with a second memory module in probability information carry out a check-node flow process;
One computing stops judge module, in order to judge in this first memory module with this second memory module in probability information whether satisfy a decoding end condition;
One two-way amplitude limiter is converted to a low density parity check code dateout in order to probability information via one hard decision with this first memory module, and carries out a rearrangement by this second memory module.
17. decoding low-density parity-check (ldpc) code device according to claim 16 wherein when this low density parity check code of decoding, uses this parity matrix to come related this variable node flow process or this check-node flow process.
18. decoding low-density parity-check (ldpc) code device according to claim 17, wherein should decoding end condition be in this first memory module with this second memory module in the condition of the following equation of probability information conforms (1):
VH
T=0 ... equation (1)
Wherein, v is a vector, the low density parity check code input that its representative is received, or the low density parity check code code word of representative through being received after the wireless transmission, and H
TWhen decoding this low density parity check code, the transposed matrix of a needed parity check matrix H.
19. decoding low-density parity-check (ldpc) code device according to claim 17 also comprises:
One control module, in order to confirm whether reached a Preset Time threshold value, wherein,
If not, then this control module notify this variable node processing module and this code check node processing module continue in this first memory module with this second memory module in probability information carry out this variable node flow process or this check-node flow process; And
If then this control module notifies this slicer that this hard decision of probability information via of this first memory module is converted to this low density parity check code dateout, and carries out this rearrangement by this second memory module.
20. decoding low-density parity-check (ldpc) code device according to claim 19, wherein this Preset Time threshold value is a frame period.
21. decoding low-density parity-check (ldpc) code device according to claim 17, wherein,
In computing circulation, this variable node processing module and this code check node processing module in this first memory module with this second memory module in whole probability information carry out this variable node flow process and this check-node flow process;
After this variable node processing module is carried out this variable node flow process to the probability information in this first memory module, one first operation result of this variable node flow process is kept in back in this first memory module, carry out this check-node flow process by this code check node processing module again; And
After this variable node processing module is carried out this variable node flow process to the probability information in this second memory module, one second operation result of this variable node flow process is kept in back in this second memory module, carry out this check-node flow process by this code check node processing module again.
22. decoding low-density parity-check (ldpc) code device according to claim 17 also comprises:
One matrix conversion unit in order to this parity matrix being divided into one first submatrix and one second submatrix, and is grouped into a plurality of unit matrixs of repeat pattern at random with this first submatrix; And
This variable node processing module and this code check node processing module with the pairing probability information of this first submatrix and the pairing probability information of this second submatrix temporary respectively to the first memory module with a second memory module in, comprise in this first memory module that wherein a plurality of memory cells have man-to-man one corresponding relation with the described unit matrix of repeat pattern at random.
23. decoding low-density parity-check (ldpc) code device according to claim 17, wherein this second submatrix is a unit matrix, and it comprises that two cornerwise numerical value are all " 1 ", and between this two diagonal a constant offset is arranged.
24. also comprise according to claim 17 a described decoding low-density parity-check (ldpc) code device:
One memory addressing memory module, in order to when this code check node processing module is carried out this check-node flow process to the probability information in this first memory module, the initial memory location that each memory cell in this first memory module is provided is to this code check node processing module, and a wherein said memory cell memory location access sequence separately is inequality.
25. decoding low-density parity-check (ldpc) code device according to claim 17, wherein a plurality of memory cells of this first memory module have a part of parallel processing framework, and comprise multi-set parallel processing memory module.
26. decoding low-density parity-check (ldpc) code device according to claim 16, wherein the first memory unit in each group parallel processing memory module of this first memory module comprises an input port group, and a last memory cell comprises an output port group.
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| CN105262493A (en) * | 2015-11-17 | 2016-01-20 | 中国人民解放军92728部队 | Decoding method of low-density parity check codes |
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