CN102156628A - Microprocessor and hierarchical memory method of prefetching data to cache memory of microprocessor - Google Patents
Microprocessor and hierarchical memory method of prefetching data to cache memory of microprocessor Download PDFInfo
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- CN102156628A CN102156628A CN2011100948091A CN201110094809A CN102156628A CN 102156628 A CN102156628 A CN 102156628A CN 2011100948091 A CN2011100948091 A CN 2011100948091A CN 201110094809 A CN201110094809 A CN 201110094809A CN 102156628 A CN102156628 A CN 102156628A
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Abstract
Disclosed are a microprocessor and a hierarchical memory method of prefetching data to a cache memory of the microprocessor. The microprocessor comprises first and second cache memories belonging to different levels, and the second cache memory is at a lower level than the first cache memory. The microprocessor also comprises a data prefetching device which monitors load operation, records the load operation of the current prefetching row as the latest history, and determines whether the latest history has an obvious direction. If the latest history has an obvious direction, the data prefetching device prefetches one or more cache row to the first cache memory; otherwise, the data prefetching device prefetches one or more cache row to the second cache memory. The data prefetching device determines whether the load operation of the latest history has a large data bulk. When other conditions remain unchanged, a lot of cache rows are prefetched when the data bulk is great. And, the data prefetching device determines whether the load operation of the latest history occurs in a continuous clock cycle. The invention also provides an extra prefetching mode.
Description
Technical field
The present invention is relevant with microprocessor (microprocessors) field, and is particularly to data pre-fetching (data prefetching) technology of microprocessor.
Background technology
The Core of Intel microprocessor architecture design (microarchitecture) is realized a hardware prefetch technology (hardware prefetcher, be relevant to data and get unit prefetcher/Data Cache Unit Prefetcher soon), in order to the ground floor data memory cache (L1D cache) of looking ahead.Get the pattern (pattern) of the content of row (cache line) soon by discerning one, data are got the unit prefetcher soon and are looked ahead and continue and come next bar to get row soon to this ground floor data memory cache.If each continues to be written into and corresponds to the address low than each previous address, previously mentioned the continuing of then looking ahead got row soon.
Summary of the invention
One embodiment of the present invention provides a microprocessor.This microprocessor comprises one first and one second memory cache, belongs to the different levels of this microprocessor one memory cache stratum, and wherein, the level of above-mentioned second memory cache in this memory cache stratum is lower than this first memory cache.This microprocessor also comprises that one is written into the unit, in order to receive the operation that is written into about a storer.This microprocessor comprises a data pre-fetching device, is coupled to above-mentioned first and second memory cache.This data pre-fetching device is used to monitor the above-mentioned operation that is written into, and will be a recent history about the operation note that is written into of getting row at present soon.This data pre-fetching device is used to also judge whether this recent history shows that the operation that is written into of getting row at present soon has a specific direction.If this recent history display has the existence of above-mentioned specific direction, this data pre-fetching device is looked ahead and one or more is got row soon to this first memory cache.If this recent history display is supreme states true direction existence clearly, this data pre-fetching device is looked ahead and one or more is got row soon to this second memory cache.
Another embodiment of the present invention then discloses a kind of method, be used for the memory cache stratum of prefetch data to microprocessor, wherein this memory cache stratum comprises one first memory cache and one second memory cache, above-mentioned first and second memory cache adheres to the different levels of this memory cache stratum separately, and the level of this second memory cache is lower than this first memory cache.This method comprises that one of this microprocessor of monitoring is written into the operation that is written into about a storer that the unit receives, and will be a recent history about the operation note that is written into of getting row at present soon.This method also comprises judges whether this recent history shows that the operation that is written into of getting row at present soon has a specific direction.When this recent history display had above-mentioned specific direction, disclosed method comprises looking ahead one or more got row soon to this first memory cache.When this recent history did not show above-mentioned specific direction, disclosed method comprises looking ahead one or more got row soon to this second memory cache.
The present invention can provide extra prefetch mode with respect to prior art.
Description of drawings
Fig. 1 diagram one calcspar is described the disclosed a kind of microprocessor of the present invention, wherein has a data pre-fetching device;
Fig. 2 is a process flow diagram, describes the operation of Fig. 1 microprocessor;
Fig. 3 is a calcspar, describes the disclosed another kind of microprocessor of the present invention, wherein has a data pre-fetching device;
Fig. 4 is a process flow diagram, and how the data pre-fetching device of describing Fig. 3 embodiment realizes the operation of step 204 among Fig. 2.
Being simply described as follows of symbol in the accompanying drawing:
100: microprocessor; 102: the instruction memory cache;
112: the instruction transfer interpreter; 116: the working storage alias table;
118: reservation station; 122: be written into the unit;
126: Bus Interface Unit; 132: ground floor data memory cache;
134: second layer memory cache;
136: the data pre-fetching device; 142: historical formation;
144: thin of historical record; 146: steering logic;
148: the clock pulse counter; 152: the address field;
154: the size field; 156: the continuity field;
158: the directivity field; 162: get column counter soon;
164: up-to-date previous clock pulse;
304: minimum pointer; 306: the highest pointer;
308: minimum pointer change counter; 312: the highest pointer change counter.
Embodiment
The present invention narrates a data pre-fetching device, gets the unit prefetcher soon with the data of Intel and compares, and the disclosed data pre-fetching device of the present invention also provides extra prefetch mode.The first, disclosed data pre-fetching device will consider whether have the clear and definite direction (clear load direction) that is written into; If uncertain have the clear and definite direction that is written into to exist, then with data pre-fetching to second layer memory cache (L2) but not ground floor data memory cache (L1D).The second, disclosed data pre-fetching device will be judged the same time interval that is written into of getting row soon.If spacing lacks (for example, taking place in the cycle in continuous clock pulse), data pre-fetching device a fairly large number of row (comparing) of getting soon of can looking ahead with other situations.The 3rd, disclosed data pre-fetching device can be observed the described data volume that is written into.If data volume is quite big, data pre-fetching device a fairly large number of row (comparing) of getting soon of can looking ahead then with other situations.
Consult Fig. 1, it provides a calcspar, describes according to the disclosed microprocessor 100 of one embodiment of the present invention, has a data pre-fetching device 136 in the microprocessor 100.This microprocessor 100 comprises an instruction memory cache (instruction cache) 102; This instruction memory cache 102 couples an instruction transfer interpreter (instruction translator) 112; This instruction transfer interpreter 112 couples a working storage alias table (registeralias table, RAT) 116; This working storage alias table 116 couples a reservation station (reservation stations) 118; And described reservation station 118 couples one and is written into unit (load unit) 122.Described reservation station 118 issuing commands are written into unit 122 (or to other performance elements, not being shown among the figure) to this, make it to be able to the escape procedure order and carry out.One retirement unit (retire unit does not show in the drawings) comprises a record buffer (recorder buffer), comes instruction retired in order to the foundation procedure order.The described unit 122 that is written into is from a ground floor data memory cache (L1D cache) 132 reading of data.One second layer memory cache (L2cache) is supported this ground floor data memory cache 132 and this instruction memory cache 102.This second layer memory cache 134 is by a Bus Interface Unit (bus interface unit) 126 reading and writing system storages (system memory); This Bus Interface Unit 126 is the interface of this microprocessor 100 and a bus (bus, for example local bus local bus or memory bus memory bus).Microprocessor 100 also comprises a data pre-fetching device 136, or claims a pre-fetch unit prefetch unit, in order to from the system storage prefetch data to second layer memory cache 134 and ground floor data memory cache 132, below go through its content.
Data pre-fetching device 136 comprises a steering logic 146.This steering logic 146 couples and controls a historical formation (history queue) 142, and gets column counter (cache line counter) 162, one clock pulse counter (clock cycle counter) 148 and one up-to-date previous clock pulse working storage (most recent previous clock cycle register) 164 soon.Historical formation 142 with thin (entries) 144 of historical record with formation mode record.Thin 144 of each historical record comprises an address field (an address field) 152, one size field (a size field) 154, one continuity field (a consecutive filed) 156 and one directivity field (a direction field) 158.Address field 152 stores that thin 144 of pairing historical record put down in writing be written into operation (load operation) be written into address (load address).Size field 154 stores this and is written into the size (byte quantity) of operation.156 signs of continuity field received by this data pre-fetching device 136 this be written into operation and whether be positioned at the consecutive hours arteries and veins cycle with the previous the last operation that is written into that takes place.158 of directivity fields show that this is written into operation with respect to the previous the last direction that is written into operation that takes place.
Begin to follow the trail of the access of getting row soon at present from this data pre-fetching device 136, this gets the total quantity that is written into operation of row soon to get column counter 162 countings soon, and the step 204 in the following corresponding diagram 2 is discussed.Clock pulse counter 148 is with the clock pulse increment of microprocessor 100.Therefore, when step 204 processing one is written into operation, the sampling result of 146 pairs of these clock pulse counters 148 of this steering logic can be used to indicate that to be written into operation with respect to other new these that are written into operation instantly be to be received in which in clock pulse cycle, and, be used in particular for judging whether this is written into operation is to be received in the cycle at the last continuous clock pulse that is written into after operation receives, to set the continuity field 156 in the thin item 144 of historical record.Below the function of clock pulse counter 148 and up-to-date previous clock pulse working storage 164 further is discussed in Fig. 2.
Consult Fig. 2, it is with the operation of flow chart description Fig. 1 microprocessor 100.This flow process starts from step 202.
In step 202, the new operation that is written into is passed to ground floor data memory cache 132 from being written into unit 122.This is written into operation and clearly indicates one to be written into the address, and the address of data in storer of being desired to be written into indication institute in addition, is written into operation and also clearly indicates the size of desiring the data that are written into to some extent, for example, and 1,2,4,8 or 16 bytes.Process flow diagram is then come step 204.
In step 204, data pre-fetching device 136 is spied on this ground floor data memory cache 132, with detect this time new be written into operation with and relevant information.According to the detecting result, data pre-fetching device 136 is in historical formation 142 configurations and insert thin 144 of a historical record.Particularly, this steering logic 146 is inserted the above-mentioned address that is written at address field 152, and inserts the size that is written into data at size field 154.In addition, steering logic 146 reads the value of this clock pulse counter 148 and this up-to-date previous clock pulse working storage 164, and compares.If the value of the more up-to-date previous clock pulse working storage 164 of value that clock pulse counter 148 is present many 1, steering logic 146 can 156 indication new being written into this time of setting continuity field be operating as generation in the continuous clock pulse cycle that before once is written into operation, otherwise, steering logic 146 can be removed the content of this continuity field 156, and operating with this time new being written into of indication is not that the continuous clock pulse that formerly once is written into operation took place in the cycle.In another embodiment, steering logic 146 is to set these continuity field 156 indications to be written into and to be operating as continuous clock pulse and to take place in the cycle when many N of value of the present more up-to-date previous clock pulse working storage 164 of value of clock pulse counter 148, and wherein, N is a preset value; Otherwise steering logic 146 can be removed this continuity field 156.In one embodiment, the N value is 2.Yet preset value N is a design parameter, can set based on multiple parameter, for example ground floor data memory cache 132 with and/or the size of second layer memory cache 134.In one embodiment, this preset value N can (model specified register MSR) sets via the peculiar working storage of the model of microprocessor 100.After the content that reads up-to-date previous clock pulse working storage 164, steering logic 146 can be used for its value that is read from clock pulse counter 148 to upgrade the content of up-to-date previous clock pulse working storage 164.In addition, steering logic 146 can be with these new up-to-date address field 152 comparisons that once before had been written into operation that address and historical formation 142 are write down that are written into that are written into operation, and fill in the new directivity field 158 that is written into operation this time according to this, with indication this time new be written into operation with respect to the up-to-date direction that once before had been written into operation.In addition, steering logic can indicate the thin item 144 of this historical record for effective by the significance bit (valid bit) in the thin item 144 of setting historical record.In addition, steering logic 146 is gone back increment this is got column counter 162 soon.In addition, in configuration, fill in and thin 144 of historical record that validation disposed and increment before this gets column counter 162 soon, steering logic 146 can judge that this time new positions that are written into the address that are written into operation are whether with other are written into operation and are positioned at the same row of getting soon in the historical formation 142; If not then steering logic 146 makes thin 144 of all historical record in the historical formation 142 for invalid, beginning carrying out record, and remove the value that this gets column counter 162 soon for these new related new row of getting soon of operation that are written into.Fig. 2 flow process then enters next step 206.
In step 206, related one in the row of getting soon of operation that are written into that 136 identifications of data pre-fetching device are this time new are written into access pattern (load access pattern).In one embodiment, prefetcher 136 identification when getting column counter 162 (in step 204 increment) more than or equal to a preset value P is soon got one in the row at present soon and is written into the access pattern.In one embodiment, the P value is 4.Yet preset value P is a design parameter, can determine based on multiple factor, for example, ground floor data memory cache 132 with and/or the size of second layer memory cache 134.In one embodiment, preset value P can utilize the peculiar working storage of the model of microprocessor (model specified register MSR) sets.In addition, also can otherwise detect and at present get one in the row soon and be written into the access pattern.Fig. 2 flow process then enters step 208.
In step 208, data pre-fetching device 136 judges that this is written into the access pattern and whether has clear and definite direction.In one embodiment, if the directivity field 158 of the thin item 144 of the up-to-date historical record that is written into operation at least for D time shows same direction, then data pre-fetching device 136 can be judged has specific direction to exist, and wherein D is a preset value.In one embodiment, preset value D is 3.Yet preset value D is a design parameter, can be based on various factors, for example ground floor data memory cache 132 with and/or the size of second layer memory cache 134, and adjust.In one embodiment, preset value D can utilize the peculiar working storage of a model (MSR) of microprocessor 100 to set.Another kind of available embodiment will wherein adopt another mode to judge whether that specific direction exists in following Fig. 3 discussion.Have a specific direction to exist if data pre-fetching device 136 is judged, Fig. 2 process flow diagram enters determining step 218; Otherwise, then enter another determining step 212.
In determining step 212, data pre-fetching device 136 judges whether the data volume that is written into operation of getting row at present soon is excessive.In one embodiment, if the effective statistical result showed of the size field 154 of thin 144 of historical record, relevantly be written into operation and have data volume Y at least altogether, then data pre-fetching device 136 can judge that described being written into be operating as big data quantity, and wherein Y is a preset value.In one embodiment, preset value Y is 8 bytes.Yet preset value Y is a design parameter, can be based on multiple factor, for example ground floor data memory cache 132 with and/or the size of second layer memory cache 134, and determine.In one embodiment, preset value Y can utilize the peculiar working storage of a model (MSR) of microprocessor 100 to set.In another embodiment, data pre-fetching device 136 can when being written in the operation great majority and having at least data volume Y, judge that described being written into is operating as big data quantity in described; The employing means are: follow the trail of big data quantity with two counters and be written into operation, be written into the quantity of operation with non-big data quantity, and compare than; Can carry out it in step 204.If described being written into is operating as big data quantity, then Fig. 2 flow process enters step 214; Otherwise Fig. 2 flow process enters step 216.
In step 214, data pre-fetching device 136 look ahead continue after two get soon and be listed as to second layer memory cache 134.Because determining step 208 do not have specific direction, data pre-fetching device 136 prefetch datas are to second layer memory cache 134 but not ground floor data memory cache 132; Reason is, it is inessential that the data of looking ahead have bigger chance, and therefore, data pre-fetching device 136 is not inclined to the potential data that may use are positioned over ground floor data memory cache 132.Fig. 2 flow process finishes in step 214.
In step 216, data pre-fetching device 136 only look ahead continue after one get soon and be listed as to second layer memory cache 134.Fig. 2 flow process finishes in step 216.
In determining step 218, data pre-fetching device 136 judges whether be at continuous clock pulse cycle in be received with getting at present relevant described of row soon if being written into operation.If be written into is to be received in the cycle at continuous clock pulse, then representation program is just with the speed swept memory that is exceedingly fast, therefore data pre-fetching device 136 more data of must looking ahead, to take the lead the speed that program is carried out, for example, before program is asked, in ground floor data memory cache 132, prepare follow-up data of getting row soon in advance.In one embodiment, if all be labeled about the up-to-date continuity field 156 that is written into the thin item 144 of historical record of operation at least for C time of getting at present row soon, then data pre-fetching device 136 can learn that described to be written into operation be to be received in the cycle at continuous clock pulse, and wherein C is a preset value.In one embodiment, preset value C is 3, yet preset value C is a design parameter, can be based on various factors, for example ground floor data memory cache 132 with and/or the size of second layer memory cache 134, and determine.In one embodiment, preset value C can set by the peculiar working storage of a model (MSR) of microprocessor 100.Take place if be loaded in the continuous clock pulse cycle, Fig. 2 flow process enters determining step 232; Otherwise then flow process enters determining step 222.
In determining step 222, data pre-fetching device 136 judge about get at present row soon whether described to be written into operation be big data quantity; Detailed technology and above-mentioned determining step 212 are similar.If big data quantity, Fig. 2 flow process enters step 224; Otherwise flow process enters step 226.
In step 224, the specific direction that data pre-fetching device 136 follows step 208 to judge, two of continuing of looking ahead get soon and are listed as to ground floor data memory cache 132.Have specific direction to exist because determining step 208 is judged, data pre-fetching device 136 can be with data pre-fetching to ground floor data memory cache 132 but not second layer memory cache 134; Reason is, the data of looking ahead very likely are used really, and the data that prefetcher 136 can tendency might be used are placed on ground floor data memory cache 132.Fig. 2 flow process ends at step 224.
In step 226, look ahead of continuing gets and is listed as to ground floor data memory cache 132 specific direction that data pre-fetching device 136 can follow step 208 to judge soon.Fig. 2 flow process ends at step 226.
In determining step 232, data pre-fetching device 136 can judge whether get at present row soon described is written into operation is big data quantity; Detailed content and aforementioned determining step 212 content class are seemingly.Be big data quantity if be written into, Fig. 2 flow process enters step 234; Otherwise Fig. 2 flow process enters step 236.
In step 234, look ahead three of continuing get and are listed as to ground floor data memory cache 132 specific direction that data pre-fetching device 136 can follow step 208 to judge soon.Fig. 2 flow process ends at step 234.
In step 236, look ahead two of continuing get and are listed as to ground floor data memory cache 132 specific direction that data pre-fetching device 136 can follow step 208 to judge soon.Fig. 2 flow process ends at step 236.
Fig. 3 technology then is discussed, and it describes the microprocessor 100 that another embodiment of the present invention is realized with calcspar, and this microprocessor 100 has a data pre-fetching device 136.The data pre-fetching device 136 that data pre-fetching device 136 and Fig. 1 of Fig. 3 are introduced is similar, and also operates in the mode of similar Fig. 2, and the difference of two kinds of embodiments below is discussed.Judge that about the specific direction that historical record upgrades and determining step 208 is done that step 204 among Fig. 2 is done Fig. 3 data pre-fetching device 136 has does following the adjustment.In Fig. 3 embodiment, thin 144 of the historical record of historical formation 142 do not comprise directivity field 158.In addition, data pre-fetching device 136 comprises a minimum pointer working storage (min pointer register) 304 and one the highest pointer working storage (max pointer register) 306, by steering logic 146 control, point to respectively to get soon at present in the row and begin to follow the trail of read that the back taken place minimum of getting row at present soon and location variable superlatively from data pre-fetching device 136.Data pre-fetching device 136 also comprises a minimum pointer change counter 308 and the highest pointer change counter 312, in order to begin from data pre-fetching device 136 to follow the trail of get the reading of row at present soon after, count the change frequency of above-mentioned minimum pointer working storage 304 and the highest pointer working storage 306 respectively.Below discuss as how the disclosed embodiment of Fig. 3 realize described data pre-fetching device 136 operations of step 204 among Fig. 2.By whether judging difference between above-mentioned minimum pointer change counter 308 and the highest pointer change counter 312 greater than a preset value, steering logic 146 has judged whether that a specific direction exists.In one embodiment, this preset value is 1; Yet this preset value is a design parameter, can be based on multiple parameter, for example ground floor data memory cache 132 with and/or the size of second layer memory cache 134, and determine.In one embodiment, this preset value can utilize the peculiar working storage of model (MSR) of microprocessor 100 to set.If the value of this minimum pointer change counter 308 exceeds more than the above-mentioned preset value than the value of this highest pointer change counter 312, judge that then the specific direction of coming out is for downwards; If the value of this highest pointer change counter 312 value of this minimum pointer change counter 308 exceeds more than the above-mentioned preset value, judge that then the specific direction of coming out is for making progress; Remaining situation, then judging does not have specific direction.In addition, if this new address that is written into that is written into operation put down in writing other and is written into operation and points to same row, then steering logic 146 the highest pointer change counter 312 of removing and the minimum variation pointer counters 308 got soon with historical formation 142.
With reference now to Fig. 4,, how it realizes the action of step 204 among Fig. 2 with the data pre-fetching device 136 of flow chart description Fig. 3 embodiment.Fig. 4 flow process arises from step 404.
Whether at determining step 404, steering logic 146 is judged the new up-to-date address deviator that is written into of getting row soon before the address, particularly feeling the pulse with the finger-tip that is written into, greater than the value of the highest pointer working storage 306.If then flow process enters step 406; All the other situations, then flow process enters determining step 408.
In step 406, steering logic 146 is upgraded the highest pointer working storage 306 with the new address deviator that is written into, and this highest pointer change counter 312 of increment.In this case, Fig. 4 flow process ends at step 406.
At determining step 408, steering logic 146 judges that get row at present soon up-to-date is written into the value whether the address deviator is less than minimum pointer working storage 304.If Fig. 4 flow process enters step 412; If other situations then finish Fig. 4 flow process.
In step 412, steering logic 146 is upgraded minimum pointer working storage 304 with the up-to-date address deviator that is written into, and this minimum pointer change counter 308 of increment.Fig. 4 flow process also finishes in step 412.
Although above embodiment mainly discusses and is written into operation, in other embodiments, also disclosed prefetching technique can be done suitably improvement, to be applied in the store operation (store operations).
Though above narration numerous embodiments of the present invention, what must state is that foregoing is the certain applications example of present technique, is not to be used for limiting scope of the present invention.Those skilled in the art can follow feature of the present invention, develop in addition with prior art many distortion.For example, can software mode realize the disclosed content of the present invention, for example, the function of disclosed equipment or method, making, modelling, simulation, explanation with and/or test.Above-mentioned software can adopt common program language (for example, C, C++), hardware description language, and (hardware description language HDL) comprises Verilog HDL, VHDL etc. or other available program languages.Above-mentioned software can be stated from existing any computer storage media, for example, magnetic recording system (magnetic tape), semiconductor (semiconductor), disk (magnetic disk) or CD (optical disc, as CD-ROM, DVD-ROM etc.) also can be stated from networking, wired system or other communication medias.The disclosed various apparatus and method of the present invention can be by semiconductor intellectual property core, and for example a microprocessor core can be realized and protection by hardware description language, and can be converted into example, in hardware, makes with IC regime.In addition, disclosed apparatus and method also can design realization jointly by hardware and software.Therefore, the present invention is not limited by above-mentioned any embodiment should, should understand according to the claim restricted portion.Particularly, the present invention can be implemented in the microprocessor, realizes general computing machine commonly used.The technology of the present invention field personnel might be based on the present invention, based on disclosed notion and described particular embodiment, design or adjust other structures, with under the prerequisite of the content that does not depart from claim and defined, development and the present invention have the technology of same purpose.
Claims (35)
1. a microprocessor is characterized in that, comprising:
One first memory cache and one second memory cache belong to the different levels of a memory cache stratum of this microprocessor respectively, and wherein, the level of this second memory cache in this memory cache stratum is lower than this first memory cache;
One is written into the unit, in order to receive the operation that is written into about a storer; And
One data pre-fetching device couples above-mentioned first memory cache and above-mentioned second memory cache, in order to:
Monitor the above-mentioned operation that is written into, and record is about getting at present an above-mentioned recent history that is written into operation of row soon;
Judge that this recently historical whether demonstration about what get row at present soon above-mentionedly is written into operation and has a specific direction; And
When the above-mentioned specific direction of this recent history display exists, look ahead one or many get row soon to this first memory cache; And do not show when having above-mentioned specific direction in this recent history, look ahead one or many get row soon to this second memory cache.
2. microprocessor according to claim 1 is characterized in that, be taken in advance this first memory cache above-mentioned one or many get soon classify as follow this specific direction to continue to get soon at present row one or many get row soon.
3. microprocessor according to claim 2 is characterized in that, be taken in advance this second memory cache above-mentioned one or many get soon to classify as to be connected in and get at present one after the row or many soon and get row soon.
4. microprocessor according to claim 1 is characterized in that, if being written into for D time at least of taking place recently is operating as same direction, above-mentioned recent history display has above-mentioned specific direction to exist, and wherein D is the default integer greater than 1.
5. microprocessor according to claim 4 is characterized in that D is set by the user.
6. microprocessor according to claim 1, it is characterized in that, this recent history comprises about the above-mentioned lowest address deviator and that is written into operation of getting at present row soon location deviator superlatively, and the highest counting that comprises a lowest count of the change of counting above-mentioned lowest address deviator and count the change of above-mentioned location superlatively deviator, above-mentioned being written into that described lowest count and the highest described counting are got row at present soon with this data pre-fetching device opening entry is operating as above-mentioned recent historical beginning, wherein, when the gap of above-mentioned minimum and the highest counting during greater than a preset value, above-mentioned recent history display one specific direction exists.
7. microprocessor according to claim 6 is characterized in that this preset value is set by the user.
8. microprocessor according to claim 1, it is characterized in that, this data pre-storage device is used for also judging whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the constant situation of other conditions, if above-mentioned being written into is operating as big data quantity, the quantity of getting row soon that this data pre-fetching device was looked ahead when the quantity of getting row soon that this data pre-fetching device is looked ahead can more above-mentionedly be written into operation not for big data quantity is many.
9. microprocessor according to claim 8 is characterized in that, is at least the Y byte if get all above-mentioned data volumes that are written into operation of row at present soon, and above-mentioned being written into of this recent history display is operating as big data quantity, and wherein Y is a preset value.
10. microprocessor according to claim 9 is characterized in that, the parameter that this preset value Y sets for the user.
11. microprocessor according to claim 8 is characterized in that, if above-mentionedly be written into that most data volume is at least the Y byte in the operation, above-mentioned being written into of this recent history display is operating as big data quantity, and wherein Y is a preset value.
12. microprocessor according to claim 8, it is characterized in that, when this recent history does not show that this specific direction exists, if above-mentioned being written into is operating as big data quantity, then can look ahead continue two of getting soon at present after the row of this data pre-fetching device get row soon to this second memory cache, if the above-mentioned non-big data quantity of operation that is written into, then can look ahead continue of getting soon at present after the row of this data pre-fetching device gets row soon to this second memory cache.
13. microprocessor according to claim 1, it is characterized in that, when this recent history display has above-mentioned specific direction, this data pre-fetching device judges also whether this recent history shows that above-mentioned being written into operates in continuous clock pulse and be received in the cycle, wherein, under the constant situation of other conditions, if above-mentioned being written into operates in continuous clock pulse and be received in the cycle, then the quantity of getting row soon that is taken to this first memory cache in advance by this data pre-fetching device can be written into operation is not taken to this first memory cache in advance by this data pre-fetching device when continuous clock pulse was received in the cycle the quantity of getting row soon more than above-mentioned.
14. microprocessor according to claim 13, it is characterized in that, if get soon at present row up-to-date above-mentionedly be written into that to operate be to be received in the cycle in the preceding continuous clock pulse that once is written into operation C time at least, this recent history display is got above-mentioned being written into of all of row at present soon and is operated in continuous clock pulse and be received in the cycle, wherein, C is the default integer greater than 1.
15. microprocessor according to claim 14 is characterized in that, this default integer C is user's parameter.
16. microprocessor according to claim 13, it is characterized in that, this data pre-fetching device is used for also judging whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the constant situation of other conditions, if above-mentioned being written into is operating as big data quantity, the quantity of getting row soon that then is taken to this first memory cache in advance can be more than the above-mentioned quantity of getting row soon that is taken to this first memory cache when operation is not big data quantity in advance that is written into.
17. microprocessor according to claim 16 is characterized in that, also comprises:
When above-mentioned being written into operates in that continuous clock pulse was received in the cycle and during for big data quantity, can look ahead three of following this specific direction to continue to get row at present soon of this data pre-fetching device get row soon to this first memory cache; And
When above-mentioned being written into operates in that continuous clock pulse was received in the cycle but during non-big data quantity, can look ahead two of following this specific direction to continue to get row at present soon of this data pre-fetching device get row soon to this first memory cache.
18. microprocessor according to claim 17 is characterized in that, also comprises:
To be written into operation be not to be received in the cycle but during for big data quantity at continuous clock pulse when above-mentioned, and can look ahead two of following this specific direction to continue to get row at present soon of this data pre-fetching device get row soon to this first memory cache; And
To be written into operation be not to be received in the cycle and during non-big data quantity at continuous clock pulse when above-mentioned, and can look ahead of following this specific direction to continue to get row at present soon of this data pre-fetching device gets row soon to this first memory cache.
19. microprocessor according to claim 1, it is characterized in that, above-mentioned one or more operation of getting row soon of can inhibition itself looking ahead of this data pre-fetching device has at least P time unless this recent history display is got the above-mentioned quantity that is written into operation of row at present soon, and wherein P is a preset value.
20. microprocessor according to claim 19 is characterized in that, the parameter that P sets for the user.
21. a prefetch data is to the method for the memory cache stratum of microprocessor, it is characterized in that, this memory cache stratum comprises one first memory cache and one second memory cache that belongs to different stratum, wherein this second memory cache is lower than this first memory cache in the level of this memory cache stratum, and this method comprises:
Monitor one of this microprocessor and be written into the operation that is written into that the unit receives, and record is operating as a recent history about above-mentioned being written into of getting row at present soon about a storer;
Judge whether this recently historically shows that get row at present soon above-mentioned is written into operation and has a specific direction; And
When this recent history display has above-mentioned specific direction, look ahead and one or more get row soon, and when this recent history does not show above-mentioned specific direction to this first memory cache, look ahead and one or more get row soon to this second memory cache.
22. prefetch data according to claim 21 is to the method for the memory cache stratum of microprocessor, it is characterized in that, be taken to above-mentioned one or more of this first memory cache in advance and get soon to classify as to follow this specific direction to continue at present to get one or more of row soon and get row soon.
23. prefetch data according to claim 22 is to the method for the memory cache stratum of microprocessor, it is characterized in that, be taken to above-mentioned one or more of this second memory cache in advance and get soon that classifying as continues one or more gets row soon after getting at present row soon.
24. prefetch data according to claim 21 is to the method for the memory cache stratum of microprocessor, it is characterized in that if being written into for D time at least of up-to-date generation is operating as same direction, the above-mentioned specific direction of this recent history display exists, wherein, D is the default integer greater than 1.
25. prefetch data according to claim 21 is to the method for the memory cache stratum of microprocessor, it is characterized in that, this recent history comprises a lowest address deviator and that get at present row soon above-mentioned be written into operation location deviator superlatively, and comprise a lowest count of the variation of counting this lowest address deviator and count this highest counting of the variation of location deviator superlatively, described lowest count and the highest described counting are got soon to list to state to be written into to operate to be recorded in this recent history from present and are begun, wherein, if the difference of described lowest count and described the highest counting is greater than a preset value, this recent history display has above-mentioned specific direction existence.
26. prefetch data according to claim 21 is characterized in that to the method for the memory cache stratum of microprocessor, also comprises:
Judge whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the identical situation of other conditions, if above-mentioned being written into be operating as big data quantity, the quantity of getting row soon of then looking ahead can be greater than the above-mentioned quantity of getting row soon of looking ahead when being written into operation not for big data quantity.
27. prefetch data according to claim 26 is to the method for the memory cache stratum of microprocessor, it is characterized in that, if the data volume that all are above-mentioned to be written into operation is Y byte at least, above-mentioned being written into of this recent history display is operating as big data quantity, and wherein Y is a preset value.
28. prefetch data according to claim 26 is to the method for the memory cache stratum of microprocessor, it is characterized in that, if most of above-mentioned data volumes that are written into operation are Y byte at least, above-mentioned being written into of this recent history display is operating as big data quantity, and wherein Y is a preset value.
29. prefetch data according to claim 26 is to the method for the memory cache stratum of microprocessor, it is characterized in that, if this recent history does not show above-mentioned specific direction, above-mentioned looking ahead one or more got row to the step of this second memory cache soon and is included in above-mentioned two of being written into that looking ahead when being operating as big data quantity continues and getting soon at present after the row and gets row soon to this second memory cache, and continue of getting soon at present after the row of looking ahead under other situations gets row soon to this second memory cache.
30. prefetch data according to claim 21 is characterized in that to the method for the memory cache stratum of microprocessor, also comprises:
When this recent history display has above-mentioned specific direction, judge whether this recent history shows that above-mentioned to be written into operation be to be received in the cycle at continuous clock pulse, wherein, under the constant situation of other conditions, if above-mentioned being written into operates in continuous clock pulse and be received in the cycle, the quantity of getting row soon that then is taken to this first memory cache in advance can be written into operation is not taken to this first memory cache in advance when continuous clock pulse was received in the cycle the quantity of getting row soon more than above-mentioned.
31. prefetch data according to claim 30 is to the method for the memory cache stratum of microprocessor, it is characterized in that, if get soon at present row up-to-date above-mentionedly be written into that to operate be to be received in the cycle in the preceding continuous clock pulse that once is written into operation C time at least, this recent history display is got above-mentioned being written into of all of row at present soon and is operated in continuous clock pulse and be received in the cycle, wherein, C is the default integer greater than 1.
32. prefetch data according to claim 30 is characterized in that to the method for the memory cache stratum of microprocessor, also comprises:
Judge whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the identical situation of other conditions, if above-mentioned being written into is operating as big data quantity, the quantity of getting row soon that then is taken to this first memory cache in advance can be more than the above-mentioned quantity of getting row soon that is taken to this first memory cache when operation is not big data quantity in advance that is written into.
33. prefetch data according to claim 32 is characterized in that to the method for the memory cache stratum of microprocessor, also comprises:
Operate in that continuous clock pulse was received in the cycle and during for big data quantity in above-mentioned being written into, three of following this specific direction to continue to get row at present soon of looking ahead get row soon to this first memory cache;
Operate in that continuous clock pulse was received in the cycle but during non-big data quantity in above-mentioned being written into, two of following this specific direction to continue to get row at present soon of looking ahead get row soon to this first memory cache.
34. prefetch data according to claim 33 is characterized in that to the method for the memory cache stratum of microprocessor, also comprises:
Be written in above-mentioned that operation is non-to be received in the cycle but when the big data quantity in continuous clock pulse, two of following this specific direction to continue to get row at present soon of looking ahead get row soon to this first memory cache; And
Be written in above-mentioned that operation is non-to be received in the cycle and during non-big data quantity in continuous clock pulse, of following this specific direction to continue to get row at present soon of looking ahead gets row soon to this first memory cache.
35. prefetch data according to claim 21 is characterized in that to the method for the memory cache stratum of microprocessor, also comprises:
Suppress above-mentioned one or more step of getting row soon of looking ahead, be that wherein P is a preset value P time at least unless this recent history display is got the quantity that is written into operation of row at present soon.
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| US12/869,386 | 2010-08-26 | ||
| US12/869,386 US8291172B2 (en) | 2010-04-27 | 2010-08-26 | Multi-modal data prefetcher |
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