CN102148567B - Voltage generating circuit - Google Patents
Voltage generating circuit Download PDFInfo
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- CN102148567B CN102148567B CN201010111216.7A CN201010111216A CN102148567B CN 102148567 B CN102148567 B CN 102148567B CN 201010111216 A CN201010111216 A CN 201010111216A CN 102148567 B CN102148567 B CN 102148567B
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Abstract
The invention discloses a voltage generating circuit, which is used for providing voltages to a loading unit. The loading unit comprises a voltage input end. The voltage generating circuit comprises a voltage adjuster and a voltage compensation unit. The voltage adjuster adjusts a reference voltage and generates an output voltage; and the voltage compensation unit generates a compensation voltage the of which lasting time is a preset time when the loading unit beings working; moreover, the output voltage and the compensation voltage are inputted to the voltage input end. The voltage generating circuit reduces the amplitude jogging of the output voltage, and guarantees the normal work of the loading unit.
Description
Technical field
The present invention relates to a kind of voltage generation circuit.
Background technology
Chip internal often needs multiple voltage accurately, as control signal or the reference voltage signal of disparate modules, as program voltage, erasing voltage etc. in flash memory (flash memory).Voltage generation circuit of the prior art generally uses reference voltage source to produce reference voltage, re-uses voltage regulator (regulator) and regulates this reference voltage, produces the output voltage of relevant voltage value according to the demand of disparate modules.
Fig. 1 shows a kind of voltage generation circuit schematic diagram of prior art, voltage regulator is used to regulate the reference voltage Vref that reference voltage source produces, produce output voltage Vout, described voltage regulator comprises: operational amplifier 101, driver element 102 and feedback unit 103.Described operational amplifier 101 is used as comparator, and two input connects the feedback voltage Vfb of reference voltage Vref and feedback unit 103 generation respectively, and its output connects described driver element 102; Described driver element 102 produces output voltage Vout and inputs to described feedback unit 103 and produces described feedback voltage Vfb.The output voltage Vout of described voltage regulator inputs to load unit 104, and described load unit 104 can comprise capacitor type load 1041 and/or current mode load 1042, as the read control signal port of flush memory device.
Fig. 2 is the particular circuit configurations of the voltage generation circuit shown in Fig. 1, and wherein driver element 102 specifically comprises PMOS transistor M1, and feedback unit 103 specifically comprises the resistor network be made up of resistance R1 and resistance R2.Wherein, operational amplifier 101 is used as comparator, the branch pressure voltage that feedback unit 103 produces is as feedback voltage Vfb, the conducting situation of PMOS transistor M1 is controlled by the comparative result of feedback voltage Vfb and reference voltage Vref, after repeatedly feeding back, make feedback voltage Vfb be tending towards equal with the magnitude of voltage of reference voltage Vref, thus obtain stable output voltage.In actual applications, output voltage Vout can be made to be scheduled voltage by the resistance value of the resistor network in the magnitude of voltage of adjustment reference voltage Vref and feedback unit 103.
About voltage generation circuit and voltage regulator, more detailed descriptions can also be the Chinese patent application of 200710197115.4 with reference to disclosed application number.
Usually, load unit 104 in Fig. 1 and Fig. 2 is not keep operating state always, but just starts working after an enable signal is effective, thus equivalence can become current mode or capacitor type load, and when enable signal is invalid, be equivalent to open-circuit condition.Fig. 3 shows the schematic diagram of the output voltage of enable signal and the generation of described voltage regulator, composition graphs 3 and Fig. 2, and after enable signal EN is effective, load unit 104 is started working, and the load of whole voltage regulator is changed.Owing to being fixing by the transient current of PMOS transistor M1, and capacitor type load 1041 and current mode load 1042 all can produce shunting effect, the electric current resulting through resistance R1 and R2 diminishes, the magnitude of voltage of the output voltage Vout of whole voltage regulator is reduced, the feedback voltage Vfb that feedback unit 103 produces simultaneously also reduces, after feedback, output voltage Vout returns to scheduled voltage gradually.But, because voltage regulator is the course of work of reaction type, output voltage Vout from be reduced to return to scheduled voltage often will through certain feedback delay, therefore, after load unit 104 is started working, there is downward amplitude dither in the voltage curve of output voltage Vout, affects the normal work of load unit 104.
Summary of the invention
The problem that the present invention solves is to provide a kind of voltage generation circuit, reduces the amplitude dither of its output voltage when load unit is started working.
For solving the problem, the invention provides a kind of voltage generation circuit, for providing voltage to load unit, described load unit comprises voltage input end, and described voltage generation circuit comprises:
Voltage regulator, regulates reference voltage, produces output voltage;
Voltage compensation unit, producing the duration when described load unit is started working is the bucking voltage of Preset Time,
Described output voltage and bucking voltage input to described voltage input end.
Optionally, described voltage compensation unit comprises:
Trigger generation unit, producing the duration when described load unit is started working is the triggering signal of Preset Time;
Voltage drive unit, is controlled by described triggering signal, produces described bucking voltage.
Optionally, described load unit is controlled by enable signal, works, quit work when described enable signal is invalid when described enable signal is effective.
Optionally, described triggering signal is pulse signal, and its pulse duration equals described Preset Time.
Optionally, described enable signal is that high level is effective, and described triggering generation unit comprises:
Time delay rp unit, inputs described enable signal, carries out enable signal in the middle of time delay and anti-phase rear generation;
NAND gate, inputs described enable signal and middle enable signal, after carrying out NAND operation, produces described pulse signal.
Optionally, described voltage drive unit comprises PMOS transistor, and the grid of described PMOS transistor inputs described pulse signal, and source electrode input predetermined voltage, drain electrode connects the voltage input end of described load unit.
Optionally, described enable signal is Low level effective, and described triggering generation unit comprises:
Time delay rp unit, inputs described enable signal, carries out enable signal in the middle of time delay and anti-phase rear generation;
NOR gate, inputs described enable signal and middle enable signal, after carrying out NOR-operation, produces described pulse signal.
Optionally, described voltage drive unit comprises nmos pass transistor, and the grid of described nmos pass transistor inputs described pulse signal, and drain electrode connects predetermined voltage, and source electrode connects the voltage input end of described load unit.
Optionally, described time delay rp unit comprises: the inverter of odd level series connection.
Optionally, total time delay of the inverter of described odd level series connection equals described Preset Time.
Compared with prior art, this technology has the following advantages: when load unit is started working, produce bucking voltage by voltage compensation unit, compensates the output voltage of voltage regulator, reduces the amplitude dither of output voltage.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of voltage generation circuit of prior art;
Fig. 2 is the circuit diagram that voltage generation circuit shown in Fig. 1 is corresponding;
Fig. 3 is the sequential relationship schematic diagram of the output voltage of the voltage generation circuit of prior art and the enable signal of load unit;
Fig. 4 is the structural representation of the voltage generation circuit connection load unit of embodiment of the present invention;
Fig. 5 is the embodiment circuit diagram that the voltage compensation unit shown in Fig. 4 connects load unit;
Fig. 6 is the sequential relationship schematic diagram of the enable signal that the voltage generation circuit shown in Fig. 5 is corresponding, middle enable signal, pulse signal and output voltage;
Fig. 7 be voltage compensation unit shown in Fig. 4 connect load unit another embodiment circuit diagram;
Fig. 8 is the sequential relationship schematic diagram of the enable signal that the voltage generation circuit shown in Fig. 7 is corresponding, middle enable signal, pulse signal and output voltage.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with drawings and Examples.
In the voltage generation circuit of prior art, use the control voltage of output voltage as load unit of voltage regulator, when load unit is started working, the output loading of whole voltage regulator is caused to change, and due to the delay of feedback of voltage regulator, make the output voltage of voltage regulator produce the shake of amplitude, affect the normal work of described load unit.
Technical scheme of the present invention adds voltage compensation unit in voltage generation circuit, when load unit is started working, producing the duration is the bucking voltage of Preset Time, to compensate the output voltage of voltage regulator in the certain hour after load unit is started working, reduce its amplitude dither, thus the normal work of proof load unit.
Fig. 4 shows the structural representation of the voltage generation circuit connection load unit of embodiment of the present invention.Described load unit 204 can comprise capacitor type load 2041 and/or current mode load 2042, as the read port of flush memory device.In the present embodiment, the operating state of described load unit 204 is controlled by enable signal EN, works, be equivalent to current mode load when described enable signal EN is effective; Quit work when described enable signal is invalid, be equivalent to open circuit.Load unit 204 comprises voltage input end, and the operating voltage of load unit 204 or control voltage (such as, program voltage, the erasing voltage of flash memory) are provided by the voltage of the described voltage input end of input.
As shown in Figure 4, described voltage generation circuit is used for providing voltage to load unit, mainly comprise: voltage regulator 200 and voltage compensation unit 205, the output voltage Vout that described voltage regulator 200 produces and the bucking voltage that described voltage compensation unit 205 produces input to the voltage input end of load unit 204, and namely the output of voltage regulator 200, the output of voltage compensation unit 205 are connected with the voltage input end of load unit 204.
Described voltage regulator 200 comprises: operational amplifier 201, driver element 202 and feedback unit 203.Two inputs of described operational amplifier 201 connect reference voltage Vref and feedback voltage Vfb respectively, and output connects the voltage input end of described driver element 202; Described driver element 202 produces output voltage Vout; Described feedback unit 203 receives described output voltage Vout and produces described feedback voltage Vfb.Similarly to the prior art, described driver element 202 can comprise PMOS transistor, and described feedback unit 203 can comprise the resistor network that series resistance is formed.
Described voltage compensation unit 205 is when described load unit 204 is started working, and producing the duration is the bucking voltage of Preset Time, and described bucking voltage inputs to the voltage input end of described load unit 204.The span of described Preset Time is suitable with the feedback delay of described voltage regulator 200, can be such as 0.5ns to 5ns, make after described load unit 204 is started working, described voltage regulator 200 produces bucking voltage before feedback stability not yet, described output voltage Vout is compensated, reduce the amplitude dither of the output voltage Vout caused when load unit 204 is started working, ensure that it normally works.
In the present embodiment, described voltage compensation unit 205 comprises triggering generation unit 206 and voltage drive unit 207.It is the triggering signal of Preset Time that described triggering generation unit 206 produces the duration when load unit 204 starts working (when namely enable signal EN starts effective), be specially pulse signal in the present embodiment, its pulse duration equals described Preset Time.Described voltage drive unit 207 controls by described triggering signal (being pulse signal in the present embodiment), produces bucking voltage.
In actual applications, described Preset Time determines according to the particular circuit configurations of voltage regulator 200 and the operating current of load unit 204, and in a specific embodiment, the internal circuit configuration of voltage regulator 200 is determined; After another load unit 204 is determined, the magnitude of voltage of the output voltage Vout of voltage regulator 200 is also determined thereupon; In addition, the current margin of load unit 204 is also corresponding to be determined, thus can pass through circuit simulation software (as spice) load unit 204 is started working after the feedback procedure of voltage regulator 200 simulate, determine its delay of feedback, thus determine the duration of described bucking voltage accordingly.It should be noted that, if the duration of described bucking voltage is too short, much smaller than the feedback delay of described voltage regulator 200, can cause fully can not compensating described output voltage, the voltage signal that the voltage input end of described load unit 204 is received still has obvious shake; If the duration of described bucking voltage is long, much larger than the feedback delay of described voltage regulator 200, described bucking voltage after feedback stability is still existed, there is " overcharging " in the voltage signal causing the voltage input end of described load unit 204 to receive, the i.e. shake upwards of voltage magnitude, the normal work affecting described load unit 204 even causes circuit to damage.
In addition, the scheduled voltage (namely needing to be supplied to the magnitude of voltage of load unit 204) of the output voltage Vout that the magnitude of voltage of described bucking voltage should produce with described voltage regulator 200 adapts, if the magnitude of voltage of described bucking voltage is too low, its compensation ability is excessively weak, causes the amplitude of output voltage Vout still to have significantly shake downwards; If the magnitude of voltage of described bucking voltage is too high, the amplitude of output voltage Vout can be caused to occur significantly overcharging, the damage of described load unit 204 internal circuit may be caused.
Fig. 5 shows the circuit diagram that voltage compensation unit of the present invention connects an embodiment of load unit.As shown in Figure 5, voltage compensation unit comprises: trigger generation unit 206 and voltage drive unit 207.The bucking voltage that described voltage drive unit 207 produces and the output voltage that described voltage regulator (not shown) produces input in the voltage input end of load power source 204.
Described load unit 204 can comprise capacitor type load 2041 and/or current mode load 2042, and its operating state is controlled by enable signal EN.In the present embodiment, described load unit 204 is started working when enable signal EN is high level, quits work when enable signal EN is low level.
Described triggering generation unit 206 comprises and postpones rp unit 2061 and NAND gate 2062, wherein postpones the inverter that rp unit 2061 specifically comprises odd level series connection in the present embodiment, as 3 grades, 5 grades, 7 grades inverter series form.Composition graphs 6 simultaneously, described delay rp unit 2061 carries out enable signal EN_d in the middle of delay and anti-phase rear generation to described enable signal EN.Described enable signal EN and middle enable signal EN_d inputs to described NAND gate 2062, after NAND Logic computing, produces pulse signal pulse, is specially a low level pulse signal.Total time delay of the inverter (namely postponing rp unit 2061) of described odd level series connection equals described Preset Time, be specially 0.5ns to 5ns, by selecting the inverter of specific dimensions in the present embodiment, make total time delay be preferably 2ns (adapting with the delay of feedback of voltage regulator), the pulse duration of the pulse signal pulse thus generated also is 2ns.
Described voltage drive unit 207 comprises a PMOS transistor, (scheduled voltage of the output voltage Vout produced with described voltage regulator 200 adapts its source electrode input predetermined voltage, if the present embodiment is supply voltage VDD), drain electrode connects the voltage input end of load unit 204, and grid inputs the pulse signal pulse that described triggering generation unit 206 produces.Composition graphs 6, when described enable signal EN becomes high level from low level, namely when load unit 204 enters operating state, described triggering generation unit 206 produces a low level pulse signal pulse, described pulse signal pulse inputs to the grid of the PMOS transistor in voltage drive unit 207, make described PMOS transistor conducting, produce bucking voltage, compensate the output voltage Vout that voltage regulator produces, the amplitude dither of the voltage signal that the voltage input end of load unit 204 is received is less.Because the time delay of the delay rp unit 2061 chosen is 2ns in the present embodiment, suitable with the delay of feedback of voltage regulator, make the duration of the bucking voltage produced also suitable with the delay of feedback of voltage regulator, thus better to the compensation effect of the output voltage that voltage regulator produces, undercompensation or overload phenomenon can not be produced.
In actual applications, described predetermined voltage determines according to the particular circuit configurations of described voltage drive unit 207 and load unit 204, emulated by circuit simulation software, determine the magnitude of voltage of described predetermined voltage, thus ensureing that the bucking voltage produced fully can compensate the output voltage Vout of voltage regulator 200, the magnitude of voltage that the voltage input end of proof load unit 204 receives is the scheduled voltage of output voltage Vout.
Fig. 7 show voltage compensation unit of the present invention connect load unit another embodiment circuit diagram.As shown in Figure 7, comprising: trigger generation unit 206, voltage drive unit 207 and voltage regulator (not shown).The bucking voltage that described voltage drive unit 207 produces and the output voltage that described voltage regulator produces input in the voltage input end of load power source 204.
Described load unit 204 can comprise capacitor type load 2041 and/or current mode load 2042, and its operating state is controlled by enable signal EN.In the present embodiment, described load unit 204 is started working when enable signal EN is low level, quits work when enable signal EN is high level.
Described triggering generation unit 206 comprises and postpones rp unit 2063 and NOR gate 2064, wherein postpones the inverter that rp unit 2063 specifically comprises odd level series connection in the present embodiment, as 3 grades, 5 grades, 7 grades inverter series form.Composition graphs 8 simultaneously, described delay rp unit 2063 carries out enable signal EN_d in the middle of delay and anti-phase rear generation to described enable signal EN.Described enable signal EN and middle enable signal EN_d inputs to described NOR gate 2064, after NOR-logic computing, produces pulse signal pulse, is specially a low level pulse signal.Total time delay of the inverter (namely postponing rp unit 2063) of described odd level series connection equals described Preset Time, be specially 0.5ns to 5ns, by selecting the inverter of specific dimensions in the present embodiment, make total time delay be preferably 2ns (suitable with the delay of feedback of voltage regulator), the pulse duration of the pulse signal pulse thus generated also is 2ns.
Described voltage drive unit 207 comprises a nmos pass transistor, its drain electrode input predetermined voltage (the present embodiment is supply voltage VDD), source electrode connects the voltage input end of load unit 204, and grid inputs the pulse signal pulse that described triggering generation unit 206 produces.Composition graphs 8, when described enable signal EN becomes low level from high level, namely when load unit 204 enters operating state, described triggering generation unit 206 produces the pulse signal pulse of a high level, described pulse signal pulse inputs to the grid of the nmos pass transistor in voltage drive unit 207, make described nmos pass transistor conducting, produce bucking voltage, compensate the output voltage Vout that voltage regulator produces, the amplitude dither of the voltage signal that the voltage input end of load unit 204 is received is less.Because the time delay of the delay rp unit 2063 chosen is 2ns in the present embodiment, suitable with the delay of feedback of voltage regulator, make the duration of the bucking voltage produced also suitable with the delay of feedback of voltage regulator, thus better to the compensation effect of the output voltage that voltage regulator produces, undercompensation or overload phenomenon can not be produced.
To sum up, the voltage generation circuit that technique scheme provides, when load unit is started working, bucking voltage is produced by voltage compensation unit, the duration of described bucking voltage and the delay of feedback type of voltage regulator are worked as, thus effective compensation has been carried out to the output voltage that voltage regulator produces, reduce the amplitude dither of the voltage signal that load unit receives, ensure that the normal work of load unit.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a voltage generation circuit, for providing voltage to load unit, described load unit comprises voltage input end, it is characterized in that, comprising:
Voltage regulator, regulates reference voltage, produces output voltage;
Voltage compensation unit, producing the duration when described load unit is started working is the bucking voltage of Preset Time, and the span of described Preset Time is suitable with the feedback delay of described voltage regulator,
Described output voltage and bucking voltage input to described voltage input end;
Described voltage regulator comprises: operational amplifier, driver element and feedback unit; Two inputs of described operational amplifier connect reference voltage and feedback voltage respectively, and output connects the voltage input end of described driver element; Described driver element produces described output voltage; Described feedback unit receives described output voltage and produces described feedback voltage;
Described load unit also comprises: capacitor type load and/or current mode load.
2. voltage generation circuit according to claim 1, is characterized in that, described voltage compensation unit comprises:
Trigger generation unit, producing the duration when described load unit is started working is the triggering signal of Preset Time;
Voltage drive unit, is controlled by described triggering signal, produces described bucking voltage.
3. voltage generation circuit according to claim 2, is characterized in that, described load unit is controlled by enable signal, works, quit work when described enable signal is invalid when described enable signal is effective.
4. voltage generation circuit according to claim 3, is characterized in that, described triggering signal is pulse signal, and its pulse duration equals described Preset Time.
5. voltage generation circuit according to claim 4, is characterized in that, described enable signal is that high level is effective, and described triggering generation unit comprises:
Time delay rp unit, inputs described enable signal, carries out enable signal in the middle of time delay and anti-phase rear generation;
NAND gate, inputs described enable signal and middle enable signal, after carrying out NAND operation, produces described pulse signal.
6. voltage generation circuit according to claim 5, it is characterized in that, described voltage drive unit comprises PMOS transistor, and the grid of described PMOS transistor inputs described pulse signal, source electrode input predetermined voltage, drain electrode connects the voltage input end of described load unit.
7. voltage generation circuit according to claim 4, is characterized in that, described enable signal is Low level effective, and described triggering generation unit comprises:
Time delay rp unit, inputs described enable signal, carries out enable signal in the middle of time delay and anti-phase rear generation;
NOR gate, inputs described enable signal and middle enable signal, after carrying out NOR-operation, produces described pulse signal.
8. voltage generation circuit according to claim 7, it is characterized in that, described voltage drive unit comprises nmos pass transistor, and the grid of described nmos pass transistor inputs described pulse signal, drain electrode connects predetermined voltage, and source electrode connects the voltage input end of described load unit.
9. the voltage generation circuit according to any one of claim 5 to 8, is characterized in that, described time delay rp unit comprises: the inverter of odd level series connection.
10. want the voltage generation circuit described in 9 according to right, it is characterized in that, total time delay of the inverter of described odd level series connection equals described Preset Time.
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| CN201010111216.7A CN102148567B (en) | 2010-02-10 | 2010-02-10 | Voltage generating circuit |
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| CN201010111216.7A CN102148567B (en) | 2010-02-10 | 2010-02-10 | Voltage generating circuit |
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| CN102148567B true CN102148567B (en) | 2015-07-08 |
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| EP0928056A2 (en) * | 1997-12-30 | 1999-07-07 | Texas Instruments Incorporated | Voltage loss compensation for dc-dc converters |
| CN101135917A (en) * | 2006-08-28 | 2008-03-05 | 联詠科技股份有限公司 | Voltage regulator |
| CN101145063A (en) * | 2006-09-11 | 2008-03-19 | 华硕电脑股份有限公司 | Transient voltage compensation device and power supply device using same |
| CN101183268A (en) * | 2007-11-26 | 2008-05-21 | 天津理工大学 | Dynamic recovery device control system based on voltage self anti-interference control |
| CN101187818A (en) * | 2006-11-21 | 2008-05-28 | 联发科技股份有限公司 | Integration circuit and method for providing output voltage actually reference voltage |
| CN101393465A (en) * | 2008-10-28 | 2009-03-25 | 上海电力学院 | Bridge type series, parallel and mixture connection electric energy regulator based on IGBT |
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2010
- 2010-02-10 CN CN201010111216.7A patent/CN102148567B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0928056A2 (en) * | 1997-12-30 | 1999-07-07 | Texas Instruments Incorporated | Voltage loss compensation for dc-dc converters |
| CN101135917A (en) * | 2006-08-28 | 2008-03-05 | 联詠科技股份有限公司 | Voltage regulator |
| CN101145063A (en) * | 2006-09-11 | 2008-03-19 | 华硕电脑股份有限公司 | Transient voltage compensation device and power supply device using same |
| CN101187818A (en) * | 2006-11-21 | 2008-05-28 | 联发科技股份有限公司 | Integration circuit and method for providing output voltage actually reference voltage |
| CN101183268A (en) * | 2007-11-26 | 2008-05-21 | 天津理工大学 | Dynamic recovery device control system based on voltage self anti-interference control |
| CN101393465A (en) * | 2008-10-28 | 2009-03-25 | 上海电力学院 | Bridge type series, parallel and mixture connection electric energy regulator based on IGBT |
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