CN102141944B - Method for reducing errors incapable of being corrected, memory device and controller thereof - Google Patents
Method for reducing errors incapable of being corrected, memory device and controller thereof Download PDFInfo
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- CN102141944B CN102141944B CN 201010121050 CN201010121050A CN102141944B CN 102141944 B CN102141944 B CN 102141944B CN 201010121050 CN201010121050 CN 201010121050 CN 201010121050 A CN201010121050 A CN 201010121050A CN 102141944 B CN102141944 B CN 102141944B
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Abstract
The invention relates to a method for reducing errors incapable of being corrected with respect to error correction codes in a memory device. The method comprises the following steps of: carrying out a majority rule based on data of the same address read at different times to generate majority rule data corresponding to the address; and checking whether the majority rule data has errors incapable of being corrected to decide whether the majority rule data is output to be used as the data of the address. The invention further relates to a relevant memory device and a controller thereof. The invention can be used for reducing errors incapable of being corrected with respect to error correction codes in the memory device. In addition, the invention can give consideration to operational efficiency and system resource use control and management without relevant technical problems, such as wrongly marking some blocks as bad blocks. Furthermore, the capacity of a buffer region/buffer device can be saved and the data at the last time and the majority rule data are ready for use during the reading of the data at the last time, so that the best efficiency is provided.
Description
Technical field
The present invention relates to the error correction technical field of flash memory (Flash Memory) control chip; More particularly; Relate to and a kind ofly be used for reducing in the middle of the memory storage about error correcting code (Error CorrectionCode, the method for the mistake that can't correct ECC) and relevant memory storage and controller thereof.
Background technology
Because the technology of flash memory constantly develops, various Portable memory storages (for example: the memory card that meets SD/MMC, CF, MS, XD standard) or possess the solid state hard disc of flash memory (Solid StateDrive SSD) is implemented in many application widely in recent years.Therefore, the access control of the flash memory in these memory storages becomes quite popular subject under discussion then.
With NAND type flash memory commonly used, it mainly can divide into the single-order cell, and (Single LevelCell is SLC) with multistage cell (Multiple Level Cell, MLC) two big types flash memory.The transistor that in the single-order cell flash memory each is taken as mnemon has only two kinds of charge values, is used for presentation logic value 0 and logical value 1 respectively.In addition; The transistorized storage capacity that in the multistage cell flash memory each is taken as mnemon then is fully utilized; Adopt higher voltage to drive, (for example: 00,01,11,10) in a transistor, write down two groups of position information with voltage through different stage; In theory, the recording density of multistage cell flash memory can reach more than the twice of recording density of single-order cell flash memory, and this is extraordinary message for once for the related industry of the NAND type flash memory that runs into bottleneck in the evolution.
Compared to single-order cell flash memory, because the price of multistage cell flash memory is more cheap, and can provide bigger capacity in limited space, so multistage cell flash memory becomes the main flow that Portable memory storage on the market competitively adopts soon.Yet the problem that instability caused of multistage cell flash memory is also appeared in one's mind one by one.To these problems,, always can't take into account operational effectiveness and system resource and use keyholed back plate though some settling modes are provided in the correlation technique.So,, often have corresponding spinoff no matter take which settling mode.Therefore, the method for a kind of novelty of needs is strengthened the data access of keyholed back plate flash memory, uses keyholed back plate to take into account operational effectiveness and system resource.
Summary of the invention
The technical matters that the present invention will solve is; Above-mentioned defective to prior art; Providing a kind of is used for reducing in the middle of the memory storage about error correcting code (Error Correction Code; The method of the mistake that can't correct ECC) and relevant memory storage and controller thereof use keyholed back plate to take into account operational effectiveness and system resource.
One of the technical solution adopted for the present invention to solve the technical problems is: construct a kind of method that is used for reducing the mistake that can't correct; Those mistakes that can't correct are the central mistake that can't correct about error correcting code of a memory storage; This method includes: the data that are dependent on the same address that homogeneous did not read are carried out majority rule, to produce the majority rule data corresponding to this address; And check whether these majority rule data have the mistake that can't correct, whether export the data of these majority rule data with decision as this address.
Method of the present invention, it includes in addition:
At least a portion in the middle of the data of this same address that homogeneous did not read is temporary in a plurality of buffer zone/impact dampers respectively.
Method of the present invention, the step that wherein that the data of this same address that homogeneous did not read are central at least a portion is temporary in those buffer zone/impact dampers respectively includes in addition:
All data except last data in the middle of the data of this same address that homogeneous did not read are temporary in those buffer zone/impact dampers respectively.
Method of the present invention, the step that wherein that the data of this same address that homogeneous did not read are central at least a portion is temporary in those buffer zone/impact dampers respectively includes in addition:
In the process of carrying out this majority rule; Last data in the middle of the data of this same address that homogeneous did not read are temporary in the first buffer zone/impact damper in those buffer zone/impact dampers, to take the up-to-date part that reads in the middle of the part of carrying out this majority rule is substituted by these last data with up-to-date in the middle of this first buffer zone/impact damper.
Method of the present invention, the data that wherein are dependent on this same address that homogeneous did not read are carried out this majority rule and are included in addition with the step that produces corresponding to this majority rule data of this address:
In the process of carrying out this majority rule; These majority rule data are temporary in the second buffer zone/impact damper in those buffer zone/impact dampers, with up-to-date part of taking up-to-date generation in the middle of the part of carrying out this majority rule is substituted by these majority rule data in the middle of this second buffer zone/impact damper.
Method of the present invention, the number of times that wherein reads the data of this same address is an odd number.
Method of the present invention, wherein the employed threshold voltage (Read Threshold-Voltage) that reads is not quite similar when homogeneous does not read the data of this same address.
Two of the technical solution adopted for the present invention to solve the technical problems is: construct a kind of memory storage, this memory storage includes: a flash memory (Flash Memory), and this flash memory comprises a plurality of blocks; And a controller, be used for this flash memory of access (Access) and management this a plurality of blocks, and be used for reducing the central mistake that can't correct of this memory storage in addition about error correcting code.In addition, this controller is dependent on the data of the same address that homogeneous did not read and carries out majority rule, to produce the majority rule data corresponding to this address.In addition, whether these these majority rule data of controller inspection have the mistake that can't correct, whether export the data of these majority rule data as this address with decision.
Memory storage of the present invention, wherein this controller is temporary in a plurality of buffer zone/impact dampers respectively with at least a portion in the middle of the data of this same address that homogeneous did not read.
Memory storage of the present invention, wherein this controller is temporary in those buffer zone/impact dampers respectively with all data except last data in the middle of the data of this same address that homogeneous did not read.
Memory storage of the present invention; Wherein in the process of carrying out this majority rule; This controller will this same address that homogeneous did not read the central last data of data be temporary in the first buffer zone/impact damper in those buffer zone/impact dampers, to take the up-to-date part that reads in the middle of the part of carrying out this majority rule is substituted by these last data with up-to-date in the middle of this first buffer zone/impact damper.
Memory storage of the present invention; Wherein in the process of carrying out this majority rule; This controller is temporary in the second buffer zone/impact damper in those buffer zone/impact dampers with these majority rule data, with up-to-date part of taking up-to-date generation in the middle of the part of carrying out this majority rule is substituted by these majority rule data in the middle of this second buffer zone/impact damper.
Memory storage of the present invention, wherein to read the number of times of the data of this same address be odd number to this controller.
Memory storage of the present invention, wherein this controller employed threshold voltage (Read Threshold-Voltage) that reads when homogeneous does not read the data of this same address is not quite similar.
Memory storage of the present invention, wherein this controller comprises:
One majority rule module, the data that are used for being dependent on this same address that homogeneous did not read are carried out majority rule, to produce these majority rule data corresponding to this address; And
One error correcting code demoder is used for carrying out the error correcting code decoding.
Memory storage of the present invention, wherein this controller comprises in addition:
A plurality of multiplexers are used for carrying out multiplex's selection, to control the data stream in this controller.
Memory storage of the present invention, wherein this majority rule module, this error correcting code demoder and those multiplexers are the part of a steering logic of this controller, and are made up of the logical circuit in this steering logic.
Memory storage of the present invention, wherein the performed program code of the microprocessor in this controller comprises a plurality of programs module/unit; And at least a portion in the middle of this majority rule module, this error correcting code demoder and those multiplexers is implemented through utilizing this microprocessor of carrying out those program module/unit.
Three of the technical solution adopted for the present invention to solve the technical problems is: the controller of constructing a kind of memory storage; This controller is used for the flash memory in this memory storage of access; This flash memory comprises a plurality of blocks; This controller includes: (Read Only Memory ROM), is used for storing a program code to a ROM (read-only memory); An and microprocessor; Be used for carrying out this program code with control access and management this a plurality of blocks to this flash memory, wherein this controller through this this program code of microprocessor execution is used for reducing in the middle of this memory storage the mistake that can't correct about error correcting code in addition.In addition, this controller is dependent on the data of the same address that homogeneous did not read and carries out majority rule, to produce the majority rule data corresponding to this address.In addition, whether these these majority rule data of controller inspection have the mistake that can't correct, whether export the data of these majority rule data as this address with decision.
Controller of the present invention, wherein this controller is temporary in a plurality of buffer zone/impact dampers respectively with at least a portion in the middle of the data of this same address that homogeneous did not read.
Controller of the present invention, wherein this controller is temporary in those buffer zone/impact dampers respectively with all data except last data in the middle of the data of this same address that homogeneous did not read.
Controller of the present invention; Wherein in the process of carrying out this majority rule; This controller will this same address that homogeneous did not read the central last data of data be temporary in the first buffer zone/impact damper in those buffer zone/impact dampers, to take the up-to-date part that reads in the middle of the part of carrying out this majority rule is substituted by these last data with up-to-date in the middle of this first buffer zone/impact damper.
Controller of the present invention; Wherein in the process of carrying out this majority rule; This controller is temporary in the second buffer zone/impact damper in those buffer zone/impact dampers with these majority rule data, with up-to-date part of taking up-to-date generation in the middle of the part of carrying out this majority rule is substituted by these majority rule data in the middle of this second buffer zone/impact damper.
Controller of the present invention, wherein to read the number of times of the data of this same address be odd number to this controller.
Controller of the present invention, wherein this controller employed threshold voltage (Read Threshold-Voltage) that reads when homogeneous does not read the data of this same address is not quite similar.
Controller of the present invention, wherein this controller comprises:
One majority rule module, the data that are used for being dependent on this same address that homogeneous did not read are carried out majority rule, to produce these majority rule data corresponding to this address; And
One error correcting code demoder is used for carrying out the error correcting code decoding.
Controller of the present invention, wherein this controller comprises in addition:
A plurality of multiplexers are used for carrying out multiplex's selection, to control the data stream in this controller.
Controller of the present invention, wherein this majority rule module, this error correcting code demoder and those multiplexers are the part of a steering logic of this controller, and are made up of the logical circuit in this steering logic.
Controller of the present invention, wherein this program code comprises a plurality of programs module/unit; And at least a portion in the middle of this majority rule module, this error correcting code demoder and those multiplexers is implemented through utilizing this microprocessor of carrying out those program module/unit.
The technical scheme of embodiment of the present invention has following beneficial effect: the present invention can reduce the central mistake that can't correct about error correcting code of memory storage.In addition, the present invention can take into account operational effectiveness and system resource and use keyholed back plate, and the problem that does not have a correlation technique such as with some block errors be denoted as bad block.
In addition; The present invention can save the consumption of buffer zone/impact damper; And in the process that reads these last data, be ready for these last data and this majority rule data simultaneously for taking, so method of the present invention and relevant memory storage and controller thereof can provide splendid usefulness.
Description of drawings
To combine accompanying drawing and embodiment that the present invention is described further below, in the accompanying drawing:
Fig. 1 is the synoptic diagram of a kind of memory storage of the present invention one first embodiment.
Fig. 2 is that one embodiment of the invention a kind of is used for reducing in the middle of the memory storage about error correcting code (Error Correction Code, the process flow diagram of the method for the mistake that can't correct ECC).
Fig. 3 is the implementation detail of method in an embodiment shown in Figure 2.
Fig. 4 is illustrated in the synoptic diagram of the related majority rule of method shown in Figure 2 among the embodiment.
[main element symbol description]
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| 110 | |
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| 112 | |
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| | Program code | |
| 112M | ROM (read-only memory) | |
| 114 | |
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| 1142，1146 | |
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| 1144 | The error |
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| 1148 | The |
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| 120 | Flash |
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| 910 | Be used for reducing in the middle of the memory storage method about the mistake that can't correct of error correcting code |
| 912，914，922，924，926， 928，930 | |
| 920 | Workflow |
| B(1)，B(2) | Buffer zone/impact damper |
| Bit(x)，Bit(y)，Bit(z) | The position |
| D(1)，D(2)，D(3) | The data of the same address that homogeneous did not read |
| V(D(1)，D(2)，D(3)) | The majority rule data |
Embodiment
Please refer to Fig. 1; Fig. 1 is the synoptic diagram of a kind of memory storage 100 of the present invention one first embodiment; Wherein memory storage 100 can represent the Portable memory storage (for example: the memory card that meets SD/MMC, CF, MS, XD standard) or solid state hard disc (Solid State Drive, various memory storages such as SSD).Memory storage 100 includes: a flash memory (Flash Memory) 120; And a controller, be used for access (Access) flash memory 120, wherein this controller Memory Controller 110 for example.According to present embodiment; Memory Controller 110 comprises a microprocessor 112, a ROM (read-only memory) (Read Only Memory; ROM) 112M, a steering logic 114, a memory buffer 116, with an interface logic 118; Wherein steering logic 114 comprise multiplexer 1142 and 1146, an error correcting code (Error CorrectionCode, ECC) demoder 1144, with a majority rule module 1148.At this, impact damper B (1) and B (2) can represent the different buffer zone in the middle of the memory buffer 116 or represent the impact damper that has entity framework separately in the middle of the memory buffer 116.In addition, ROM (read-only memory) 112M is used for storing a program code 112C, and microprocessor 112 then is used for executive routine code 112C with the access of control to flash memory 120.Note that program code 112C also must be stored in memory buffer 116 or any type of storer.
Under typical situation, flash memory 120 comprises a plurality of blocks (Block), and the erase running of data is that unit erases with the block and this controller (for example: through the Memory Controller 110 of microprocessor 112 executive routine code 112C) is to flash memory 120.In addition, a block can write down the page or leaf (Page) of specific quantity, and wherein this controller is that unit writes with the page or leaf to the running that flash memory 120 writes data.
On real the work; Memory Controller 110 through microprocessor 112 executive routine code 112C can utilize itself inner element to carry out many control runnings, for example: utilize steering logic 114 to control the access running of flash memory 120 (especially at least one block or the access running of one page at least), utilize memory buffer 116 to carry out required buffered and utilize an interface logic 118 and a main device (Host Device) to link up.
According to present embodiment, multiplexer 1142 and 1146 can be used to carry out multiplex's selection, to control the data stream in this controller.For example: multiplexer 1142 and 1146 can carry out multiplex's selection according to the control of the microprocessor 112 of executive routine code 112C; Again for example: multiplexer 1142 and 1146 can carry out multiplex's selection according to the control of the logical circuit in the steering logic 114.In addition, error correcting code demoder 1144 can be used to carry out the error correcting code decoding, and majority rule module 1148 can be used to carry out the majority rule running.On real the work, multiplexer 1142 and 1146, error correcting code demoder 1144, and majority rule module 1148 be the part of steering logic 114, and constitute by the logical circuit in the steering logic 114.This is not a limitation of the present invention just for illustrative purposes.Some variant according to present embodiment; Program code 112C comprises some program module/unit, and multiplexer 1142 and 1146, error correcting code demoder 1144, can implement through utilizing the microprocessor 112 of carrying out those program module/unit with at least a portion in the middle of the majority rule module 1148.For example: multiplexer 1142 and 1146, error correcting code demoder 1144, can implement through utilizing the microprocessor 112 of carrying out those program module/unit, and multiplexer 1142 and 1146, error correcting code demoder 1144, constitute by the logical circuit in the steering logic 114 with majority rule module 1148 central another part with the parts in the middle of the majority rule module 1148.Again for example: multiplexer 1142 and 1146, error correcting code demoder 1144, all can implement through utilizing the microprocessor 112 of carrying out those program module/unit with majority rule module 1148.
No matter this above-mentioned controller is designed to a certain framework (for example: multiplexer 1142 and 1146, error correcting code demoder 1144, can implement through utilizing the microprocessor 112 of carrying out those program module/unit with at least a portion of majority rule module 1148) in framework shown in Figure 1 (for example: multiplexer 1142 and 1146, error correcting code demoder 1144, be the part of steering logic 114 with majority rule module 1148) or those variant, can be used to reduce the memory storage 100 central mistakes that can't correct in addition about error correcting code through this controller of microprocessor 112 executive routine code 112C.Correlative detail please refer to Fig. 2 and further specifies.
Fig. 2 is that one embodiment of the invention a kind of is used for reducing in the middle of the memory storage process flow diagram about the method 910 of the mistake that can't correct of error correcting code.This method can be applicable to memory storage shown in Figure 1 100, especially above-mentioned controller (for example: through the Memory Controller 110 of microprocessor 112 executive routine code 112C).In addition, this method can be implemented through utilizing memory storage shown in Figure 1 100, especially through utilizing above-mentioned controller to implement.This method is explained as follows:
In step 912, this controller (especially the majority rule module 1148) is dependent on the data of the same address that homogeneous did not read and carries out majority rule, to produce the majority rule data corresponding to this address.For example, decoding error (that is, can't utilize the mistake of error correcting code corrigendum) takes place in this controller when reading the data of this address for the first time.So this controller is to the flash memory 120 employed threshold voltage (Read Threshold-Voltage) that reads when reading the data of this address with modification of giving an order.After the modification, this controller (for the second time) once more reads the data of this address.Yet, when reading the data of this address for the second time, decoding error also takes place.So this controller is given an order to flash memory 120 and is read threshold voltage to revise once more.After the modification, this controller reads the data of this address for the third time.Yet, when reading the data of this address for the third time, decoding error also takes place.Noting that above-mentioned reading times is merely the usefulness of explanation, is not the present invention's restriction.According to present embodiment, this controller employed threshold voltage (Read Threshold-Voltage) that reads when homogeneous does not read the data of this same address is not quite similar; Read under the situation that threshold voltage is not quite similar employed; Data in the same address that homogeneous did not read maybe be slightly variant; And majority rule module 1148 can carry out majority rule and replaces in the data of the same address that homogeneous was not read with the majority rule data that produce corresponding to this address, reduces in the middle of the memory storage 100 mistakes that can't correct about error correcting code by this.
In step 914, whether these these majority rule data of controller inspection have the mistake that can't correct, whether export the data of these majority rule data as this address with decision.For example: under the situation of the mistake that does not have in these majority rule data to correct, error correcting code demoder 1144 is notified this controller, so this controller just can be exported the data of these majority rule data as this address.Again for example: have under the situation of the mistake that can't correct in these majority rule data; Error correcting code demoder 1144 repayment decoding errors give this controller, so this controller carries out other running according to this such as the mistake sign of carrying out about the storage area at this place, address.
According to a special case of present embodiment, this controller can be temporary at least a portion in the middle of the data of this same address that homogeneous did not read respectively a plurality of buffer zone/impact dampers such as impact damper B (1) shown in Figure 1 and B (2).For example: this controller can be temporary in those buffer zone/impact dampers respectively with all data except last data in the middle of the data of this same address that homogeneous did not read earlier, and wherein these last data can just read in the process of carrying out this majority rule.Clearer and more definite; In the process of carrying out this majority rule; This controller last data in the middle of will the data of this same address that homogeneous did not read are temporary in first buffer zone/impact damper such as impact damper B (1) in those buffer zone/impact dampers, to take the up-to-date part that reads (for example at least one or byte) in the middle of the part of carrying out this majority rule (for example at least one position or byte) is substituted by these last data with up-to-date in the middle of this first buffer zone/impact damper.On the other hand; In the process of carrying out this majority rule; This controller is temporary in second buffer zone/impact damper in those buffer zone/impact dampers such as impact damper B (2) with these majority rule data, with up-to-date part (for example at least one position or byte) of taking up-to-date generation in the middle of the part of carrying out this majority rule (for example at least one position or byte) is substituted by these majority rule data in the middle of this second buffer zone/impact damper.For example, impact damper B (1) stores for the first time a memory page or leaf is read and a decoded page data, and impact damper B (2) stores for the second time this memory page or leaf is read and a decoded page data.When controller reads this memory page or leaf for the third time, also in proper order corresponding byte (or position) among impact damper B (1) and the B (2) is read, for example separately first byte among sense buffer B (1) and the B (2) respectively.Simultaneously; 1148 pairs of majority rule modules read from first byte of impact damper B (1), read from first byte of impact damper B (2) and first byte that reads gained for the third time and carry out majority rule, and the majority rule data that will carry out the majority rule gained are deposited back impact damper B (2).In addition, controller also will be deposited back impact damper B (1) to the data that this memory page or leaf reads gained for the third time simultaneously.Note that; Owing to reading to the first time, the second time of this memory page or leaf in the running after separately first byte read; Its occupied buffer space can discharge for its usefulness, so this controller can deposit read for the third time and decode first byte of back gained and the majority rule data of carrying out the majority rule gained respectively in impact damper B (1), the corresponding space of B (2).
Through above-mentioned running, the present invention can save the consumption of buffer zone/impact damper, and in the process that reads these last data, is ready for these last data and this majority rule data simultaneously for taking.Especially, when last data have read when finishing, majority rule module 1148 is almost accomplished the running of this majority rule simultaneously, and error correcting code demoder 1144 is almost accomplished the error correcting code decoding to these last data simultaneously.So; Under the situation of the mistake that does not have in these last data to correct; Error correcting code demoder 1144 is notified this controller; And this controller just can be immediately reads these last data and exports from this first buffer zone/impact damper such as impact damper B (1), can not lose time.In addition, have under the situation of the mistake that can't correct in these last data, error correcting code demoder 1144 just can be checked or error correction such as these majority rule data among the impact damper B (2) this second buffer zone/impact damper immediately; As long as these majority rule data do not have the mistake that can't correct, this controller just can read these majority rule data and exports in step 914 from this second buffer zone/impact damper such as impact damper B (2), can not lose time.Therefore, method of the present invention and relevant memory storage and controller thereof can provide splendid usefulness.
Note that the present invention can save the consumption of buffer zone/impact damper through above-mentioned running.This is not the restriction to the present invention just for illustrative purposes.Some variant according to present embodiment; Quantity and corresponding cost thereof at those buffer zone/impact dampers do not have under the situation of strict upper bound at the beginning of Memory Controller 110 designs, and this controller can be temporary in those buffer zone/impact dampers respectively with the data of this same address of being read each time.That is to say that when not being the primary matter of priority when reducing cost, the present invention does not get rid of and uses memory buffer 116 wastefully.
Fig. 3 is that method 910 shown in Figure 2 is in the implementation detail of an embodiment; The data of this same address that wherein homogeneous did not read described in the step 912 comprise the data D (1) that reads for the first time, the data D (2) that reads for the second time ..., with the data D (N) that reads for the N time, and the latter is above-mentioned last data.For the ease of understanding, present embodiment can explain that each element in the steering logic 114 wherein shown in Figure 1 and the data routing between the memory buffer 116 are not limited to only connect to impact damper B (1) and impact damper B (2) in the present embodiment with reference to framework shown in Figure 1.
According to present embodiment, the times N that this controller reads the data of this same address is an odd number.For example: Fig. 3 illustrates the situation of N=3.At this, the data D (1) that reads for the first time at first is temporary in impact damper B (1) shown in Figure 1, and error correcting code demoder 1144 can be checked or error correction the data D (1) among the impact damper B (1).Data D (1) reading for the first time has under the situation of the mistake that can't correct, and this controller is carried out workflow 920 shown in Figure 3.
In step 922, whether the data D (2) that this controller inspection is read for the second time has the mistake that can't correct.Especially, the data D (2) that reads for the second time is temporary in impact damper B (2) shown in Figure 1, and error correcting code demoder 1144 can be checked or error correction the data D (2) among the impact damper B (2).When detecting the data D (2) that reads for the second time when can't correct wrong arranged, then get into step 924; Otherwise, power cut-off flow process 920, the data D (2) that this this controller of expression reads the exportable second time is as the data of this address.
In step 924, whether the data D (3) that this controller inspection is read for the third time has the mistake that can't correct.Especially; The data D that reads for the third time (3) is temporary in another buffer zone/impact damper in the middle of the memory buffer 116 such as impact damper B (3) (not being illustrated in Fig. 1), and error correcting code demoder 1144 can be checked or error correction the data D (3) among the impact damper B (3).When detecting the data D (3) that reads for the third time when can't correct wrong arranged, then get into step 926; Otherwise, power cut-off flow process 920, this expression exportable data D that reads for the third time of this controller (3) is as the data of this address.
In step 926, this controller (especially the majority rule module 1148) carries out majority rule, with produce above-mentioned majority rule data for example majority rule data V (D (1), D (2) ..., D (N)); Under the situation of N=3, majority rule data V (D (1), D (2) ..., D (N)) and can be write as majority rule data V (D (1), D (2), D (3)).
In step 928, whether these these majority rule data of controller inspection have the mistake that can't correct.Especially; These majority rule data are temporary in another buffer zone/impact damper in the middle of the memory buffer 116 such as impact damper B (0) (not being illustrated in Fig. 1), and error correcting code demoder 1144 can be checked or error correction these majority rule data among the impact damper B (0).When detecting these majority rule data when can't correct wrong arranged, then get into step 930; Otherwise, power cut-off flow process 920, exportable these majority rule data of this this controller of expression are as the data of this address.
In step 930, error correcting code demoder 1144 repayment decoding errors give this controller.
Note that Fig. 3 illustrates step 9249
running separately.This is not a limitation of the present invention just for illustrative purposes.Such as above-mentioned special case, step 926 needn't be illustrated in Fig. 3 (in other words, step 926 can be incorporated into step 924) according to some variant of present embodiment.Especially; The data D that this controller will read in the process of carrying out this majority rule for the third time (3) is temporary in memory buffer 116 impact damper B (1), with the up-to-date up-to-date part that reads in the middle of the part of carrying out this majority rule (for example at least one position or byte) is substituted by data D (3) (for example at least one position or byte) of taking in the middle of impact damper B (1) original data D that is kept in (1).So error correcting code demoder 1144 can be checked or error correction the data D (3) among the impact damper B (1) in step 924.When detecting the data D (3) that reads for the third time when can't correct wrong arranged, then get into step 928; Otherwise, power cut-off flow process 920, this expression exportable data D that reads for the third time of this controller (3) is as the data of this address.On the other hand; In the process of carrying out this majority rule; This controller is temporary in impact damper B (2) with these majority rule data, with up-to-date part (for example at least one position or byte) of taking up-to-date generation in the middle of the part of carrying out this majority rule (for example at least one position or byte) is substituted by these majority rule data in the middle of impact damper B (2) original data D that kept in (2).So error correcting code demoder 1144 can be checked or error correction these majority rule data among the impact damper B (2) in step 928.
In addition, Fig. 3 illustrates the situation of N=3.This is not the restriction to the present invention just for illustrative purposes.According to present embodiment; Under the situation of N＞3; Step 922 to step 924 desirable on behalf of a row step such as step 922-2, step 922-3 ..., with step 922-N, be used for respectively checking the data D (2) that reads for the second time, the data D (3) that reads for the third time ..., with the data D (N) that reads for the N time whether the mistake that can't correct is arranged.
Fig. 4 is illustrated in the synoptic diagram of the related majority rule of method shown in Figure 2 among the embodiment 910, and wherein present embodiment is a special case embodiment illustrated in fig. 3.At this, except position Bit (x), Bit (y), with Bit (z), data D (1), D (2), mutually the same with D (3).As shown in Figure 4, each position of majority rule data V (D (1), D (2), D (3)) meet respectively data D (1), D (2), with corresponding the majority rule result of D (3).For example: data D (1), D (2), be 1 with first Bit (1) of D (3), so first Bit (1) of majority rule data V (D (1), D (2), D (3)) is 1.Again for example: data D (1), D (2), be respectively 1,0 with x the position Bit (x) of D (3), and 1, it can abbreviate set { 1,0 as; 1}, and majority rule data V (D (1), D (2); D (3)) x position Bit (x) then for set 1,0, numerical value " 1 " the most repeatedly appears among the 1}; Similarly, majority rule data V (D (1), D (2); D (3)) y position Bit (y) be data D (1), D (2), with y the formed set of Bit (y) of D (3) 1,0, appearance numerical value " 0 " the most repeatedly among the 0}; And z of majority rule data V (D (1), D (2), D (3)) position Bit (z) then be data D (1), D (2), with z the formed set of Bit (z) { 0 of D (3); 0, numerical value " 0 " the most repeatedly appears among the 1}.
One of benefit of the present invention is that the present invention can reduce the central mistake that can't correct about error correcting code of memory storage.In addition, the present invention can take into account operational effectiveness and system resource and use keyholed back plate, and the problem that does not have a correlation technique such as with some block errors be denoted as bad block.In addition; Preferred embodiment of the present invention can be saved the consumption of buffer zone/impact damper; And in the process that reads these last data, be ready for these last data and this majority rule data simultaneously for taking, so method of the present invention and relevant memory storage and controller thereof can provide splendid usefulness.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (5)
1. method that is used for reducing the mistake that can't correct, those mistakes that can't correct be in the middle of the memory storage about the mistake that can't correct of error correcting code, it is characterized in that this method includes:
The data that are dependent on the same address that homogeneous did not read are carried out majority rule, to produce the majority rule data corresponding to this address; And
Check whether these majority rule data have the mistake that can't correct, whether export the data of these majority rule data as this address with decision;
This method includes in addition:
At least a portion in the middle of the data of this same address that homogeneous did not read is temporary in a plurality of buffer zone/impact dampers respectively;
All data except last data in the middle of the data of this same address that homogeneous did not read are temporary in those buffer zone/impact dampers respectively;
In the process of carrying out this majority rule; Last data in the middle of the data of this same address that homogeneous did not read are temporary in the first buffer zone/impact damper in those buffer zone/impact dampers, to take the up-to-date part that reads in the middle of the part of carrying out this majority rule is substituted by these last data with up-to-date in the middle of this first buffer zone/impact damper;
In the process of carrying out this majority rule; These majority rule data are temporary in the second buffer zone/impact damper in those buffer zone/impact dampers, with up-to-date part of taking up-to-date generation in the middle of the part of carrying out this majority rule is substituted by these majority rule data in the middle of this second buffer zone/impact damper.
2. method according to claim 1 is characterized in that, the number of times that wherein reads the data of this same address is an odd number.
3. method according to claim 1 is characterized in that, wherein the employed threshold voltage that reads is not quite similar when homogeneous does not read the data of this same address.
4. a memory storage is characterized in that, includes:
One flash memory, this flash memory comprises a plurality of blocks; And
One controller is used for this flash memory of access and management this a plurality of blocks, and is used for reducing the central mistake that can't correct about error correcting code of this memory storage in addition;
Wherein this controller data of being dependent on the same address that homogeneous did not read are carried out majority rule, to produce the majority rule data corresponding to this address; And this controller checks whether these majority rule data have the mistake that can't correct, whether export the data of these majority rule data as this address with decision;
Wherein this controller is temporary in a plurality of buffer zone/impact dampers respectively with at least a portion in the middle of the data of this same address that homogeneous did not read;
Wherein this controller is temporary in those buffer zone/impact dampers respectively with all data except last data in the middle of the data of this same address that homogeneous did not read;
Wherein in the process of carrying out this majority rule; This controller will this same address that homogeneous did not read the central last data of data be temporary in the first buffer zone/impact damper in those buffer zone/impact dampers, to take the up-to-date part that reads in the middle of the part of carrying out this majority rule is substituted by these last data with up-to-date in the middle of this first buffer zone/impact damper;
Wherein in the process of carrying out this majority rule; This controller is temporary in the second buffer zone/impact damper in those buffer zone/impact dampers with these majority rule data, with up-to-date part of taking up-to-date generation in the middle of the part of carrying out this majority rule is substituted by these majority rule data in the middle of this second buffer zone/impact damper.
5. the controller of a memory storage, this controller are used for the flash memory in this memory storage of access, and this flash memory comprises a plurality of blocks, it is characterized in that, this controller includes:
One ROM (read-only memory) is used for storing a program code; And
One microprocessor; Be used for carrying out this program code with control access and management this a plurality of blocks to this flash memory, wherein this controller through this this program code of microprocessor execution is used for reducing in the middle of this memory storage the mistake that can't correct about error correcting code in addition;
Wherein this controller data of being dependent on the same address that homogeneous did not read are carried out majority rule, to produce the majority rule data corresponding to this address; And this controller checks whether these majority rule data have the mistake that can't correct, whether export the data of these majority rule data as this address with decision;
Wherein this controller is temporary in a plurality of buffer zone/impact dampers respectively with at least a portion in the middle of the data of this same address that homogeneous did not read;
Wherein this controller is temporary in those buffer zone/impact dampers respectively with all data except last data in the middle of the data of this same address that homogeneous did not read;
Wherein in the process of carrying out this majority rule; This controller will this same address that homogeneous did not read the central last data of data be temporary in the first buffer zone/impact damper in those buffer zone/impact dampers, to take the up-to-date part that reads in the middle of the part of carrying out this majority rule is substituted by these last data with up-to-date in the middle of this first buffer zone/impact damper;
Wherein in the process of carrying out this majority rule; This controller is temporary in the second buffer zone/impact damper in those buffer zone/impact dampers with these majority rule data, with up-to-date part of taking up-to-date generation in the middle of the part of carrying out this majority rule is substituted by these majority rule data in the middle of this second buffer zone/impact damper.
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| CN 201010121050 CN102141944B (en) | 2010-02-02 | 2010-02-02 | Method for reducing errors incapable of being corrected, memory device and controller thereof |
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| JP5586666B2 (en) * | 2012-08-01 | 2014-09-10 | 力晶科技股▲ふん▼有限公司 | Nonvolatile semiconductor memory device and reading method thereof |
| JP5870901B2 (en) * | 2012-11-02 | 2016-03-01 | ソニー株式会社 | Error detection and correction device, mismatch detection device, memory system, and error detection and correction method |
| CN108038016B (en) * | 2017-12-22 | 2021-01-01 | 湖南国科微电子股份有限公司 | Solid state disk error data processing method and device |
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| CN1259213A (en) * | 1997-06-06 | 2000-07-05 | 艾利森电话股份有限公司 | A hardware design for majority voting, and testing and maintenance of majority voting |
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| CN1259213A (en) * | 1997-06-06 | 2000-07-05 | 艾利森电话股份有限公司 | A hardware design for majority voting, and testing and maintenance of majority voting |
| CN1230824A (en) * | 1998-03-31 | 1999-10-06 | 京都陶瓷株式会社 | Acknowledgment message receiving method |
| CN1640172A (en) * | 2002-07-09 | 2005-07-13 | 富士通株式会社 | Communication system, transmitter/receiver, and transmitting/receiving method |
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