CN102137220B - Addressing method of Line Buffer and chip - Google Patents
Addressing method of Line Buffer and chip Download PDFInfo
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- CN102137220B CN102137220B CN 201010531754 CN201010531754A CN102137220B CN 102137220 B CN102137220 B CN 102137220B CN 201010531754 CN201010531754 CN 201010531754 CN 201010531754 A CN201010531754 A CN 201010531754A CN 102137220 B CN102137220 B CN 102137220B
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Abstract
The embodiment of the invention provides an addressing method of a Line Buffer and a chip, relating to the electronic field. Addition and subtraction during addressing in the prior art are abandoned, rapid addressing can be achieved, and the problem of addressing cross-border of the Line Buffer is better solved. A method for solving the problem comprises the following steps of: indicating the Line Buffer of the current working line by using an indicating bit in a first cycle shift register, after the result y of a motion vector Y is obtained, circularly shifting the indicating bit of the first cycle shift register by y bits to obtain the indicating bit of a second cycle shift register; and indicating the Line Buffer of the addressing line by the indicating bit in the second cycle shift register. The embodiment of the invention is used in Line Buffer addressing.
Description
Technical field
The present invention relates to electronic applications, relate in particular to a kind of Line Buffer (line buffer) addressing method and chip.
Background technology
In video frequency processing chip; often can need to realize motion compensation or other similar algorithms; these algorithms have a common operation be exactly according to the motion vector that calculates in the several rows of the front and back of the current line of image, find the view data of certain delegation to carry out computing.
Suppose that current line is that the N of image is capable, the form of motion vector is (X, Y), owing to adopt Line Buffer (line buffer), the X span is as long as in Line Buffer is capable, and how many bar Line Buffer are the scope of Y determined to need to adopt.If the span of Y is that (we need 2m+1 bar Line Buffer to store the capable data of the upper and lower m of current line so for m, m.
Traditional Line Buffer addressing method is that a log is set
2(2m+1) position counter (address of article one Line Buffer is 0, and second is 1 ... the like), simultaneously, a register LineBuffer_Indx_Reg is set, and to write down current be at which Line Buffer to operate.Like this, if calculate motion vector for (X, Y), can obtain wanting with LineBuffer_Indx_Reg+Y the address of the LineBuffer of addressing.
The inventor finds, a shortcoming of this method of prior art is, use add, subtraction, when LineBuffer is more, during such as tens, can cause sequential nervous.Because motion vector often will if the addition spended time is too many, then can not produce Line Buffer read signal at present clock period through complicated calculating, must wait until the next clock cycle.
Another shortcoming is, because Line Buffer is loopy moving, prior art adopts the fixed address addressing also will consider the address out of range problem, and judges that address out of range bothers very much, and this will be so that circuit scale be larger, and sequential is more bad.
Summary of the invention
Embodiments of the invention provide a kind of Line Buffer addressing method and chip, and adding when having abandoned addressing in the prior art, subtraction can be realized immediate addressing, have also solved preferably the problem that Line Buffer addressing is crossed the border.
On the one hand, provide a kind of Line Buffer addressing method, the span of establishing motion vector Y is that (m, m) m is the integer greater than 0, and then the line number of Line Buffer is 2m+1, and described Line Buffer addressing method comprises:
Line Buffer with the indication of the indicating bit in the first circulating register work at present row; Described the first circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference;
The result who obtains motion vector Y is y, behind the y ∈ (m, m), the indicating bit cyclic shift y position in described the first circulating register is obtained indicating bit in the second circulating register; Wherein, when the as a result y of the motion vector Y that obtains on the occasion of the time, the indicating bit in described the first circulating register is obtained indicating bit in described the second circulating register to first direction cyclic shift y position; When the as a result y of the motion vector Y that obtains is negative value, the indicating bit in described the first circulating register is obtained indicating bit in described the second circulating register to second direction cyclic shift y position;
The Line Buffer of the indicating bit indication addressed row in described the second circulating register; Described the second circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference.
On the other hand, provide a kind of Line Buffer addressing chip, the span of establishing motion vector Y is that (m, m) m is the integer greater than 0, and then the line number of Line Buffer is 2m+1, and described chip comprises:
The first circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference, and its indicating bit is used to indicate the Line Buffer of work at present row;
The second circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference, and its indicating bit is used to indicate the Line Buffer of addressed row;
Barrel shifter, the result who obtains motion vector Y is y, behind the y ∈ (m, m), is used for indicating bit cyclic shift y position with described the first circulating register and obtains indicating bit in described the second circulating register; Wherein, when the as a result y of the described motion vector Y that obtains on the occasion of the time, described barrel shifter obtains indicating bit in described the second circulating register with the indicating bit in described the first circulating register to first direction cyclic shift y position; When the as a result y of the described motion vector Y that obtains was negative value, described barrel shifter obtained indicating bit in described the second circulating register with the indicating bit in described the first circulating register to second direction cyclic shift y position.
Line Buffer addressing method and chip that the embodiment of the invention provides, Line Buffer with the indication of the indicating bit in the first circulating register work at present row, after the result who obtains motion vector Y is y, the indicating bit cyclic shift y position of the first circulating register is obtained the indicating bit of the second circulating register, and indicate the Line Buffer of addressed row with the indicating bit in this second circulating register.Thereby adding when having abandoned addressing in the prior art, subtraction, can not cause because of the sequential that adds, subtraction causes nervous.And owing to adopted circulating register indication Line Buffer, the loopy moving of corresponding LineBuffer has been avoided in the prior art because the address out of range problem that the fixed address addressing causes better.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The FB(flow block) of the Line Buffer addressing method that Fig. 1 provides for the embodiment of the invention;
The structural representation of the principle of the Line Buffer addressing method that Fig. 2 provides for the embodiment of the invention;
The structural representation of another principle of the Line Buffer addressing method that Fig. 3 provides for the embodiment of the invention;
The structural representation block diagram of the Line Buffer addressing chip that Fig. 4 provides for the embodiment of the invention;
The structural representation block diagram of another Line Buffer addressing chip that Fig. 5 provides for the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The embodiment of the invention provides a kind of Line Buffer addressing method, and the span of establishing motion vector Y is that (m, m) m is the integer greater than 0, and then the line number of Line Buffer is 2m+1, and as shown in Figure 1, this Line Buffer addressing method comprises:
S101, with the Line Buffer of the indicating bit in the first circulating register indication work at present row, this first circulating register comprises the 2m+1 position, and each corresponding Line Buffer of delegation respectively.
S102, the result who obtains motion vector Y are y, behind the y ∈ (m, m), the indicating bit cyclic shift y position in the first circulating register are obtained indicating bit in the second circulating register.
Concrete, when the as a result y of the motion vector Y that obtains on the occasion of the time, with the indicating bit in the first circulating register to first direction, right for example, cyclic shift y position obtains the indicating bit in the second circulating register; When the as a result y of the motion vector Y that obtains is negative value, with the indicating bit in the first circulating register to second direction, for example left to, cyclic shift y position obtains the indicating bit in the second circulating register.
The Line Buffer of the indicating bit indication addressed row in S103, the second circulating register, this second circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference.
The Line Buffer addressing method that the embodiment of the invention provides, Line Buffer with the indication of the indicating bit in the first circulating register work at present row, after the result who obtains motion vector Y is y, the indicating bit cyclic shift y position of the first circulating register is obtained the indicating bit of the second circulating register, and indicate the Line Buffer of addressed row with the indicating bit in this second circulating register.Thereby adding when having abandoned addressing in the prior art, subtraction, can not cause because of the sequential that adds, subtraction causes nervous.And owing to adopted circulating register indication Line Buffer, the loopy moving of corresponding Line Buffer has been avoided in the prior art because the address out of range problem that the fixed address addressing causes better.
The Line Buffer addressing method that another embodiment of the present invention provides, the structure of its principle as shown in Figure 2.
In Fig. 2, suppose that the span of motion vector Y is (4,4), therefore, the line number of Line Buffer is 2 * 4+1=9, uses this 9 row of Line Buffer 0～Line Buffer 8 index Line Buffer in Fig. 2.Also be provided with the first circulating register 10 and the second circulating register 11 in the present embodiment, and barrel shifter 12 and motion vector computation unit 13.
Wherein, the line number of the first circulating register 10 corresponding Line Buffer has 2 * 4+1=9 position, and the corresponding Line Buffer of delegation of each difference.In the present embodiment, each of this first circulating register 10 can be made as 1 bit, and with these 9 of bit 0～bit 8 index.Preferably, everybody of the first circulating register 10 can corresponding each the row Line Buffer of order, i.e. bit 0 corresponding Line Buffer 0, and the corresponding Line Buffer1 of bit1 ..., bit 8 corresponding Line Buffer 8.
In the first circulating register 10, indicating bit can be indicated with "True" the LineBuffer of work at present row, and everybody is " vacation " for all the other.For example, in Fig. 2, indicating bit can " 1 " be indicated the Line Buffer of work at present row, and everybody is " 0 " for all the other; Can certainly be conversely, with the Line Buffer of " 0 " indication work at present row, everybody is " 1 " for all the other, and this is restriction not.
The line number of the second circulating register 11 corresponding Line Buffer has 2 * 4+1=9 position, and the corresponding Line Buffer of delegation of each difference.In the present embodiment, each of this second circulating register 11 can be made as 1 bit, and with these 9 of bit 0～bit 8 index.Preferably, everybody of the second circulating register 11 can corresponding each the row Line Buffer of order, i.e. bit 0 corresponding Line Buffer 0, and bit 1 corresponding Line Buffer1 ..., bit 8 corresponding Line Buffer 8.
In the second circulating register 11, indicating bit can be indicated with "True" the Line Buffer of addressed row, and everybody is " vacation " for all the other.For example, in Fig. 2, indicating bit can " 1 " be indicated the Line Buffer of addressed row, and everybody is " 0 " for all the other; Can certainly be conversely, with the Line Buffer of " 0 " indication addressed row, everybody is " 1 " for all the other, and this is restriction not.
Motion vector computation unit 13 is used for calculating kinematical vector (X, Y), and the as a result y (y ∈ (4,4)) of the motion vector Y that obtains is sent to barrel shifter 12; Barrel shifter 12 can be adjusted the first circulating register 10 to realize Line Buffer addressing according to the value of this y.
Concrete Line Buffer addressing process is as follows:
Suppose that current line is that the N of a frame data image is capable, because the span of motion vector Y is (4,4), so, must there be 4 row Line Buffer to store the view data of the capable 4 top row N-4 of N, N-3, N-2, N-1.In addition, also must there be other 4 row Line Buffer to store the view data of the capable 4 following row N+1 of N, N+2, N+3, N+4.
In Fig. 2, Line Buffer 4 expression work at present row, the upper row of Line Buffer 0～Line Buffer 3 expression current lines, the following row of Line Buffer 5～Line Buffer 8 expression current lines.
According to corresponding relation described above, in the first circulating register 10, bit 4 is indicating bit, and its value is " 1 ", and expression work at present row is stored among the Line Buffer 4, and current line is that the N of current image frame is capable.
When Current Datarow is processed, the view data of going arbitrarily in 4 row about may needing.Motion vector computation unit 13 calculates motion vector (X, Y), if the result of motion vector Y is 3 (3 ∈ (4,4)), means that then the data of wanting addressing are following the third lines of current line.In the present embodiment, the result 3 of motion vector Y can send to barrel shifter 12, and barrel shifter 12 moves right 3 with the indicating bit of the first circulating register 10, obtains the indicating bit of the second circulating register 11.In Fig. 2, the indicating bit bit 4 of the first circulating register 10 moves right 3 and obtains the indicating bit bit 7 of the second circulating register 11.
The bit 7 of the second circulating register 11 is indicating bit, and its value is " 1 ", and expression bit 7 corresponding Line Buffer 7 are for wanting the Line Buffer of addressing.Can see obviously that from Fig. 2 the row that Line Buffer 7 refers to namely is the third line below the current line.
Like this, the embodiment of the invention is with the Line Buffer of the indication of the indicating bit in the first circulating register work at present row, after the result who obtains motion vector Y is y, the indicating bit cyclic shift y position of the first circulating register is obtained the indicating bit of the second circulating register, and indicate the Line Buffer of addressed row with the indicating bit in this second circulating register.Thereby adding when having abandoned addressing in the prior art, subtraction can not cause because of the sequential that adds, subtraction causes nervously, and can make circuit faster.
After all data that N is capable are over the ground all finished dealing with, next it is capable to process N+1, at this moment, it is capable that current line is N+1, therefore, fifth line above N is capable, the data that namely N-4 is capable have not needed, and can take out in advance the Line Buffer (Line Buffer 0) that the capable data of N+5 are put into the original capable place of N-4 from system storage (memory).
Describe with reference to Fig. 3, after Line Buffer 4 processing of bit 4 indications of former the first circulating register 10 finished, indicating bit moved right one, and namely bit 5 is new indicating bit, its value is " 1 ", represents that present current line is that the capable data of N+1 are stored among the Line Buffer 5.Suppose that the result of the motion vector Y that calculates is 4 (4 ∈ (4,4)), means that then the data of wanting addressing are following fourth lines of current line when processing N+1 is capable.In the present embodiment, the result 4 of motion vector Y can send to barrel shifter 12, and barrel shifter 12 moves right 4 with the indicating bit of the first circulating register 10, obtains the indicating bit of the second circulating register 11.In Fig. 3, the indicating bit bit 5 of the first circulating register 10 moves right 4 and obtains the indicating bit bit 0 of the second circulating register 11.
The bit 0 of the second circulating register 11 is indicating bit, and its value is " 1 ", and expression bit 0 corresponding Line Buffer 0 is for wanting the Line Buffer of addressing.Can see obviously that from Fig. 3 the data of the row storage that Line Buffer 0 refers to namely are the fourth line data below the current line.
For prior art, the represented situation of Fig. 3 namely is a kind of crossing the border, because the address of LineBuffer of wanting addressing is less than the address of the Line Buffer of work at present row.And in the present embodiment, evaded the judgement that addressing is crossed the border to Line Buffer by the method for cyclic shift.Thereby so that circuit logic is simple, computing is faster.
In addition, in the present embodiment, the result of the motion vector Y that exemplifies is on the occasion of, circulating register circulation right shift; When the result of motion vector Y was negative value, circulating register circulated to shifting left.
The Line Buffer addressing chip that the embodiment of the invention provides, the span of establishing motion vector Y are that (m, m) m is the integer greater than 0, and then the line number of Line Buffer is 2m+1, and as shown in Figure 4, this chip 40 comprises:
The first circulating register 10 comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference, and its indicating bit is used to indicate the Line Buffer of work at present row.
The second circulating register 11 comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference, and its indicating bit is used to indicate the Line Buffer of addressed row.
The Line Buffer addressing chip that the embodiment of the invention provides, Line Buffer with the indication of the indicating bit in the first circulating register work at present row, after the result who obtains motion vector Y is y, the indicating bit cyclic shift y position of the first circulating register is obtained the indicating bit of the second circulating register, and indicate the Line Buffer of addressed row with the indicating bit in this second circulating register.Thereby adding when having abandoned addressing in the prior art, subtraction, can not cause because of the sequential that adds, subtraction causes nervous.And owing to adopted circulating register indication Line Buffer, the loopy moving of corresponding Line Buffer has been avoided in the prior art because the address out of range problem that the fixed address addressing causes better.
Further, as shown in Figure 5, this Line Buffer addressing chip 40 also comprises:
Motion vector computation unit 13 is used for calculating kinematical vector (X, Y), and the as a result y of motion vector Y is sent to barrel shifter 12.
In addition, corresponding each row Line Buffer of everybody order of the first circulating register 10; Corresponding each row Line Buffer of everybody order of the second circulating register 11.
Each of the first circulating register 10 is 1 bit; Each of the second circulating register 11 is 1 bit.
When the as a result y of the motion vector Y that obtains on the occasion of the time, barrel shifter 12 with the indicating bit in the first circulating register 10 to first direction, right for example, cyclic shift y position obtains the indicating bit in the second circulating register 11; When the as a result y of the motion vector Y that obtains is negative value, barrel shifter 12 with the indicating bit in the first circulating register 10 to second direction, for example left to, cyclic shift y position obtains the indicating bit in the second circulating register 11.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of program command, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (8)
1. Line Buffer addressing method, the span of establishing motion vector Y for (m, m) m for greater than 0 integer, then the line number of Line Buffer is 2m+1, it is characterized in that, described Line Buffer addressing method comprises:
Line Buffer with the indication of the indicating bit in the first circulating register work at present row; Described the first circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference;
The result who obtains motion vector Y is y, behind the y ∈ (m, m), the indicating bit cyclic shift y position in described the first circulating register is obtained indicating bit in the second circulating register; Wherein, when the as a result y of the motion vector Y that obtains on the occasion of the time, the indicating bit in described the first circulating register is obtained indicating bit in described the second circulating register to first direction cyclic shift y position; When the as a result y of the motion vector Y that obtains is negative value, the indicating bit in described the first circulating register is obtained indicating bit in described the second circulating register to second direction cyclic shift y position;
The Line Buffer of the indicating bit indication addressed row in described the second circulating register; Described the second circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference.
2. Line Buffer addressing method according to claim 1 is characterized in that,
Corresponding each row Line Buffer of everybody order of described the first circulating register;
Corresponding each row Line Buffer of everybody order of described the second circulating register.
3. Line Buffer addressing method according to claim 1 and 2 is characterized in that,
Each of described the first circulating register is 1 bit;
Each of described the second circulating register is 1 bit.
4. Line Buffer addressing method according to claim 3 is characterized in that,
The indicating bit of described the first circulating register is with the Line Buffer of "True" indication work at present row, and everybody is " vacation " for all the other;
The indicating bit of described the second circulating register is with the Line Buffer of "True" indication addressed row, and everybody is " vacation " for all the other.
5. Line Buffer addressing chip, the span of establishing motion vector Y for (m, m) m for greater than 0 integer, then the line number of Line Buffer is 2m+1, it is characterized in that, described chip comprises:
The first circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference, and its indicating bit is used to indicate the Line Buffer of work at present row;
The second circulating register comprises the 2m+1 position, and the corresponding Line Buffer of delegation of each difference, and its indicating bit is used to indicate the Line Buffer of addressed row;
Barrel shifter, the result who obtains motion vector Y is y, behind the y ∈ (m, m), is used for indicating bit cyclic shift y position with described the first circulating register and obtains indicating bit in described the second circulating register; Wherein, when the as a result y of the described motion vector Y that obtains on the occasion of the time, described barrel shifter obtains indicating bit in described the second circulating register with the indicating bit in described the first circulating register to first direction cyclic shift y position; When the as a result y of the described motion vector Y that obtains was negative value, described barrel shifter obtained indicating bit in described the second circulating register with the indicating bit in described the first circulating register to second direction cyclic shift y position.
6. Line Buffer addressing chip according to claim 5 is characterized in that, described Line Buffer addressing chip also comprises:
The motion vector computation unit is used for calculating kinematical vector (X, Y), and the as a result y of described motion vector Y is sent to described barrel shifter.
7. according to claim 5 or 6 described Line Buffer addressing chips, it is characterized in that,
Corresponding each row Line Buffer of everybody order of described the first circulating register;
Corresponding each row Line Buffer of everybody order of described the second circulating register.
8. according to claim 5 or 6 described Line Buffer addressing chips, it is characterized in that,
Each of described the first circulating register is 1 bit;
Each of described the second circulating register is 1 bit.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0505051A1 (en) * | 1991-03-19 | 1992-09-23 | National Semiconductor Corporation | Data storage system with intrinsic burst detection |
| EP1162535A2 (en) * | 2000-05-24 | 2001-12-12 | Texas Instruments Incorporated | Method for executing data operations and assembly for same |
| CN1589029A (en) * | 2004-07-29 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Reference storage device and method based on line buffer in video decoding chip |
| CN1734495A (en) * | 2004-05-06 | 2006-02-15 | 佳能株式会社 | Image information processing circuit and image display apparatus |
| TW200832219A (en) * | 2006-09-18 | 2008-08-01 | Nat Semiconductor Corp | Methods and systems for efficiently storing and retrieving streaming data |
-
2010
- 2010-11-04 CN CN 201010531754 patent/CN102137220B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0505051A1 (en) * | 1991-03-19 | 1992-09-23 | National Semiconductor Corporation | Data storage system with intrinsic burst detection |
| EP1162535A2 (en) * | 2000-05-24 | 2001-12-12 | Texas Instruments Incorporated | Method for executing data operations and assembly for same |
| CN1734495A (en) * | 2004-05-06 | 2006-02-15 | 佳能株式会社 | Image information processing circuit and image display apparatus |
| CN1589029A (en) * | 2004-07-29 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Reference storage device and method based on line buffer in video decoding chip |
| TW200832219A (en) * | 2006-09-18 | 2008-08-01 | Nat Semiconductor Corp | Methods and systems for efficiently storing and retrieving streaming data |
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Effective date of registration: 20160721 Address after: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee after: Qingdao Hisense Electric Co., Ltd. Address before: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee before: Qingdao Hisense Xinxin Technology Co., Ltd. |
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Address after: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee after: Hisense Video Technology Co.,Ltd. Address before: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee before: HISENSE ELECTRIC Co.,Ltd. |
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