CN102136450A - Method for forming metal interconnection - Google Patents
Method for forming metal interconnection Download PDFInfo
- Publication number
- CN102136450A CN102136450A CN201010102401XA CN201010102401A CN102136450A CN 102136450 A CN102136450 A CN 102136450A CN 201010102401X A CN201010102401X A CN 201010102401XA CN 201010102401 A CN201010102401 A CN 201010102401A CN 102136450 A CN102136450 A CN 102136450A
- Authority
- CN
- China
- Prior art keywords
- layer
- copper
- annealing
- dielectric layer
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for forming metal interconnection of a semiconductor device. The method comprises the following steps: depositing an inter-layer dielectric layer on a front end device layer; forming a metal interconnection layer on the inter-layer dielectric layer; performing chemical mechanical grinding on the metal interconnection layer; and annealing the metal interconnection layer. According to the process provided by the invention, holes in metal interconnection can be effectively reduced, and the yield rate in production can be improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly form the method for copper interconnection structure.
Background technology
Along with the making of integrated circuit to very lagre scale integrated circuit (VLSIC) (ULSI) development, its inner current densities is increasing, contained number of elements constantly increases, and makes the surface of wafer can't provide enough areas to make required interconnection line.For co-operating member dwindles the interconnection line demand that increased of back, utilize the design of the two-layer above multiple layer metal interconnection line that groove realizes, become the method that very large scale integration technology institute must employing.
Traditional metal interconnectedly realize by aluminium, but along with constantly the dwindling of device feature size in the integrated circuit (IC) chip, the current density in the metal connecting line constantly increases, the response time constantly shortens, and the conventional aluminum interconnection line has reached technological limits.After process was less than 130nm, traditional aluminum interconnecting technology was replaced by the copper interconnecting line technology gradually.With the aluminum metallic matrix ratio, the resistivity of copper metal is lower, electromigration lifetime is longer, utilizes process for copper to make RC that metal interconnecting wires can reduce interconnection line and postpones, improves the integrity problem that electromigration etc. causes.
Fig. 1 is the flow chart that prior art forms copper interconnection structure.As shown in Figure 1, in step 101, make semiconductor device, for example deposited interlayer dielectric layer on the front end device layer of MOS transistor; In step 102, on this interlayer dielectric layer, make groove/through-hole pattern by lithography, and etching forms groove/through hole; In step 103, be the copper metal that makes filling and the dielectric layer good adhesion of groove/through-hole side wall, and prevent that the copper metal from spreading in dielectric layer, before filling metal, deposit one deck adhesion layer earlier, this adhesion layer can be formed by the Ta/TaN composition usually, then forms the crystal seed layer of copper on adhesion layer with methods such as physical vapour deposition (PVD)s; In step 104, in electroplating chamber, utilize electric plating method in groove/through hole, to fill the copper metal, form the copper layer; In step 105, the copper layer is carried out annealing in process, so that the copper layer has the good character such as Low ESR and high stability; In step 106, remove the part that metal level exceeds interlayer dielectric layer in cmp (CMP) mode, thereby finish copper interconnection structure; In step 107, the surface behind CMP forms the dielectric layer of one deck down with the method for chemical vapor deposition (CVD).
In order to make the copper layer have good electric property and long life-span, behind plated film, carried out annealing in process, yet annealing process can increase the stress of copper layer.After the aforesaid processing step 105 that metal level is carried out annealing in process, and etc. may exist the very long stand-by period (to be also referred to as queuing time, Q-time) between the step 106 of pending CMP.In the wait process, stress gradient can be impelled room diffusion, the nucleation in the interconnection line and grow into the cavity, thereby causes the interconnection resistance increase even cause the interconnection line fracture.Stress migration lost efficacy and mostly occurred in through hole and iso-stress concentrated area, metal connecting line edge.Fig. 2 for annealing before and the stress of annealing back copper layer with the change curve of copper layer thickness.As shown in Figure 2, the stress of copper layer can significantly improve after annealing, and film is thin more, and the influence of annealing counter stress is big more.Fig. 2 is the stand-by period greater than the SEM photo of copper laminar surface after 5 hours.As shown in Figure 3, in groove 301, have bigger cavity 302 on the edge of copper layer.These bigger cavities can reduce the electrical connection characteristic and the mechanical property of copper interconnection structure, thereby reduce the life-span and the yields of copper-connection.
Therefore, when having the long stand-by period between annealing in process and cmp, the metal cavity of reducing in the interconnection structure becomes most important.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
For solving the empty problem in metal interconnected, improve the yields of explained hereafter, the invention provides a kind of metal interconnected method that forms, described method comprises: deposit interlayer dielectric layer on the front end device layer; On described interlayer dielectric layer, form metal interconnecting layer; Described metal interconnecting layer is carried out cmp; Described metal interconnecting layer is annealed.
According to a further aspect in the invention, described method also is included in after the annealing steps dielectric layer on described metal interconnecting layer.
According to a further aspect in the invention, wherein said metal interconnecting layer is the copper layer.
According to a further aspect in the invention, wherein utilize electro-plating method to form described copper layer.
According to a further aspect in the invention, wherein said annealing steps carries out in annealing device.
According to a further aspect in the invention, wherein said annealing steps carries out in the reaction chamber that forms described dielectric layer.
According to a further aspect in the invention, wherein when carrying out, described annealing steps feeds in nitrogen, helium or the argon gas one or more as protective gas.
According to a further aspect in the invention, wherein annealing temperature is 300～400 ℃, and temperature retention time is 45～60s.
According to a further aspect in the invention, wherein the flow velocity of helium is 60～100sccm, and the flow velocity of nitrogen is 1000～1500sccm.
Can effectively solve the problem that behind cmp, stays the cavity according to manufacturing process of the present invention on the metal interconnect structure surface.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the flow chart that prior art forms copper interconnection structure;
Fig. 2 is the change curve of the stress of before the annealing and annealing back copper layer with copper layer thickness;
Fig. 3 is the stand-by period greater than the SEM photo of copper laminar surface after 5 hours;
Fig. 4 is the flow chart that forms copper interconnection structure according to one embodiment of the invention;
Fig. 5 is the flow chart that forms copper interconnection structure according to a further embodiment of the invention;
Fig. 6 is the cumulative distribution function curve according to the puncture voltage of the copper interconnection structure of traditional handicraft and technology of the present invention formation.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, the processing step of good copper interconnection structure formed according to the present invention is described, so that solve the back stays the metal cavity in groove surfaces the problem of grinding.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution mode.
In order to overcome problems of the prior art, the present invention proposes the technology integrating method that is used to reduce the metal cavity.This method can reduce when having the long stand-by period between annealing in process and cmp, owing to the caused metal of the stress cavity of annealing and increasing.Metal interconnect structure formed according to the present invention has higher puncture voltage and long life-span.
Fig. 4 is the process chart that forms copper interconnection structure according to one embodiment of the invention.
In step 401, made semiconductor device, for example deposit interlayer dielectric layer on the front end device layer of MOS transistor.The material of this interlayer dielectric layer can be a silicon nitride etc.
In step 402, on this interlayer dielectric layer, apply antireflecting coating and photoresist successively, form photoresist layer through technologies such as exposure, developments then with groove/through-hole pattern, be that mask etching forms groove/through hole with this photoresist layer.
In step 403, be the copper metal that makes filling and the interlayer dielectric layer good adhesion of groove/through-hole side wall, and prevent that the copper metal from spreading in interlayer dielectric layer, before filling metal, deposit one deck adhesion layer earlier, this adhesion layer can be formed by the Ta/TaN composition usually, then forms the crystal seed layer of copper on adhesion layer with methods such as physics vapor phase depositions.
In step 404, utilize electro-plating method to form the copper layer, the thickness of this copper layer is enough to filling groove/through hole.With containing copper sulphate (CuSO
4) and the electrolyte of other additive come copper layer, other additive can be copper ion, sulfuric acid, from chloride ion of hydrochloric acid etc. one or more.
In step 405, remove the part that metal level exceeds interlayer dielectric layer in the CMP mode, make the surface become smooth, thereby finish copper interconnection structure.
In step 406, carry out annealing process.The purpose of this technology is to make the copper grain growth, reduces the crystal boundary in the copper layer, improves the quality of copper layer, so that the copper layer has the good character such as Low ESR and high stability.Annealing in process need feed protective gas in annealing device, this protective gas can be one or more in nitrogen, helium or the argon gas etc.What the present invention used is the mist of helium and nitrogen, and the flow velocity of helium is about 60～100sccm, and the flow velocity of nitrogen is about 1000～1500sccm.Wherein, sccm is under the standard state, just 1 atmospheric pressure, 1 cubic centimetre of (1cm of 25 degrees centigrade of following per minutes
3/ min) flow.In addition, can also feed the ammonia that flow velocity is about 800～1000sccm, apply the radio-frequency power that is about 400～600W.Using high-frequency radio frequency power is in order to impel the ammonia generation hydrogen that dissociates, to utilize the reproducibility characteristics of hydrogen to improve the stability of copper in annealing process.The device that forms the copper layer is heated to about 300～400 ℃ rapidly, is incubated about 45～60s.
In step 407, the surface after annealing forms the dielectric layer of one deck down with the CVD method.At first carry out stabilization processes, in the CVD chamber, feed the needed precursor gas of depositing operation subsequently.In an embodiment of the present invention, in the CVD chamber, feed helium, need feed reacting gas ammonia and trimethyl silane in addition as protective gas.This step probably continued for 10 seconds.By this step, in reacting furnace, formed even and stable precursor gas atmosphere, pending wafer surface and on every side precursor gas have been had fully and contact uniformly.Then, with methods such as CVD dielectric layer on the surface of stabilized processing, the material of preferred dielectric layer can be nitrogenous carborundum.In deposition process, continue to feed reacting gas and protective gas to the CVD chamber, wherein the flow velocity of helium is about 60～100sccm, and the flow velocity of ammonia is about 300～500sccm, and the flow velocity of trimethyl silane is about 500～600sccm.Simultaneously, apply the high-frequency radio frequency power that is about 600～800W, ammonia and trimethyl silane are reacted generate nitrogenous carborundum to be deposited on the copper laminar surface.At last, through cleaning, lifting and process such as bleed, finish the depositing operation of dielectric layer.
Owing to after the electrochemistry plating forms the copper layer, do not pass through annealing in process according to the present invention, therefore in the copper layer, also keeping less stress.Stress in the copper layer that forms according to the embodiment of the invention is about 57Mpa, is starkly lower than according to traditional handicraft the copper layer to be carried out the stress (about 333Mpa) that forms in the copper layer after the annealing in process.Under less relatively membrane stress and actuating force, even through the long stand-by period, because the small cavity of the inhomogeneous formation of growth can not moved yet, and promptly small cavity still is evenly distributed in the copper layer, do not form than macroscopic-void in the copper layer thereby can not assemble at the top of groove/through hole.
Fig. 5 is the flow chart that forms copper interconnection structure according to a further embodiment of the invention.
In step 501, made semiconductor device, for example deposit interlayer dielectric layer on the front end device layer of MOS transistor.The material of this interlayer dielectric layer can be a silicon nitride etc.
In step 502, on this interlayer dielectric layer, apply antireflecting coating and photoresist successively, form photoresist layer through technologies such as exposure, developments then with groove/through-hole pattern, be that mask etching forms groove/through hole with this photoresist layer.
In step 503, be the copper metal that makes filling and the interlayer dielectric layer good adhesion of groove/through-hole side wall, and prevent that the copper metal from spreading in interlayer dielectric layer, before filling metal, deposit one deck adhesion layer earlier, this adhesion layer can be formed by the Ta/TaN composition usually, then forms the crystal seed layer of copper on adhesion layer with methods such as physics vapor phase depositions.
In step 504, utilize electro-plating method to form the copper layer, the thickness of this copper layer is enough to filling groove/through hole.With containing copper sulphate (CuSO
4) and the electrolyte of other additive come copper layer, other additive can be copper ion, sulfuric acid, from chloride ion of hydrochloric acid etc. one or more.
In step 505, remove the part that metal level exceeds interlayer dielectric layer in the CMP mode, make the surface become smooth, thereby finish copper interconnection structure.
In step 506, in the CVD chamber, the copper layer is carried out annealing in process.At first, first stabilization processes before annealing.In this step, do not open radio frequency source, just in the CVD chamber, feed precursor gas, for example one or more in the protective gas such as nitrogen, argon gas and helium and reacting gas.By this step, in reacting furnace, formed even and stable precursor gas atmosphere, pending wafer surface and on every side precursor gas have been had fully and contact uniformly.The protective gas that provides according to the embodiment of the invention is nitrogen and helium, and reacting gas is an ammonia.Wherein, the flow velocity of helium is about 60～100sccm, and the flow velocity of nitrogen is about 1000～1500sccm, and the flow velocity of ammonia is about 800～1000sccm, and this step probably continued for 10 seconds.
Then, carry out annealing process.In the CVD chamber, continue to feed protective gas; this protective gas can be one or more in nitrogen, helium or the argon gas etc.; what the present invention used is the mist of helium and nitrogen, continues simultaneously to feed the reacting gas ammonia, and the flow velocity of three kinds of gases is identical with the technology of first stabilization processes.Open radio frequency source, radio-frequency power is about 400～600W, and using high-frequency radio frequency power is in order to impel the ammonia generation hydrogen that dissociates, to utilize the reproducibility characteristics of hydrogen to improve the stability of copper in high-temperature annealing process.The device that forms the copper layer is heated to about 300～400 ℃ rapidly, is incubated about 45～60s.
Then, carry out second stabilization processes, in this step, close radio frequency source, in the CVD chamber, feed the needed precursor gas of depositing operation subsequently simultaneously.In an embodiment of the present invention; feed helium as protective gas in the CVD chamber, feed ammonia and trimethyl silane as reacting gas, wherein the flow velocity of helium is about 60～100sccm; the flow velocity of ammonia is about 300～500sccm, and the flow velocity of trimethyl silane is about 500～600sccm.This step probably continued for 10 seconds.
Then, adopt the dielectric layer of CVD method at one deck under deposition on the surface of second stabilization processes, preferred dielectric layer material can be nitrogenous carborundum.In deposition process, continue to feed reacting gas ammonia and trimethyl silane to the CVD chamber, and the protective gas helium.Simultaneously, apply high-frequency radio frequency power.Wherein the flow velocity of three kinds of gases is identical with the technology of second stabilization processes, and radio-frequency power is about 600～800W.Under the effect of high-frequency radio frequency power, ammonia and trimethyl silane react and generate nitrogenous carborundum and be deposited on the copper laminar surface.
At last, through cleaning, lifting and process such as bleed, finish the depositing operation of dielectric layer.
Copper interconnection structure according to traditional handicraft and technology of the present invention formation is worsened experiment, and experimental result shows that the cumulative distribution function curve of the copper interconnection structure that technology forms according to the present invention is more restrained, so the life-span is longer.Fig. 6 is the cumulative distribution function curve according to the puncture voltage of the copper interconnection structure of traditional handicraft and technology of the present invention formation.As shown in Figure 6, the puncture voltage of the copper interconnection structure that technology forms according to the present invention becomes big.Therefore, the copper interconnection structure that technology forms according to the present invention has good electric property and long useful life.
Though above-mentioned specific embodiment has used the copper metal, the present invention is not limited to this or any other use of electric conducting material.Various material can experience annealing and cause and migration will all will fall within the scope of protection of the present invention subsequently through planarization.For example, optional embodiment of the present invention can be used to cause the migration of the conducting metal outside the copper removal, includes but not limited to aluminium, Al-zn-mg-cu alloy and gold.In these optional electric conducting materials some can form by deposition technique, and other can form by electroplating technology.
Semiconductor device according to the metal interconnect structure with good electrical character of aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcie arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. one kind forms metal interconnected method, and described method comprises:
On the front end device layer, deposit interlayer dielectric layer;
On described interlayer dielectric layer, form metal interconnecting layer;
Described metal interconnecting layer is carried out cmp;
Described metal interconnecting layer is annealed.
2. method according to claim 1, further comprising the steps of:
After annealing steps on described metal interconnecting layer dielectric layer.
3. method according to claim 1, wherein said metal interconnecting layer are the copper layers.
4. method according to claim 3 wherein utilizes electro-plating method to form described copper layer.
5. method according to claim 1, wherein said annealing steps carries out in annealing device.
6. method according to claim 2, wherein said annealing steps carries out in the reaction chamber that forms described dielectric layer.
7. method according to claim 1 wherein feeds in nitrogen, helium or the argon gas one or more as protective gas when described annealing steps carries out.
8. method according to claim 1, wherein annealing temperature is 300～400 ℃, temperature retention time is 45～60s.
9. method according to claim 7, wherein the flow velocity of helium is 60～100sccm, the flow velocity of nitrogen is 1000～1500sccm.
10. electronic equipment that method according to claim 1 is made, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010102401XA CN102136450A (en) | 2010-01-27 | 2010-01-27 | Method for forming metal interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010102401XA CN102136450A (en) | 2010-01-27 | 2010-01-27 | Method for forming metal interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102136450A true CN102136450A (en) | 2011-07-27 |
Family
ID=44296187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010102401XA Pending CN102136450A (en) | 2010-01-27 | 2010-01-27 | Method for forming metal interconnection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102136450A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104037120A (en) * | 2013-03-06 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing MIM capacitor |
| CN107564852A (en) * | 2017-08-31 | 2018-01-09 | 长江存储科技有限责任公司 | The heat treatment method of steel structure and the forming method of three-dimensional storage |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1767168A (en) * | 2004-10-29 | 2006-05-03 | 台湾积体电路制造股份有限公司 | Differentially doped copper enchasing structure and its manufacturing method |
| US7419847B2 (en) * | 2004-12-29 | 2008-09-02 | Dongbu Electronics Co., Ltd. | Method for forming metal interconnection of semiconductor device |
-
2010
- 2010-01-27 CN CN201010102401XA patent/CN102136450A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1767168A (en) * | 2004-10-29 | 2006-05-03 | 台湾积体电路制造股份有限公司 | Differentially doped copper enchasing structure and its manufacturing method |
| US7419847B2 (en) * | 2004-12-29 | 2008-09-02 | Dongbu Electronics Co., Ltd. | Method for forming metal interconnection of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104037120A (en) * | 2013-03-06 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing MIM capacitor |
| CN107564852A (en) * | 2017-08-31 | 2018-01-09 | 长江存储科技有限责任公司 | The heat treatment method of steel structure and the forming method of three-dimensional storage |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102584552B1 (en) | Method and apparatus for characterizing metal oxide reduction | |
| CN100481380C (en) | Method for manufacturing interconnect structure for semiconductor devices | |
| TWI645511B (en) | Doped tantalum nitride for copper barrier applications | |
| TWI619171B (en) | Barrier layers | |
| TW200915485A (en) | Method of depositing tungsten using plasma-treated tungsten nitride | |
| KR20090093985A (en) | Fabricating a contact rhodium structure by electroplating and electroplating composition | |
| CN101728315A (en) | Manufacture method of conducing plug | |
| JP2001298028A (en) | Manufacturing method of semiconductor device | |
| TW201925532A (en) | Methods and apparatus for filling substrate features with cobalt | |
| TW472348B (en) | Method to deposit a two-layer-diffusion barrier | |
| CN100590812C (en) | Method for forming copper layer and copper mosaic structure | |
| Lee et al. | Barrier properties of CVD Mn oxide layer to Cu diffusion for 3-D TSV | |
| TWI281189B (en) | Plasma treatment method for electromigration reduction | |
| US9449872B1 (en) | Method for forming cobalt barrier layer and metal interconnection process | |
| CN102881677A (en) | Alloy copper diffusion barrier layer for copper interconnection and manufacturing method thereof | |
| CN102136450A (en) | Method for forming metal interconnection | |
| US7981793B2 (en) | Method of forming a metal directly on a conductive barrier layer by electrochemical deposition using an oxygen-depleted ambient | |
| JP2002026017A (en) | Method of forming metal wiring of semiconductor element | |
| CN115910917B (en) | Metal tungsten film and preparation method thereof | |
| US20150130064A1 (en) | Methods of manufacturing semiconductor devices and a semiconductor structure | |
| Yu et al. | Advanced integrated metallization enables 3D-IC TSV scaling | |
| KR102118580B1 (en) | Chemical vapor deposition (cvd) of ruthenium films and applications for same | |
| US6528415B2 (en) | Method of forming a metal line in a semiconductor device | |
| JP2002356775A (en) | Method of achieving high adhesion property of thin cvd copper film on tan substrate | |
| CN107154380B (en) | Preparation method of metal interconnection structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130107 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130107 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110727 |