CN102131328A

CN102131328A - Power-on circuit of LED (light-emitting diode) drive chip

Info

Publication number: CN102131328A
Application number: CN2010106039543A
Authority: CN
Inventors: 石万文; 江石根
Original assignee: SUZHOU HUAXIN MICROELECTRONICS CO Ltd
Current assignee: SUZHOU HUAXIN MICROELECTRONICS CO Ltd
Priority date: 2010-12-24
Filing date: 2010-12-24
Publication date: 2011-07-20
Anticipated expiration: 2030-12-24
Also published as: CN102131328B

Abstract

The invention provides a power-on circuit of an LED (light-emitting diode) drive chip. The LED drive chip is characterized by comprising a delay circuit and a power supply voltage detection module, wherein, high-voltage reference voltage current and low-voltage reference voltage current are input into an input terminal of the delay circuit, and an output terminal of the delay circuit is connected with an enabling end of the power supply voltage detection module; and power supply voltage and reference voltage are input into an input terminal of the power supply voltage detection module, and an output terminal of the power supply voltage detection module is the output terminal of the whole power-on circuit. The power-on circuit provided by the invention has the advantages that the high-voltage reference voltage current and the low-voltage reference voltage current are analyzed and judged, and then an effective enabling signal is sent after the high-voltage reference voltage current and the low-voltage reference voltage current keep stable so as to achieve the purpose of controlling the operating condition of units of the LED drive chip, thus preventing failure of the chip in normal operation and even damage on an LED system owing to uncontrolled operating condition of the units during the power-on process.

Description

A kind of circuit that powers on of LED chip for driving

Technical field

The invention belongs to integrated circuit fields, relate in particular to the integrated circuit of LED type of drive.

Background technology

One class LED chip for driving is arranged, its part pin normal working voltage is more than 8V, and most of circuit of chip internal all is operated in below the 8V, so such chip for driving adopts the integrated circuit fabrication process of high-voltage CMOS and low voltage CMOS compatibility usually, be operated in the following circuit of 8V and adopt low voltage CMOS, and the circuit that is operated in more than the 8V adopts high-voltage CMOS.The reference voltage current module (high pressure reference voltage current module) that such LED chip for driving is made up of high-voltage CMOS and resistance, electric capacity etc., the reference voltage current module (low pressure reference voltage current module) that also has low voltage CMOS and resistance, electric capacity etc. to form simultaneously.

When power supply has just been begun to be added to the power pin of chip, the power pin of chip can rise to operating voltage range from 0V in the regular hour, in this process, high pressure reference voltage or reference current and low pressure reference voltage or reference current can be successively from the normal range of operation that is raised to above freezing, general chip internal device all has certain normal range of operation, when exceeding this scope, device meeting operation irregularity, even cause the LED system damage.

Summary of the invention

The technical problem to be solved in the present invention is: a kind of circuit that powers on of LED chip for driving is provided, can carries out ordered control to the operating state of each unit of LED chip for driving.

The present invention solves the problems of the technologies described above the technical scheme of being taked to be: a kind of circuit that powers on of LED chip for driving, it is characterized in that: it comprises delay circuit and supply voltage detection module, wherein the input of delay circuit is imported high pressure reference voltage electric current and low pressure reference voltage electric current, and the output of delay circuit is connected with the Enable Pin of supply voltage detection module; The input input supply voltage and the reference voltage of supply voltage detection module, output is the output of the whole circuit that powers on.

Press such scheme, described delay circuit comprises the high-tension current mirror to high pressure reference current mirror image that is made of PMOS pipe and the 2nd PMOS pipe, is managed and current mirror, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, first comparator, second comparator, first resistance and the electric capacity of the road current source mirror image that the 4th PMOS pipe constitutes by the 3rd PMOS; The drain electrode one tunnel of the 2nd PMOS pipe is connected back ground connection with first resistance, another road is connected with the grid of the 2nd NMOS pipe, the source ground of the 2nd NMOS pipe; The drain electrode of the 4th PMOS pipe is connected with the drain electrode of a NMOS pipe, the grid input low pressure reference voltage of a NMOS pipe, and the source electrode of a NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe; The drain electrode of the one NMOS pipe also is connected with the input of first comparator, and the output of first comparator is connected with the grid of the 3rd NMOS pipe, and the 3rd NMOS manages source ground, and the drain electrode of the 3rd NMOS pipe is connected with the drain electrode of the 5th PMOS pipe; The grid of the 5th PMOS pipe connects the source mirror image of one road electric current, and the drain electrode one tunnel of the 5th PMOS pipe connects ground connection behind the electric capacity, and another road connects the input of second comparator, and the output of second comparator is the delay circuit output.The source mirror image of the road electric current that is connected with the grid of the 5th PMOS pipe can be low pressure reference current or other current source current, and its effect is to provide one road operating current to N1 and N2.

Press such scheme, described supply voltage detection module is the 3rd comparator, and the Enable Pin of the 3rd comparator is connected with the output of delay circuit, and the output of the 3rd comparator is the output of described supply voltage detection module; The end of oppisite phase of input the 3rd comparator connects after the described supply voltage dividing potential drop, and reference voltage is imported the positive terminal of the 3rd comparator.

Operation principle of the present invention is: when power supply has just been begun to be added to chip, high pressure reference voltage electric current and low pressure reference voltage electric current can be at first from the normal range of operation that is raised to above freezing, when the supply voltage detection module detects high pressure reference voltage or reference current and rises to a setting, when low pressure reference voltage or reference current also rise to a setting simultaneously, because the effect of delay circuit, high pressure reference voltage or reference current and low pressure reference voltage or reference current reach setting and have kept a period of time, be the time that delay circuit is set during this period of time, allow the supply voltage detection module start working then; This moment, the supply voltage detection module began supply voltage is detected, and when the supply voltage that detects during more than or equal to setting V1, the output of supply voltage detection module is just exported effective enable signal and given the LED system; When effective enable signal output state, when the supply voltage detection module detects supply voltage and is lower than setting V2, then export invalid enable signal, V1 always greater than (or equaling) V2 to prevent forming vibration, cause the frequent switch of above-mentioned functions and cannot stop.

Beneficial effect of the present invention is:

1, by increasing delay circuit and supply voltage detection module, can carry out analysis and judgement to high pressure reference voltage electric current, low pressure reference voltage electric current, treat to send effective enable signal again after high pressure reference voltage electric current, the low pressure reference voltage current stabilization, thereby reach the purpose of controlling each cell operation state of LED chip for driving;

2, before LED chip for driving enable signal, carry out and prejudge, guarantee that voltage/current allows other unit of LED chip for driving start working after stable again, assurance LED system safety is worked reliably, prevent the operating state chip cisco unity malfunction that causes out of control of each unit when powering on, even the LED system is damaged.

Description of drawings

Fig. 1 is the structured flowchart of one embodiment of the invention

Fig. 2 is the circuit theory diagrams of one embodiment of the invention

Embodiment

Fig. 1 is the structured flowchart of one embodiment of the invention, comprise delay circuit and supply voltage detection module, wherein the input of delay circuit is imported high pressure reference voltage electric current and low pressure reference voltage electric current, and the output of delay circuit is connected with the Enable Pin of supply voltage detection module; The input input supply voltage and the reference voltage of supply voltage detection module, output is the output of the whole circuit that powers on.

Fig. 2 is the circuit theory diagrams of one embodiment of the invention, described delay circuit comprises the high-tension current mirror to high pressure reference current IREF1 mirror image that is made of PMOS pipe P1 and the 2nd PMOS pipe P2, the current mirror of the road current source IREF2 mirror image that is made of the 3rd PMOS pipe P3 and the 4th PMOS pipe P4; The drain electrode one tunnel of the 2nd PMOS pipe P2 is connected back ground connection with first resistance R 1, another road is connected with the grid of the 2nd NMOS pipe N2, the source ground of the 2nd NMOS pipe N2; The drain electrode of the 4th PMOS pipe P4 is connected with the drain electrode of NMOS pipe N1, the grid input low pressure reference voltage V REF1 of NMOS pipe N1, and the source electrode of NMOS pipe N1 is connected with the drain electrode of described the 2nd NMOS pipe N2; The drain electrode of the one NMOS pipe N1 also is connected with the input of the first comparator C OMP1, the output of the first comparator C OMP1 is connected with the grid of the 3rd NMOS pipe N3, the 3rd NMOS pipe N3 source ground, the drain electrode of the 3rd NMOS pipe N3 is connected with the drain electrode of the 5th PMOS pipe P5; The grid of the 5th PMOS pipe P5 connects one road current source IREF2 mirror image, and the drain electrode one tunnel of the 5th PMOS pipe P5 connects ground connection behind the electric capacity, and another road connects the input of the second comparator C OMP2, and the output of the second comparator C OMP2 is the delay circuit output.

The supply voltage detection module is the 3rd comparator C OMP3, and the Enable Pin of the 3rd comparator is connected with the output of the second comparator C OMP2, and the output of the 3rd comparator C OMP3 is the output of described supply voltage detection module; The end of oppisite phase of described supply voltage input the 3rd comparator C OMP3 after R2 and R3 dividing potential drop is connected, and reference voltage VREF2 imports the positive terminal of the 3rd comparator.

The course of work is: the high pressure reference current is electric current I REF1 by the current mirror mirror image, the current mirror of forming by PMOS pipe P1 and PMOS pipe P2 is mirrored to P2 with IREF1, flow through PMOS pipe P2 source-drain current then and on resistance R 1, form a voltage, big more as big more then this voltage of high pressure reference current, when this voltage greatly to making NMOS manage the N2 conducting, low pressure reference voltage V REF1 is also greatly to making NMOS pipe N1 conducting simultaneously, then the drain terminal of NMOS pipe N1 can become low level by high level, the comparator C OMP1 output that the hysteresis buffer is formed also becomes low level by high level, causing NMOS pipe N3 to be become by conducting ends, the input of the comparator C OMP2 that the hysteresis buffer forms is begun by the electric current that is mirrored to PMOS pipe P5 by IREF2 capacitor C 1 to be charged by low level, the input terminal voltage of COMP2 is slowly risen, when this voltage rises to overturn point above COMP2, it is that the Enable Pin of hysteresis loop comparator COMP3 becomes high level by low level that the output of COMP2 becomes high level by low level, COMP3 begins operate as normal when the Enable Pin of COMP3 is high level, otherwise the output Y of COMP3 is a high level always.When beginning operate as normal, COMP3 just can detect supply voltage, supply voltage VDD is divided to the COMP3 backward end by resistance R 2 and resistance R 3, when COMP3 backward end voltage during greater than reference voltage VREF2 the output Y of COMP3 become low level, make other unit of chip begin to enter operating state.So just can well solve when powering on, the operating state of each unit of LED chip for driving is carried out the ordered control problem, and assurance LED system safety is worked reliably.

Claims

1. the circuit that powers on of a LED chip for driving, it is characterized in that: it comprises delay circuit and supply voltage detection module, wherein the input of delay circuit is imported high pressure reference voltage electric current and low pressure reference voltage electric current, the output of delay circuit is connected with the Enable Pin of supply voltage detection module, the input input supply voltage and the reference voltage of supply voltage detection module, output is the output of the whole circuit that powers on.

2. the circuit that powers on of LED chip for driving according to claim 1 is characterized in that: described delay circuit comprises the high-tension current mirror to high pressure reference current mirror image that is made of PMOS pipe and the 2nd PMOS pipe, is managed and current mirror, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, first comparator, second comparator, first resistance and the electric capacity of the road current source mirror image that the 4th PMOS pipe constitutes by the 3rd PMOS; The drain electrode one tunnel of the 2nd PMOS pipe is connected back ground connection with first resistance, another road is connected with the grid of the 2nd NMOS pipe, the source ground of the 2nd NMOS pipe; The drain electrode of the 4th PMOS pipe is connected with the drain electrode of a NMOS pipe, the grid input low pressure reference voltage of a NMOS pipe, and the source electrode of a NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe; The drain electrode of the one NMOS pipe also is connected with the input of first comparator, and the output of first comparator is connected with the grid of the 3rd NMOS pipe, and the 3rd NMOS manages source ground, and the drain electrode of the 3rd NMOS pipe is connected with the drain electrode of the 5th PMOS pipe; The grid of the 5th PMOS pipe connects the source mirror image of one road electric current, and the drain electrode one tunnel of the 5th PMOS pipe connects ground connection behind the electric capacity, and another road connects the input of second comparator, and the output of second comparator is the delay circuit output.

3. the circuit that powers on of LED chip for driving according to claim 1 and 2, it is characterized in that: described supply voltage detection module is the 3rd comparator, the Enable Pin of the 3rd comparator is connected with the output of delay circuit, and the output of the 3rd comparator is the output of described supply voltage detection module; The end of oppisite phase of input the 3rd comparator connects after the described supply voltage dividing potential drop, and reference voltage is imported the positive terminal of the 3rd comparator.