CN102123009B - Method and device for decoding dynamic Viterbi - Google Patents
Method and device for decoding dynamic Viterbi Download PDFInfo
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Abstract
The invention discloses a method for decoding dynamic Viterbi, comprising the following steps: using set parameter values to decode an existing receiving sequence based on a Viterbi algorithm to acquire decoding, wherein the parameter values comprise memory depth and/memory width, and the memory depth represents backtracking span of arrow diagrams in the Viterbi algorithm and/or the memory width represents branch metric of the arrow diagrams in the Viterbi algorithm; adjusting the parameter values in the range of adjustment lower limit and adjustment upper limit; and using the Viterbi algorithm which is used for adjusting the parameter values to decode the next receiving sequence. The invention also discloses a device for decoding dynamic Viterbi. According to the invention, decoding parameters can be adjusted dynamically in accordance with the condition of existing interchannel noise, the decoding performance of the Viterbi can be exerted maximally, the error rate is reduced effectively, and the effective utilization of the resources can be ensured at the same time.
Description
Technical field
The present invention relates to a kind of Digital Signal Processing, particularly relate to a kind of dynamic Viterbi coding/decoding method and device.
Background technology
In modern digital communication, for reducing the error rate of transfer of data, improve quality and the reliability thereof of communication, often adopt error correction coding in a communications system, wherein convolution code is exactly a kind of error correcting code with stronger error correcting capability.Due to the decoding algorithm of convolution code---viterbi algorithm compares and is easy to realize, and can obtain larger coding gain, the convolution code therefore based on Viterbi decoding algorithm is widely applied.
Convolution code is proposed by Ellis nineteen fifty-five, and it is different from linear block codes, and in convolution coding, n-k verification unit of this group is not only relevant with k information word of this group, and relevant with the information group that each moment former inputs to encoder.Equally, in convolution code decode procedure, in the code character that not only from then on the moment receives, extract decoding information, but also extract for information about in the code character that before will utilizing, the moment receives.
In the process of convolution coding, owing to taking full advantage of the correlation between each group, therefore under the code check identical with block code and complexity condition, no matter theoretically or from fact all proving that the performance of convolution code is at least poor unlike block code, and also comparatively block code is easy to realize best and accurate optimal decoding.So from channel coding theorem, convolution code is a kind of code class that can reach the code performance that channel coding theorem proposes.
The probabilistic decoding of convolution code starts from the sequential decoding proposed by Wozencraft for 1961 the earliest, and this is the probabilistic decoding method of the convolution code of the use that first proposes, and within 1963, Fano improves sequential decoding, proposes Fano algorithm.Within 1967, Viterbi proposes another kind of probability decoding algorithm, and it is a kind of maximum-likelihood decoding algorithm.When the constraint degree of code is less, it is higher than sequential decoding efficiency of algorithm, speed is faster, decoder is also simpler, thus since viterbi algorithm proposes, be no matter in theory or be obtained in practice and develop extremely rapidly, and be widely used in various data transmission system, particularly satellite communication system.In recent years, convolution code widely for the wireless communication system of various standard, from second generation wireless communication system GSM to TD-SCDMA, WCDMA of the third generation, all employ convolution code, so how to improve the performance of Viterbi decoding, reducing the error rate, is the emphasis that various countries' research is paid close attention to.
All receiving sequences that at every turn all will wait traditional viterbi algorithm all develop into last moment Tn on grid vector figure could start forward trace, and its shortcoming is exactly the increase along with constraint length, and the complexity of algorithm also can strengthen rapidly.But owing to using the source sequence of convolutional encoding may be very long in the communication system of reality, could forward trace be started if all receiving sequences all will be waited on grid vector figure all to develop into last moment Tn at every turn, time delay will be caused very large; Existing technology uses the backtracking mode of brachymemma usually, and it fixes a traceback length, when this traceback length of arrival just starts backtracking.But recall according to fixing traceback length, cannot adjust according to channel disturbance situation and actual transmission quality, waste or the decoding error of decode resources can be caused, be difficult to the requirement adapting to current more and more higher transmission rate.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides a kind of dynamic Viterbi coding/decoding method, comprising:
Current receiving sequence is decoded based on viterbi algorithm with the parameter value of setting, obtain decoding, described parameter value comprises memory depth and/or memory width, and described memory depth is the backtracking span of grid chart in viterbi algorithm and/or described memory width is the quantity staying routing footpath in viterbi algorithm in convolution coding circuit;
Based on the situation of interchannel noise and/or the effect of decoding, described parameter value is adjusted in adjustment lower limit with the scope of the adjustment upper limit;
With the viterbi algorithm after the described parameter value of adjustment, next section of receiving sequence is decoded;
Based on viterbi algorithm, current receiving sequence is decoded at the parameter value of described setting, after obtaining the step of decoding, also comprises:
Convolution coding is carried out in described decoding, obtains coded sequence;
Described receiving sequence and described coded sequence are carried out computing, obtains channel interference values;
Described described parameter value step of adjusting in the scope of adjustment lower limit and the adjustment upper limit to be comprised:
According to the result of described channel interference values compared with the average interference value of channel, described memory depth and/or described memory width is adjusted in the scope of described adjustment lower limit and the described adjustment upper limit, wherein, described average interference value is the mean value of a predetermined number described channel interference values;
Described adjustment mode comprises, and when described channel interference values is less than described mean value, reduces described memory depth and/or reduces described memory width; When described channel interference values is greater than described mean value, increases described memory depth and/or increase described memory width; When described channel interference values equals described mean value, maintain described memory depth and/or described memory width is constant.
Correspondingly, present invention also offers a kind of dynamic Viterbi decoding device, comprising:
Viterbi arithmetic element, for decoding to current receiving sequence based on viterbi algorithm with the parameter value of setting, obtains decoding;
The parameter adjustment unit be connected with described Viterbi arithmetic element, for based on the situation of interchannel noise and/or the effect of decoding, in adjustment lower limit with the scope of the adjustment upper limit, adjust the parameter value of memory depth and/or memory width in the viterbi algorithm of described Viterbi arithmetic element;
The output deposit unit be connected with described Viterbi arithmetic element, for the decoding that temporary described Viterbi arithmetic element will obtain after the decoding of current receiving sequence;
The input deposit unit be connected with described Viterbi arithmetic element, that decodes for the described Viterbi arithmetic element of temporary confession works as receiving sequence described in the last period;
The receiving element be connected with described input deposit unit, for receiving described receiving sequence, after described Viterbi arithmetic element is by current receiving sequence decoding, next section of receiving sequence is transferred to described input deposit unit by described receiving element;
Also comprise:
The coding unit be connected with described output deposit unit, for convolution coding is carried out in described decoding, obtains coded sequence;
The noise evaluation unit be connected respectively with described input deposit unit with described coding unit, for described receiving sequence and described coded sequence are carried out computing, obtains channel interference values;
Described noise evaluation unit also comprises:
Comparing unit, for by described channel interference values compared with the average interference value of channel, and the result compared is outputted to described parameter adjustment unit, described parameter adjustment unit adjusts described memory depth and/or described memory width according to the result of described comparison;
Wherein, described comparing unit also comprises average calculation unit, and for calculating average interference value, described average interference value is the mean value of a predetermined number described channel interference values.
Implement the present invention, there is following beneficial effect:
The present invention adopts dynamic brachymemma to recall mode, situation according to present channel noise dynamically adjusts decoding parameter, backtracking is just started when arriving the moment meeting described decoding parameter, and the fixing traceback length of non-usage one is recalled, therefore the present invention can play the decoding performance of Viterbi to greatest extent, ensures effective utilization of resource simultaneously.In order to effectively reduce the error rate, do not increase taking of resource, this method also evaluates the interference value of channel simultaneously, dynamically makes Joint regulation to the memory depth of grid vector with memory width, improve the decoding quality of Viterbi to greatest extent according to this interference value.
Accompanying drawing explanation
Fig. 1 is the flow chart of a kind of dynamic Viterbi coding/decoding method of the present invention;
Fig. 2 is (2,1,2) convolution code grid vector figure of an embodiment of a kind of dynamic Viterbi coding/decoding method of the present invention;
Fig. 3 is an embodiment flow chart of a kind of dynamic Viterbi coding/decoding method of the present invention;
Fig. 4 is the schematic diagram of a kind of dynamic Viterbi decoding device of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
Fig. 1 is the flow chart of a kind of dynamic Viterbi coding/decoding method of the present invention, comprising:
S101: based on viterbi algorithm, current receiving sequence is decoded with the parameter value of setting, obtain decoding, described parameter value comprises memory depth and/or memory width, the branch metric of described memory depth to be the backtracking span of grid chart in viterbi algorithm and/or described memory width be grid chart in viterbi algorithm.
It should be noted that, for different convolution coding circuit, different convolution code grids can be formed.But for the Veterbi decoding thought of convolution code, principle is consistent.For the ease of illustrating the technical program, be example explanation with simple (2,1,2) convolution code below.But do not represent the technical program and be defined in described (2,1,2) convolution code, the technical program is applicable to any convolutional code decoder method based on viterbi algorithm.
In viterbi algorithm, need receiving sequence path metrics, often kind of state all likely turns to the one in possible state thereafter, each state corresponds to the bit of up-to-date input in convolutional encoder shift register, this bit is 0 this kind of state corresponding, be 1 and correspond to another state, the path accumulated value of two paths on state node each on grid chart is compared, the path (path that probability is higher) had compared with small path accumulated value is preserved as survivor path, another paths is abandoned, store corresponding branched measurement value simultaneously.
Due to each timing node state may from one of two states above, if per moment all abandons the wherein a kind of state before in each state, just obtain 2 of each moment
m-1bar residual paths, wherein m is encoding constraint length.These are 2 years old
m-1bar residual paths each moment develops 2 backward
mpaths, but discard 2 according to path accumulated value again
m-1paths, residue 2
m-1paths, is constantly abandoning and is developing, and iterative method screening survivor path, reaches a survivor path of the end state in last moment, be decoding paths.By decoding paths, just decoding can be obtained.
S102: described parameter value is adjusted in adjustment lower limit with the scope of the adjustment upper limit.
Described memory depth, the span namely recalled and the performance of decoding have substantial connection, and the span of backtracking is larger, the performance of decoding is better, the span of backtracking is equivalent to the sampling to grid vector figure, when the scope of sampling is larger, more can approach development path during original coding.But the span of backtracking can not unconfinedly increase, otherwise can take too much resource, and the backtracking span exceeding certain length can be fewer and feweri to the optimization space that performance is brought.Preferably, described memory depth was preset as 4 by the technology of the present invention before adjusting.
Equally, described memory width, i.e. the performance of branch metric and decoding is also closely related.Such as (2,1,2) convolutional encoder circuit, due to encoding constraint length m=3, so existence number is 2
2=4, each moment develops 8 paths, and after reaching subsequent time screened go out 4 paths.When the interference of channel is very large, likely can at a time correct path be abandoned, the probability of the misjudgement in this moment is caused to increase, the quantity in routing footpath is stayed also to be put forward high performance means so increase, such as (2, 1, 2) in convolutional encoder circuit, when handle stays routing footpath to be increased to 8, each state in each exactly moment remains 2 paths, and 16 paths can be developed at subsequent time, after arrival subsequent time, in 16 paths of previous moment 8 are abandoned, pass through 2 paths all states retaining current time like this, the path of screening previous moment, effectively can resist the interference of channel, reduce the error rate.Preferably, described memory width was preset as 4 by the technology of the present invention before adjusting.
It should be noted that, through step S101, we obtain the decoding of one section of receiving sequence, we can assess the situation of interchannel noise and the effect of decoding accordingly, and based on this, we adjust above-mentioned memory width and memory depth, and object is to improve decoding quality and decoding efficiency.
Preferably, the adjustment lower limit depthMin=m of described memory depth, m is constraint code length, adjustment upper limit depthMax=receiveLength/symbolOutWidth, receiveLength is the bit length of described current receiving sequence, and symbolOutWidth is the bit length of the output of arranging in convolution coding.In the adjustment upper limit with the scope of adjustment lower limit, dynamic conditioning is carried out to described memory depth.Such as, for (2,1,2) convolution code, constraint length m=3, the adjustment lower limit of described memory depth is 3, and the adjustment upper limit is 14/2=7, and described memory depth carries out dynamic conditioning in the scope of 3 to 7.
Equally, preferably, the lower limit remembering the adjustment of width is 2
m-2, the upper limit of adjustment is 2
m, wherein m is encoding constraint length.In the adjustment upper limit with the scope of adjustment lower limit, dynamic conditioning is carried out to described memory width.Such as, for (2,1,2) convolution code, constraint length m=3, the adjustment lower limit of described memory width is 2, and the adjustment upper limit is 8, and described memory width carries out dynamic conditioning in the scope of 2 to 8.
When described memory depth and/or described memory width are described adjustment lower limit, when still needing reduce described memory depth and/or reduce described memory width, maintain described memory depth and/or described memory width is constant; Such as, when memory depth is 3, for reducing the adjustment of memory depth, then it is 3 constant for maintaining memory depth.
When described memory depth and/or described memory width are the described adjustment upper limit, when still needing increase described memory depth and/or increase described memory width, maintain described memory depth and/or described memory width is constant.Such as remember width when being 8, for the adjustment increasing memory width, then it is 8 constant for maintaining memory width.
S103: next section of receiving sequence is decoded with the viterbi algorithm after the described parameter value of adjustment.
It should be noted that, in order to effectively reduce the error rate, not increasing taking of resource simultaneously, this method dynamically makes Joint regulation to the memory depth of grid vector with memory width.So-called dynamic conditioning, refers to the decoding cases according to every current receiving sequence, adjusts described memory depth and/or described memory width parameter, utilizes viterbi algorithm decoding next section of receiving sequence after adjustment.So-called Joint regulation, refers to and both can adjust described memory depth or memory width by unit, also can adjust described memory depth and memory width simultaneously.Preferably, the receiving sequence that decoding is all as stated above, until by complete for the decoding of all receiving sequences.Thus played the decoding performance of Viterbi to greatest extent, effectively reduce the error rate, do not take excess resource simultaneously.
Fig. 2 is (2,1,2) convolution code grid vector figure of an implementation column of a kind of dynamic Viterbi coding/decoding method of the present invention.
(n, k, m-1) convolution code refers to that k input correspond to n the convolution coding mode exported, and wherein m is encoding constraint length.(2,1,2) convolution code of Fig. 2 implementation column is exactly corresponding two outputs of input.
Suppose that the original series needing transmission is 10111, need before being transmitted to add tail bit, become 1011100, then convolution coding is carried out to it.In (2,1,2) convolutional encoding mode of Fig. 2 for example, the technical staff of the industry, the convolution coding sequence easily obtaining above-mentioned " 1011100 " is:
11，01，00，10，01，10，11
Above-mentioned coded sequence is after the transmission of channel, and suppose have two bits to occur mistake, the receiving sequence got in decoding device is:
01，01，00，10，11，10，11
Being more than convolution coding and the information transmission result of original series, in order to further describe technical solution of the present invention, carrying out the detailed description of decode procedure below in conjunction with Fig. 2 and Fig. 3.
Fig. 3 is an embodiment flow chart of a kind of dynamic Viterbi coding/decoding method of the present invention.
S201: the accumulated value of state each in viterbi algorithm is set as preset value, wherein, the accumulated value arranging one of them state is less than the accumulated value of all the other states.
In the T0 moment as shown in Figure 2, this is initial time, now sets initial condition and the end state of convolution coding, supposes that the initial condition of convolution coding in the present embodiment and end state are all s0.As shown in Figure 2, s0 correspondence " 00 " state, s1 correspondence " 01 " state, s2 correspondence " 10 " state, s3 correspondence " 11 " state.Correspondingly, when being preset value by the operating parameter setting of viterbi algorithm, the accumulated value of s0 state should be less than the accumulated value of all the other states.Preferably, the accumulated value arranging s0 is 0, and the accumulated value arranging s1 is 10, the accumulated value arranging s2 is 10, the accumulated value arranging s3 is 10, makes the accumulated value of path accumulated value all the other states minimum of s0, must filter out the grid vector from s0 during the grid vector of screening residue like this.
S202: based on viterbi algorithm, current receiving sequence is decoded with the parameter value of setting, obtain decoding, described parameter value comprises memory depth and/or memory width, the branch metric of described memory depth to be the backtracking span of grid chart in viterbi algorithm and/or described memory width be grid chart in viterbi algorithm.
Preferably, described memory depth was preset as 4 by the technology of the present invention before adjusting.
Preferably, described memory width was preset as 4 by the technology of the present invention before adjusting.
Due to (2,1,2) convolution code is that each input correspond to 2 outputs, so every 2 inputs are divided into one group when receiving, send into decoding device, 7 moment can be divided into like this enter decoding device, respectively seven moment of the T1 to T7 of corresponding diagram 2, the following describes the computational methods in each moment.
In the T1 moment as shown in Figure 2, at this moment receiving bit is 01, and according to the coding grid vectogram of (2,1,2) convolution code, as Fig. 2, the path accumulated value calculating the upper branch road of the s0 state in T1 moment is 1, and the path accumulated value of lower branch road is 1.
Previous state due to the upper branch road of s0 is that to have set initial value be 0 to the path accumulated value of s0, s0, so the path accumulated value of the upper branch road of s0 is current path accumulated value add that the path accumulated value of previous state s0 equals 1; And the previous state of the lower branch road of s0 is s1, it is 10 that the path accumulated value of s1 has set initial value, so the path accumulated value of the lower branch road of s0 is current path accumulated value add that the path accumulated value of previous state s1 equals 11.
Because path accumulated value is less, the equal probabilities of the grid vector of decoding and the grid vector of coding is higher, again because having set memory width is 4, so staying of each state selects grid vector to be 1.According to the path accumulated value of the branch road up and down calculated respectively above, through contrast, higher for the wherein path accumulated value namely lower branch road that equal probabilities is lower is abandoned, at this moment branch road is gone up as the grid vector staying choosing, the path accumulated value of the path accumulated value of upper branch road as the s0 state in T1 moment.
In like manner, according to coding grid vectogram, as Fig. 2, the path accumulated value calculating the upper branch road of the s1 state in T1 moment is 0, and the path accumulated value of lower branch road is 2.
Previous state due to the upper branch road of s1 is that to have set initial value be 10 to the path accumulated value of s2, s2, so the path accumulated value of the upper branch road of s1 is current path accumulated value add that the path accumulated value of previous state s2 equals 10; And the previous state of the lower branch road of s1 is s3, it is 10 that the path accumulated value of s3 has set initial value, so the path accumulated value of the lower branch road of s1 is current path accumulated value add that the path accumulated value of previous state s3 equals 12.
According to the path accumulated value of the branch road up and down calculated respectively above, through contrast, higher for the wherein path accumulated value namely lower branch road that equal probabilities is lower is abandoned, at this moment branch road is gone up as the grid vector staying choosing, the path accumulated value of the path accumulated value of upper branch road as the s1 state in T1 moment.
In like manner, according to coding grid vectogram, the path accumulated value calculating the upper branch road of the s2 state in T1 moment is 1, and the path accumulated value of lower branch road is 1.
Previous state due to the upper branch road of s2 is that to have set initial value be 0 to the path accumulated value of s0, s0, so the path accumulated value of the upper branch road of s2 is current path accumulated value add that the path accumulated value of previous state s0 equals 1; And the previous state of the lower branch road of s2 is s1, it is 10 that the path accumulated value of s1 has set initial value, so the path accumulated value of the lower branch road of s2 is current path accumulated value add that the path accumulated value of previous state s1 equals 11.
According to the path accumulated value of the branch road up and down calculated respectively above, through contrast, higher for the wherein path accumulated value namely lower branch road that equal probabilities is lower is abandoned, at this moment branch road is gone up as the grid vector staying choosing, the path accumulated value of the path accumulated value of upper branch road as the s2 state in T1 moment.
In like manner, according to coding grid vectogram, the path accumulated value calculating the upper branch road of the s3 state in T1 moment is 2, and the path accumulated value of lower branch road is 0.
Previous state due to the upper branch road of s3 is that to have set initial value be 10 to the path accumulated value of s2, s2, so the path accumulated value of the upper branch road of s2 is current path accumulated value add that the path accumulated value of previous state s2 equals 12; And the previous state of the lower branch road of s3 is s3, it is 10 that the path accumulated value of s3 has set initial value, so the path accumulated value of the lower branch road of s3 is current path accumulated value add that the path accumulated value of previous state s3 equals 10.
According to the path accumulated value of the branch road up and down calculated respectively above, through contrast, higher for the wherein path accumulated value namely upper branch road that equal probabilities is lower is abandoned, this at present branch road as the grid vector staying choosing, the path accumulated value of the path accumulated value of lower branch road as the s3 state in T1 moment.
In sum, all states in T1 moment all determine the grid vector and path accumulated value that stay choosing.Wherein staying of s0 selects grid vector to be upper branch road, and path accumulated value is 1; Staying of s1 selects grid vector to be upper branch road, and path accumulated value is 10; Staying of s2 selects grid vector to be upper branch road, and path accumulated value is 1; Staying of s3 selects grid vector to be lower branch road, and path accumulated value is 10.
Before the flow process entering moment T2, the memory depth of setting before needing to judge whether to meet, owing to only calculating 1 moment now, is less than the default value that memory depth is 4, so can enter the calculating of moment T2.
The T2 moment as shown in Figure 2, at this moment receiving bit is 01, the method calculating the branch road up and down of each state in the same time 1, but because the moment 1 upgrades the path accumulated value of each state, so use the path accumulated value of moment T1 when the path accumulated value of the branch road up and down of each state of calculating moment T2, that grid vector that after comparing, selecting paths accumulated value is less.
As stated above, finally determine the grid vector and the path accumulated value that stay choosing of all states of moment T2, wherein staying of s0 selects grid vector to be upper branch road, and path accumulated value is 2; Staying of s1 selects grid vector to be upper branch road, and path accumulated value is 1; Staying of s2 selects grid vector to be upper branch road, and path accumulated value is 2; Staying of s3 selects grid vector to be upper branch road, and path accumulated value is 3.
In like manner, before the flow process entering moment T3, the memory depth of setting before needing to judge whether to meet, owing to only calculating 2 moment now, is less than the default value that memory depth is 4, so can enter the calculating of moment T3.
In the T3 moment as shown in Figure 2, at this moment receiving bit is 00, and as stated above, finally determine the grid vector and the path accumulated value that stay choosing of all states of moment T3, wherein staying of s0 selects grid vector to be upper branch road, and path accumulated value is 2; Staying of s1 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s2 selects grid vector to be lower branch road, and path accumulated value is 1; Staying of s3 selects grid vector to be upper branch road, and path accumulated value is 3.
In like manner, before the flow process entering moment T4, the memory depth of setting before needing to judge whether to meet, owing to only calculating 3 moment now, is less than the default value that memory depth is 4, so can enter the calculating of moment T4.
In the T4 moment as shown in Figure 2, at this moment receiving bit is 10, and as stated above, finally determine the grid vector and the path accumulated value that stay choosing of all states of moment T4, wherein staying of s0 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s1 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s2 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s3 selects grid vector to be upper branch road, and path accumulated value is 1.
After all states of moment T4 all calculate the grid vector and path accumulated value staying choosing, again carry out the comparison to the memory depth preset before, find to reach the requirement that the degree of depth is 4, can trace-back process be started.
The path accumulated value of all states of moment T4 is compared, can show that the state wherein with minimum value is s3, grid vector when namely with s3 being grid vector and the coding of termination in multiple grid vector of decoding has maximum equal probabilities, so the state of the starting point moment T4 of backtracking is defined as s3.
Obtained in calculating before the state s3 of moment T4 stay select grid vector be on branch road, and according to grid vector figure, the previous state that the upper branch road of state s3 is corresponding is s2, in like manner can stay from each state in each moment the continuous print grid vector selecting grid vector to obtain having maximum equal probabilities successively toward moment in the past, so just obtaining continuous print grid vector is, from moment T4 state s3, trace back to moment T3 state s2, trace back to moment T2 state s1, trace back to moment T1 state s2, trace back to moment T0 state s0.
By Fig. 2 (2,1,2) feature of convolution code grid vector figure, state after input bit 1 is s2 or the s3 state being positioned at grid vector figure the latter half, state after input bit 0 is s0 or the s1 state of the first half being positioned at grid vector figure, so just can determine corresponding input bit according to the state in each moment on grid vector during decoding.
When therefore tracing back to above the state s2 of moment T1, corresponding input is exactly bit 1, and like this, current trace-back process is bit 1 with regard to obtaining the decode results of moment T1.
After the decode results of output time T1, that continues calculating moment T5 stays network selection lattice vector sum path accumulated value, the T5 moment as shown in Figure 2, and at this moment receiving bit is 11, so wherein staying of s0 selects grid vector to be lower branch road, and path accumulated value is 3; Staying of s1 selects grid vector to be lower branch road, and path accumulated value is 2; Staying of s2 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s3 selects grid vector to be lower branch road, and path accumulated value is 2.
Because the moment quantity calculated has exceeded the memory depth of setting, so moment T5 also will carry out back tracking operation, and backtracking span equals memory depth 4.Obtaining continuous print grid vector is, from moment T5 state s1, traces back to moment T4 state s3, traces back to moment T3 state s2, trace back to moment T2 state s1.In like manner, this decode results of taking turns that trace-back process obtains moment T2 is bit 0.
After the decode results of output time T2, continue calculate below each moment stay network selection lattice vector sum path accumulated value, and often calculate the just execution back tracking operation of a moment, also obtain the decode results in each moment simultaneously, being respectively moment T1 is bit 1, moment T2 is bit 0, and moment T3 is bit 1.
When calculated moment T7 stay network selection lattice vector sum path accumulated value after, owing to being last moment, and known end state is s0, perform back tracking operation, from moment T7 state s0, trace back to moment T6 state s1, trace back to moment T5 state s3, trace back to moment T4 state s3.Because be the last backtracking of this data block, all carry out decoding to each moment in trace-back process, obtaining moment T4 is bit 1, and moment T5 is bit 1, and moment T6 is bit 0, and moment T7 is bit 0.
In sum, according to receiving sequence " 01,01,00; 10,11,10,11 " namely 01010010111011, after memory width preset value is 4 and memory depth preset value is the viterbi algorithm decoding of 4, gets decoding " 10111 ", started to carry out the step S203 shown in Fig. 3.
S203: convolution coding is carried out in described decoding, obtains coded sequence.Described receiving sequence and described coded sequence are carried out computing, obtains channel interference values.
The above-mentioned decoding " 10111 " got is carried out convolution coding again, and the circuit of convolution coding mentioned here is identical with the convolution coding circuit carrying out before sequence transmission encoding, so, be equally applicable to the grid vector figure of Fig. 2.In like manner, the technical staff of the industry, the convolution coding sequence obtaining above-mentioned " 1011100 " in easy Fig. 2 is " 11,01,00,10,01,10,11 " namely 11010010011011.
Because communication process is continuous data stream, when section receiving sequence decoding of is above complete, the decoding of next section of receiving sequence will be carried out at once, preferably, the technology of the present invention, except first paragraph receiving sequence, other receiving sequence all first will carry out computing, to obtain the interference value to interchannel noise assessment to the coded sequence of the decoding of the preceding paragraph receiving sequence and this acquisition before decoding.
The invention process is classified as unipolarity coding, so be applicable to step S2031.
S2031: when described sequence is unipolarity coding, by described receiving sequence Q (q
0, q
1, q
2... q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2... p
n-1, p
n) the concrete operational formula of carrying out computing is,
wherein C is described channel interference values.
For the invention process row, receiving sequence Q (q can be obtained by above-mentioned steps
0, q
1, q
2... q
n-1, q
n)=01010010111011, coded sequence P (p
0, p
1, p
2... p
n-1, p
n)=11010010011011.Use above-mentioned interference value formula can obtain operation result C=2, as the assessed value of interchannel noise.Utilize the assessed value of this interchannel noise, memory width and the memory depth of grid vector during decoding to next section of receiving sequence adjust.In actual applications, can on-the-spot test luck said method obtain this interchannel noise several described in interference value C1, C2 ... Cn.
In actual use, coded sequence may be mapped to bipolarity code element, and such as code element 0 maps to code element 1, and code element 1 maps to code element-1.At this moment receiving sequence may be then the bipolarity code element of floating-point, and as code element 0 maps to positive code element+R, code element 1 maps to negative code element-R, and the amplitude R of code element represents the most right ratio of ambassador, and amplitude is larger, represent this receiving symbol polarity sign may probability larger.As long as the corresponding bit of grid vector figure of Fig. 2 is also mapped as bipolarity code element, such as (1,0) is mapped to (-1,1), can carry out decoding.
For described bipolar coding, be suitable for step S2032.
S2032: when described sequence is bipolar coding, by described receiving sequence Q (q
0, q
1, q
2... q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2... p
n-1, p
n) the concrete operational formula of carrying out computing is,
wherein C is described channel interference values.
Suppose that receiving sequence is
| 10 | -11 | 10.5 | -11.5 | 10 | 11 | -11 | 11 | -10 | -10 | -10.5 | 10.5 | -11 | -11 |
Can obtain receiving sequence by above-mentioned steps is that decoded sequence is-11-1-1-111, then the decode results after inverse mapping is 1011100, identical with the decoding sequence that above-mentioned unipolarity is encoded here.Its coded sequence is 11010010011011, and the coded sequence after mapping is P (p
0, p
1, p
2... p
n-1, p
n)=
| -1 | -1 | 1 | -1 | 1 | 1 | -1 | 1 | 1 | -1 | -1 | 1 | -1 | -1 |
The coded sequence after mapping and receiving sequence Q (q
0, q
1, q
2... q
n-1, q
n)=
| 10 | -11 | 10.5 | -11.5 | 10 | 11 | -11 | 11 | -10 | -10 | -10.5 | 10.5 | -11 | -11 |
Do following computing:
Obtaining operation result is C=108.5, as the assessed value of interchannel noise.Utilize the assessed value of this interchannel noise, memory width and the memory depth of grid vector during decoding to next section of receiving sequence adjust.In actual applications, can test at the scene luck said method obtain this interchannel noise several described in interference value C1, C2 ... Cn.
It should be noted that, described receiving sequence and described coded sequence are carried out computing, the computing formula obtaining channel interference values is not limited to above-mentioned formula, can test by experiment, derive other carries out computing formula according to described receiving sequence and described coded sequence.
S204: according to the result of described channel interference values compared with the average interference value of channel, adjusts described memory depth and/or described memory width, and wherein, described average interference value is the mean value of a predetermined number described channel interference values.
Described adjustment mode comprises, and when described channel interference values is less than described mean value, reduces described memory depth and/or reduces described memory width; When described channel interference values is greater than described mean value, increases described memory depth and/or increase described memory width; When described channel interference values equals described mean value, maintain described memory depth and/or described memory width is constant.
It should be noted that, described channel average interference value σ is described interference value C1, C2 ... the mean value of Cn.Suppose the average interference value σ obtaining the road of unipolarity code element through experiment test
0=4, interference when interchannel noise interference value as above is 2 is lower, can reduce memory depth and/or reduce memory width; Suppose the average interference value σ obtaining the road of bipolarity code element through experiment test
1=80, interference when interchannel noise interference value as above is 108.5 is higher, can increase memory depth and/or increase memory width.
S205: next section of receiving sequence is decoded with the viterbi algorithm after the described parameter value of adjustment.
When interchannel noise interference value C is less than channel average interference value σ, corresponding adjustment mode reduces memory width and/or reduces memory depth.Be described below:
Implement adjustment mode one, reduce memory width.
The memory depth 4 of hypothetical trellis vector is constant, and memory width is adjusted to 2 from 4, then do following adjustment to said process.Keep memory width to be the account form of 4 to the moment point within backtracking span, adjustment is started to the memory width of the grid vector of moment T4.
For convenience of description, suppose that second segment receiving sequence is the same with first paragraph receiving sequence.Have result of calculation above, to moment T4, have staying of s0 to select grid vector to be upper branch road, path accumulated value is 3; Staying of s1 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s2 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s3 selects grid vector to be upper branch road, and path accumulated value is 1.Choose 2 state s0, s3 that wherein path accumulated value is minimum, stay the grid vector of choosing just to only have 4 like this.From moment T4 to moment T5, it is 8 that lattice vector advances from 4, to moment T5 carry out calculating stay network selection lattice vector sum path accumulated value time, only need to calculate the state relating to the residue grid vector of moment T4.
According to above-mentioned algorithm, select grid vector to be upper branch road to staying of moment T5, state s0, path accumulated value is 5; Staying of s1 selects grid vector to be lower branch road, and path accumulated value is 2; Staying of s2 selects grid vector to be upper branch road, and path accumulated value is 3; Staying of s3 selects grid vector to be lower branch road, and path accumulated value is 2.
The path accumulated value of all states of moment T5 is compared, can show that the state wherein with minimum value is s1, grid vector when namely with s1 being grid vector and the coding of termination in multiple grid vector of decoding has maximum equal probabilities, so the state of the starting point moment T5 of backtracking is defined as s1.
In calculating before, obtained staying of the state s1 of moment T5 selects grid vector to be lower branch road, in like manner can stay from each state in each moment the continuous print grid vector selecting grid vector to obtain having maximum equal probabilities successively toward moment in the past, such continuous print grid vector is, from moment T5 state s1, trace back to moment T4 state s3, trace back to moment T3 state s2, trace back to moment T2 state s1.This decode results of taking turns that trace-back process obtains moment T2 is bit 0.
In like manner, can continue decoding and obtain the decode results of moment T3 to moment T7, the decoded result of whole receiving sequence is 1011100, and decoding is correct.
Implement adjustment mode two, reduce memory depth.
The memory width of hypothetical trellis vector is 4 constant, memory depth is adjusted to 3 from 4, then does following adjustment to said process.Backtracking span is adjusted to 3, then, when the moment, T3 was complete in calculating, starts to carry out back tracking operation.Similarly, for convenience of description, suppose that second segment receiving sequence is the same with first paragraph receiving sequence.
The path accumulated value of all states of moment T3 is compared, can show that the state wherein with minimum value is s2, grid vector when namely with s2 being grid vector and the coding of termination in multiple grid vector of decoding has maximum equal probabilities, so the state of the starting point moment T3 of backtracking is defined as s2.
In calculating before, obtained staying of the state s2 of moment T3 selects grid vector to be lower branch road, in like manner can stay from each state in each moment the continuous print grid vector selecting grid vector to obtain having maximum equal probabilities successively toward moment in the past, such continuous print grid vector is, from moment T3 state s2, trace back to moment T2 state s1, trace back to moment T1 state s2.This decode results of taking turns that trace-back process obtains moment T1 is bit 1.
In like manner, can continue decoding and obtain the decode results of moment T2 to moment T7, the decoded result of whole receiving sequence is 1011100.
When interchannel noise interference value C is greater than channel average interference value σ, corresponding adjustment mode increases memory width and/or increases memory depth.Supplement and be described below:
Implement adjustment mode three, increase memory width.
The memory depth of hypothetical trellis vector is constant, and memory width is adjusted to 8 from 4, then to the following adjustment of described process do above.For convenience of description, suppose that second segment receiving sequence is the same with first paragraph receiving sequence.
To moment T1, according to previously described algorithm, calculate the path accumulated value of each state, because the grid vector generated is 8, so do not need to screen, using the path accumulated value of upper and lower branch road all as the calculating basis of moment T2.The path accumulated value of the upper branch road of the s0 of such moment T1 is 1, and the path accumulated value of lower branch road is 11; The path accumulated value of the upper branch road of s1 is 10, and the path accumulated value of lower branch road is 12; The path accumulated value of the upper branch road of s2 is 1, and the path accumulated value of lower branch road is 11; The path accumulated value of the upper branch road of s3 is 12, and the path accumulated value of lower branch road is 10.
To moment T2, the previous state of the upper branch road of state s0 is the s0 of moment T1, there are 2 grid vector in the s0 due to moment T1, so also need when the upper branch road of the s0 of calculating moment T2 the path accumulated value considering these two grid vector, because the current path accumulated value of the upper branch road of the s0 of moment T2 is 1, the accumulated value of branching path up and down of previous state s0 is 1 and 11 respectively, so the path accumulated value of the upper branch road of the s0 of moment T2 is 2 and 12.In like manner the path accumulated value of the lower branch road of the s0 of moment T2 is 11 and 13.
Due to according to above-mentioned algorithm, 16 grid vector can be developed at moment T2, and be the restriction of 8 according to memory width, need the grid vector of each state to moment T2 to screen.To the state s0 of moment T2, owing to there are four grid vector, the grid vector that 2 path accumulated values of upper branch road are respectively 2 and 12 respectively, the grid vector of 11 and 13 is respectively with 2 path accumulated values of lower branch road, screen according to these path accumulated values, two wherein larger grid vector abandon, and in residue, the path accumulated value of branch road is the grid vector of 2 and the path accumulated value of lower branch road is the grid vector of 11.
In like manner, according to above-mentioned algorithm, the remaining grid vector of the s1 of moment T2 to be the path accumulated value of upper branch road be 1 grid vector and the path accumulated value that is all branch road be the grid vector of 11; The remaining grid vector of s2 is the path accumulated value of upper branch road be the grid vector of 2 and the path accumulated value of lower branch road is the grid vector of 11; The remaining grid vector of s3 to be the path accumulated value of upper branch road be 3 grid vector and the path accumulated value that is all branch road be the grid vector of 10.
In like manner, according to above-mentioned algorithm, the remaining grid vector of the s0 of moment T3 is the path accumulated value of upper branch road be the grid vector of 2 and the path accumulated value of lower branch road is the grid vector of 3; The remaining grid vector of s1 is the path accumulated value of upper branch road be the grid vector of 3 and the path accumulated value of lower branch road is the grid vector of 4; The remaining grid vector of s2 is the path accumulated value of upper branch road be the grid vector of 4 and the path accumulated value of lower branch road is the grid vector of 1; The remaining grid vector of s3 to be the path accumulated value of upper branch road be 3 grid vector and the path accumulated value that is all branch road be the grid vector of 4.
In like manner, according to above-mentioned algorithm, the remaining grid vector of the s0 of moment T4 to be the path accumulated value of upper branch road be 3 grid vector and the path accumulated value that is all branch road be the grid vector of 4; The remaining grid vector of s1 is the path accumulated value of upper branch road be the grid vector of 2 and the path accumulated value of lower branch road is the grid vector of 3; The remaining grid vector of s2 to be the path accumulated value of upper branch road be 3 grid vector and the path accumulated value that is all branch road be the grid vector of 4; The remaining grid vector of s3 to be the path accumulated value of upper branch road be 4 grid vector and the path accumulated value that is all branch road be the grid vector of 1.
Because memory depth is 4, so start back tracking operation.The path accumulated value of all states of moment T4 is compared, can show that the state wherein with minimum value is s3, grid vector when namely with s3 being grid vector and the coding of termination in multiple grid vector of decoding has maximum equal probabilities, so the state of the starting point moment T4 of backtracking is defined as s3.
Obtained in calculating before the state s3 of moment T4 stay select grid vector be on branch road, and according to grid vector figure, the previous state that the upper branch road of state s3 is corresponding is s2, in like manner can stay from each state in each moment the continuous print grid vector selecting grid vector to obtain having maximum equal probabilities successively toward moment in the past, so just obtaining continuous print grid vector is, from moment T4 state s3, trace back to moment T3 state s2, trace back to moment T2 state s1, trace back to moment T1 state s2, trace back to moment T0 state s0.This decode results of taking turns that trace-back process obtains moment T1 is bit 1.
In like manner, according to above-mentioned algorithm, can obtain the decode results of moment T2 to T7, the decode results of whole receiving sequence is 1011100.
Implement adjustment mode four, increase memory depth.
The memory width of hypothetical trellis vector is 4 constant, memory depth is adjusted to 5 from 4, then does following adjustment to said process.Backtracking span is adjusted to 5, then, when the moment, T5 was complete in calculating, starts to carry out back tracking operation.
The path accumulated value of all states of moment T5 is compared, can show that the state wherein with minimum value is s1, grid vector when namely with s1 being grid vector and the coding of termination in multiple grid vector of decoding has maximum equal probabilities, so the state of the starting point moment T5 of backtracking is defined as s1.
In calculating before, obtained staying of the state s1 of moment T5 selects grid vector to be lower branch road, in like manner can stay from each state in each moment the continuous print grid vector selecting grid vector to obtain having maximum equal probabilities successively toward moment in the past, such continuous print grid vector is, from moment T5 state s1, trace back to moment T4 state s3, trace back to moment T3 state s2, trace back to moment T2 state s1, trace back to moment T1 state s2.This decode results of taking turns that trace-back process obtains moment T1 is bit 1.
In like manner, can continue decoding and obtain the decode results of moment T2 to moment T7, the decoded result of whole receiving sequence is 1011100.
It should be noted that, after adjusting parameter according to first paragraph receiving sequence according to above-mentioned adjustment mode, then based on viterbi algorithm decoding second segment receiving sequence; After adjusting parameter according to second segment receiving sequence according to above-mentioned adjustment mode, then to decode the 3rd section of receiving sequence based on viterbi algorithm; So analogize, until by complete for the decoding of all receiving sequences.
Fig. 4 is the schematic diagram of a kind of dynamic Viterbi decoding device of the present invention, comprising:
Viterbi arithmetic element, for decoding to current receiving sequence based on viterbi algorithm with the parameter value of setting, obtains decoding.
The parameter adjustment unit be connected with described Viterbi arithmetic element, for adjusting the parameter value of memory depth and/or memory width in the viterbi algorithm of described Viterbi arithmetic element in the scope of described adjustment lower limit and the described adjustment upper limit.
The output deposit unit be connected with described Viterbi arithmetic element, for the decoding that temporary described Viterbi arithmetic element will obtain after the decoding of current receiving sequence.
The input deposit unit be connected with described Viterbi arithmetic element, that decodes for the described Viterbi arithmetic element of temporary confession works as receiving sequence described in the last period.
The receiving element be connected with described input deposit unit, for receiving described receiving sequence, after described Viterbi arithmetic element is by current receiving sequence decoding, next section of receiving sequence is transferred to described input deposit unit by described receiving element.
Viterbi arithmetic element parameter setting unit as shown in Figure 4 also comprises, for setup parameter value in the scope of described adjustment lower limit and the described adjustment upper limit, and accept the adjustment that described parameter adjustment unit carries out described parameter value, described parameter value comprises memory depth and/or memory width, the branch metric of described memory depth to be the backtracking span of grid chart in viterbi algorithm and/or described memory width be grid chart in viterbi algorithm; Described parameter setting unit, also for the accumulated value of state each in viterbi algorithm is set as preset value, wherein, the accumulated value arranging one of them state is less than the accumulated value of all the other states.
Dynamic Viterbi decoding device as shown in Figure 4, also comprises:
The coding unit be connected with described output deposit unit, for convolution coding is carried out in described decoding, obtains coded sequence.
The noise evaluation unit be connected respectively with described input deposit unit with described coding unit, for described receiving sequence and described coded sequence are carried out computing, obtains channel interference values.
Dynamic Viterbi decoding device as shown in Figure 4, shown parameter adjustment unit comprises:
Limit processing unit, for being described adjustment lower limit when described memory depth and/or described memory width, when still needing reduce described memory depth and/or reduce described memory width, maintains described memory depth and/or described memory width is constant; Described limit processing unit, also for being the described adjustment upper limit when described memory depth and/or described memory width, when still needing increase described memory depth and/or increase described memory width, maintains described memory depth and/or described memory width is constant.
Dynamic Viterbi decoding device as shown in Figure 4, shown noise evaluation unit also comprises:
Comparing unit, for by described channel interference values compared with the average interference value of channel, and the result compared is outputted to described parameter adjustment unit, described parameter adjustment unit adjusts described memory depth in described parameter setting unit and/or described memory width according to the result of described comparison.
Wherein, described comparing unit also comprises average calculation unit, and for calculating average interference value, described average interference value is the mean value of channel interference values described in several.
Described noise evaluation unit comprises one pole encoding operation unit, for working as described receiving sequence Q (q
0, q
1, q
2... q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2... p
n-1, p
n) for unipolarity encode time, adopt following formula to carry out computing to obtain described channel interference values,
wherein C is described channel interference values.
Described noise evaluation unit comprises bipolar coding arithmetic element, for working as described receiving sequence Q (q
0, q
1, q
2... q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2... p
n-1, p
n) for bipolar coding time, adopt following formula to carry out computing to obtain described channel interference values,
wherein C is described channel interference values.
Above-described embodiment of the present invention, does not form limiting the scope of the present invention.Any amendment done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within claims of the present invention.
Claims (10)
1. a dynamic Viterbi coding/decoding method, is characterized in that, comprising:
Current receiving sequence is decoded based on viterbi algorithm with the parameter value of setting, obtain decoding, described parameter value comprises memory depth and/or memory width, and described memory depth is the backtracking span of grid chart in viterbi algorithm and/or described memory width is the quantity staying routing footpath in viterbi algorithm in convolutional encoder circuit;
Based on the situation of interchannel noise and/or the effect of decoding, described parameter value is adjusted in adjustment lower limit with the scope of the adjustment upper limit;
With the viterbi algorithm after the described parameter value of adjustment, next section of receiving sequence is decoded;
Based on viterbi algorithm, current receiving sequence is decoded at the parameter value of described setting, after obtaining the step of decoding, also comprises:
Convolution coding is carried out in described decoding, obtains coded sequence;
Described receiving sequence and described coded sequence are carried out computing, obtains channel interference values;
Described described parameter value step of adjusting in the scope of adjustment lower limit and the adjustment upper limit to be comprised:
According to the result of described channel interference values compared with the average interference value of channel, described memory depth and/or described memory width is adjusted in the scope of described adjustment lower limit and the described adjustment upper limit, wherein, described average interference value is the mean value of a predetermined number described channel interference values;
Described adjustment mode comprises, and when described channel interference values is less than described mean value, reduces described memory depth and/or reduces described memory width; When described channel interference values is greater than described mean value, increases described memory depth and/or increase described memory width; When described channel interference values equals described mean value, maintain described memory depth and/or described memory width is constant.
2. dynamic Viterbi coding/decoding method according to claim 1, is characterized in that, decodes based on viterbi algorithm at the parameter value of described setting to current receiving sequence, before obtaining the step of decoding, comprising:
The accumulated value of state each in viterbi algorithm is set as preset value, and wherein, the accumulated value arranging one of them state is less than the accumulated value of all the other states.
3. dynamic Viterbi coding/decoding method according to claim 1, is characterized in that, describedly also comprises described parameter value step of adjusting in the scope of adjustment lower limit and the adjustment upper limit:
The adjustment lower limit depthMin=m of described memory depth, m is encoding constraint length, adjustment upper limit depthMax=receiveLength/symbolOutWidth, receiveLength is the bit length of described current receiving sequence, symbolOutWidth is the bit length of the output of arranging in convolution coding, and/or the adjustment lower limit of described memory width is 2
m-2, the adjustment upper limit is 2
m, wherein m is encoding constraint length;
When described memory depth and/or described memory width are described adjustment lower limit, when still needing reduce described memory depth and/or reduce described memory width, maintain described memory depth and/or described memory width is constant;
When described memory depth and/or described memory width are the described adjustment upper limit, when still needing increase described memory depth and/or increase described memory width, maintain described memory depth and/or described memory width is constant.
4. dynamic Viterbi coding/decoding method according to claim 1, is characterized in that, the account form of described channel interference values comprises:
When described current receiving sequence, described coded sequence are unipolarity coding, by described receiving sequence Q (q
0, q
1, q
2..., q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2..., p
n-1, p
n) the concrete operation formula that carries out computing is,
wherein C is described channel interference values.
5. dynamic Viterbi coding/decoding method according to claim 1, is characterized in that, the account form of described channel interference values comprises:
When described current receiving sequence, described coded sequence are bipolar coding, by described receiving sequence Q (q
0, q
1, q
2..., q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2..., p
n-1, p
n) the concrete operation formula that carries out computing is,
wherein C is described channel interference values.
6. a dynamic Viterbi decoding device, is characterized in that, comprising:
Viterbi arithmetic element, for decoding to current receiving sequence based on viterbi algorithm with the parameter value of setting, obtains decoding;
The parameter adjustment unit be connected with described Viterbi arithmetic element, for based on the situation of interchannel noise and/or the effect of decoding, in adjustment lower limit with the scope of the adjustment upper limit, adjust the parameter value of memory depth and/or memory width in the viterbi algorithm of described Viterbi arithmetic element;
The output deposit unit be connected with described Viterbi arithmetic element, for the decoding that temporary described Viterbi arithmetic element will obtain after the decoding of current receiving sequence;
The input deposit unit be connected with described Viterbi arithmetic element, that decodes for the described Viterbi arithmetic element of temporary confession works as receiving sequence described in the last period;
The receiving element be connected with described input deposit unit, for receiving described receiving sequence, after described Viterbi arithmetic element is by current receiving sequence decoding, next section of receiving sequence is transferred to described input deposit unit by described receiving element;
Also comprise:
The coding unit be connected with described output deposit unit, for convolution coding is carried out in described decoding, obtains coded sequence;
The noise evaluation unit be connected respectively with described input deposit unit with described coding unit, for described receiving sequence and described coded sequence are carried out computing, obtains channel interference values;
Described noise evaluation unit also comprises:
Comparing unit, for by described channel interference values compared with the average interference value of channel, and the result compared is outputted to described parameter adjustment unit, described parameter adjustment unit adjusts described memory depth and/or described memory width according to the result of described comparison;
Wherein, described comparing unit also comprises average calculation unit, and for calculating average interference value, described average interference value is the mean value of a predetermined number described channel interference values.
7. dynamic Viterbi decoding device as claimed in claim 6, it is characterized in that, described Viterbi arithmetic element comprises:
Parameter setting unit, for setup parameter value in the scope of described adjustment lower limit and the described adjustment upper limit, and accept the adjustment that described parameter adjustment unit carries out described parameter value, described parameter value is the parameter value of memory depth and/or memory width, and described memory depth is the backtracking span of grid chart in viterbi algorithm and/or described memory width is the quantity staying routing footpath in viterbi algorithm in convolutional encoder circuit;
Described parameter setting unit, also for the accumulated value of state each in viterbi algorithm is set as preset value, wherein, the accumulated value arranging one of them state is less than the accumulated value of all the other states.
8. dynamic Viterbi decoding device according to claim 6, is characterized in that, described parameter adjustment unit comprises:
Limit processing unit, for being described adjustment lower limit when described memory depth and/or described memory width, when still needing reduce described memory depth and/or reduce described memory width, maintains described memory depth and/or described memory width is constant;
Described limit processing unit, also for being the described adjustment upper limit when described memory depth and/or described memory width, when still needing increase described memory depth and/or increase described memory width, maintains described memory depth and/or described memory width is constant.
9. dynamic Viterbi decoding device as claimed in claim 6, is characterized in that:
Described noise evaluation unit comprises one pole encoding operation unit, for working as described receiving sequence Q (q
0, q
1, q
2..., q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2..., p
n-1, p
n) for unipolarity encode time, adopt following formula to carry out computing to obtain described channel interference values,
wherein C is described channel interference values.
10. dynamic Viterbi decoding device as claimed in claim 6, is characterized in that:
Described noise evaluation unit comprises bipolar coding arithmetic element, for working as described receiving sequence Q (q
0, q
1, q
2..., q
n-1, q
n) and described coded sequence P (p
0, p
1, p
2..., p
n-1, p
n) for bipolar coding time, adopt following formula to carry out computing to obtain described channel interference values,
wherein C is described channel interference values.
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| US6680986B1 (en) * | 1999-11-22 | 2004-01-20 | Intelsat Global Service Corporation | Method for implementing shared channel decoder for onboard processing satellites |
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| US6680986B1 (en) * | 1999-11-22 | 2004-01-20 | Intelsat Global Service Corporation | Method for implementing shared channel decoder for onboard processing satellites |
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