CN102122658B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN102122658B
CN102122658B CN 201010033874 CN201010033874A CN102122658B CN 102122658 B CN102122658 B CN 102122658B CN 201010033874 CN201010033874 CN 201010033874 CN 201010033874 A CN201010033874 A CN 201010033874A CN 102122658 B CN102122658 B CN 102122658B
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silicon substrate
dielectric
device region
sti
sti district
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CN102122658A (en
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钟汇才
梁擎擎
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The invention provides a semiconductor structure which comprises a silicon substrate, a device region, an STI (shallow trench isolation) region and a dielectric layer, wherein the device region and the STI region are formed in the silicon substrate, the STI region is etched and filled from the bottom of the silicon substrate so as to avoid the emergence of a broken corner, and dielectric material is filled in the STI region; and the dielectric layer is formed in the silicon substrate and positioned below the device region and the STI region, and the silicon substrate is further formed below the dielectric layer. The STI region is etched and filled from the bottom of the substrate, thereby ensuring that no broken corner exists between the formed STI region and the device region and further significantly improving the performances of a device.

Description

Semiconductor structure and forming method thereof
Technical field
The present invention relates to semiconductor manufacturing and design field, particularly a kind of semiconductor structure and forming method thereof, this semiconductor structure can reduce the unfilled corner (divot) that exists between STI (silicon trench isolation) and the device region effectively.
Background technology
The fast development of integrated circuit fabrication process is so that semiconductor product is day by day integrated and miniaturization.Yet, integrated along with product, the isolation structure size of the size of semiconductor subassembly and isolation of semiconductor assembly is thereupon reduction also.Therefore, in semiconductor fabrication process, it is then more difficult how to form good isolation structure.Existing a kind of method that forms isolation structure remains the oxide layer that forms by selective oxidation, yet this kind mode produces the problem that beak corrodes for the high semiconductor device of integrated level and inapplicable easily.Therefore, at present take STI (silicon trench isolation) technique as main flow, be particularly suitable for time manufacturing of the integrated circuit that micron is following.
Yet in the chemical mechanical polish process of STI technique, along SiO 2The mechanical stress that/Si interface occurs can cause producing unfilled corner usually between STI district and device region (active silicon), and as shown in Figure 1, unfilled corner will cause current leakage and the other problems of device, thereby can reduce performance of devices.Particularly along with constantly the reducing of device size, this problem will be more and more serious.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, particularly solves in the prior art because the problem that the device performance that the unfilled corner between sti structure and the device region causes descends.
For achieving the above object, one aspect of the present invention proposes a kind of semiconductor structure, comprising: silicon substrate; Be formed on device region and STI district in the described silicon substrate, wherein, described STI district forms to avoid occurring unfilled corner from bottom etching and the filling of described silicon substrate, and is filled with dielectric material in the described STI district; Be formed in the described silicon substrate and be positioned at described device region and the STI district under dielectric layer, wherein, also be formed with silicon substrate under the described dielectric layer.
The embodiment of the invention has also proposed a kind of method that forms the semiconductor silicon substrate, may further comprise the steps: silicon substrate is provided; Form STI district and device region to avoid occurring unfilled corner from the bottom etching of described silicon substrate; Adopt dielectric material fill described STI district and be formed in the described silicon substrate and be positioned at described device region and the STI district under dielectric layer; Bonding other silicon substrates under described dielectric layer; Remove silicon substrate on described STI district and the device region to form sti structure.
The present invention is by from the bottom etching of substrate and fill the STI district, so that do not have unfilled corner between the STI district that forms and the device region, thus significantly improve performance of devices.
The aspect that the present invention adds and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the schematic diagram of the unfilled corner that produces between STI district and device region in the prior art;
Fig. 2 is the schematic diagram of the semiconductor structure that does not have unfilled corner of the embodiment of the invention;
Fig. 3-9 is the profile of the pilot process of the above-mentioned semiconductor structure method of the formation of the embodiment of the invention.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein identical or similar label represents identical or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between the various embodiment that discuss of institute and/or the setting.In addition, the various specific technique that the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
The present invention mainly is by from the bottom etching of substrate and fill the STI district, so that do not have unfilled corner between the STI district that forms and the device region, thus significantly improve performance of devices.
As shown in Figure 2, be the schematic diagram of the semiconductor structure that does not have unfilled corner of the embodiment of the invention.This semiconductor structure comprises silicon substrate 100, be formed on device region 120 and STI district 110 in the silicon substrate 100, wherein, in embodiments of the present invention, STI district 110 forms to avoid occurring unfilled corner from bottom etching and the filling of silicon substrate 100, and be filled with dielectric material in the described STI district 110, for example have the various dielectric insulation materials of various stress such as SiO 2, Si 3N 4, Ta 2O 5Or the combination of described multiple dielectric material, also comprise be formed in the silicon substrate 100 and be positioned at device region 120 and STI district 110 under dielectric layer 130, wherein, also be formed with silicon substrate under the dielectric layer 130, thereby can form the substrat structure of SOI (silicon-on-insulator).In one embodiment of the invention, preferably, the dielectric material in the dielectric layer 130 is identical with the dielectric material of filling in the STI district 110, for example all is SiO 2In addition, can adopt the mode of bonding other silicon substrates under dielectric layer 130, to form silicon substrate.In an embodiment of the present invention, can in device region 120, form MOSFET device and/or non-FET device 140.
In one embodiment of the invention, the sidewall in STI district 110 can be vertical, also can tilt, and perhaps any other possible shapes also should be within the protection range of invention of running quickly.
Alternatively, in other embodiments of the invention, in device region 110 and STI district 120, and also have one or more layers backing layer (not shown) between device region 110 and the dielectric layer 130, this backing layer can comprise that the various dielectric insulation materials with various stress are such as SiO 2, Si 3N 4, Ta 2O 5Or the combination of described multiple dielectric material.
The above-mentioned semiconductor structure that proposes for a more clear understanding of the present invention; the invention allows for the embodiment of the method that forms above-mentioned semiconductor structure; it should be noted that; those skilled in the art can select kinds of processes to make according to above-mentioned semiconductor structure; dissimilar product line for example; different technological process etc.; if but the semiconductor structure that these techniques are made adopts and the essentially identical structure of said structure of the present invention; reach essentially identical effect, so also should be included within protection scope of the present invention.In order clearerly to understand the present invention, below will specifically describe the method and the technique that form said structure of the present invention, need to prove that also following steps only are schematic, be not limitation of the present invention, those skilled in the art also can realize by other techniques.
Shown in Fig. 3-9, be the profile of the pilot process of the above-mentioned semiconductor structure method of the formation of the embodiment of the invention, the method may further comprise the steps:
Step 1 provides silicon substrate 100.
Step 2 is from etching formation STI district 110, bottom and the device region 120 of silicon substrate 100, as shown in Figure 3.In this embodiment of the present invention, the sidewall in STI district 110 can be vertical (as shown in Figure 3), also can be (as shown in Figure 4) of tilting, and other any suitable shapes also can be applicable among the present invention certainly.
Step 3 is filled STI district 110 from the bottom of silicon substrate 100, in one embodiment, can adopt oxide to fill, such as SiO 2, high dielectric constant material, have the Si of various stress 3N 4, Ta 2O 5Or its combination, as shown in Figure 5.In one embodiment of the invention, when STI district 110 was filled, the dielectric material of filling can exceed STI district 110, formed one deck dielectric layer under STI district 110 and device region 120.
Step 4 is carried out chemico-mechanical polishing CMP processing to the dielectric layer that forms under STI district 110 and the device region 120 and is carried out planarization with the surface to dielectric layer.
Alternatively, in embodiments of the present invention, before STI district 110 filled media materials, also can one or more layers backing layer 150 of first deposit, as shown in Figure 6, backing layer 150 can comprise SiO 2, have a Si of various stress 3N 4, Ta 2O 5Perhaps combination of described dielectric material etc.If deposit backing layer 150, thereby then after layer by layer the deposition body dielectric film fill STI district 110, and carry out CMP.
Step 5 in embodiments of the present invention, alternatively, does not satisfy the requirement of SOI substrate if fill the thickness of dielectric layers of STI district 110 formation, also needs deposit one deck dielectric layer 130, as shown in Figure 7.
Step 6, bonding other silicon substrates under dielectric layer 130, thus form the SOI substrate, as shown in Figure 8.
Step 7 is removed silicon substrate 100 on STI district 110 and the device region 120 to form final sti structure, as shown in Figure 9, can not produce unfilled corner between STI district 110 and the device region 120 by this mode.Can adopt the silicon substrate 100 on various ways removal STI district 110 and the device region 120, for example the CMP mode is until stop on the medium of filling.In addition, can also adopt other modes to remove silicon substrate 100 on STI district 110 and the device region 120, for example oxidation (Oxidation) mode, oxidation (Oxidation) mode is with after the top silicon crystal material oxidation, then with HF acid oxide etch is fallen silicon substrate 100.
Step 8 is utilized traditional handicraft, can form MOSFET device and/or non-FET device 140 in device region 120, and as shown in Figure 2, this view only is schematically, and those skilled in the art also can form other devices certainly.
The present invention is by from the bottom etching of substrate and fill the STI district, so that do not have unfilled corner between the STI district that forms and the device region, thus significantly improve performance of devices.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment that scope of the present invention is by claims and be equal to and limit.

Claims (10)

1. a semiconductor structure is characterized in that, comprising:
Silicon substrate;
Be formed on device region and silicon trench isolation STI district in the described silicon substrate, wherein, described STI district forms to avoid occurring unfilled corner from bottom etching and the filling of described silicon substrate, and described STI is filled with dielectric material in the district, the sidewall in described STI district tilts, in described device region and described STI district, and have one or more layers backing layer between described device region and the described dielectric layer, described backing layer comprises having various stress dielectric insulation materials;
Be formed in the described silicon substrate and be positioned at described device region and the STI district under dielectric layer, wherein, also be formed with another silicon substrate under the described dielectric layer.
2. semiconductor structure as claimed in claim 1 is characterized in that, described dielectric insulation material comprises SiO 2, Si 3N 4, Ta 2O 5Or described its combination.
3. semiconductor structure as claimed in claim 1 is characterized in that, the MOSFET device that forms in described device region and/or non-FET device.
4. semiconductor structure as claimed in claim 1 is characterized in that, dielectric material and the dielectric material in the described dielectric layer of filling in the described STI district comprise the dielectric insulation material with various stress.
5. semiconductor structure as claimed in claim 4 is characterized in that, institute's dielectric insulation material comprises SiO 2, Si 3N 4, Ta 2O 5Or its combination.
6. a method that forms the semiconductor silicon substrate is characterized in that, may further comprise the steps:
Silicon substrate is provided;
Form STI district and device region to avoid occurring unfilled corner from the bottom etching of described silicon substrate;
Form one or more layers backing layer between described device region and described dielectric layer, described backing layer comprises the dielectric insulation material with various stress;
Adopt dielectric material fill described STI district and be formed in the described silicon substrate and be positioned at described device region and the STI district under dielectric layer, the sidewall in described STI district tilts;
Bonding another silicon substrate under described dielectric layer;
Remove silicon substrate on described STI district and the device region to form sti structure.
7. the method for formation semiconductor silicon substrate as claimed in claim 6 is characterized in that, also comprises:
In described device region, form MOSFET device and/or non-FET device.
Described backing layer comprises the dielectric insulation material with various stress.
8. the method for formation semiconductor silicon substrate as claimed in claim 6 is characterized in that, described dielectric insulation material comprises SiO 2, Si 3N 4, Ta 2O 5Or its combination.
9. the method for formation semiconductor silicon substrate as claimed in claim 6 is characterized in that, dielectric material and the dielectric material in the described dielectric layer of filling in the described STI district comprise the dielectric insulation material with various stress.
10. the method for formation semiconductor silicon substrate as claimed in claim 9 is characterized in that, described dielectric insulation material comprises SiO 2, Si 3N 4, Ta 2O 5Or its combination.
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CN103165622B (en) * 2011-12-09 2016-08-31 中国科学院微电子研究所 A kind of semiconductor structure and manufacture method thereof
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436173A (en) * 1993-01-04 1995-07-25 Texas Instruments Incorporated Method for forming a semiconductor on insulator device
US5597739A (en) * 1994-01-19 1997-01-28 Sony Corporation MOS transistor and method for making the same
JP4082250B2 (en) * 2003-03-17 2008-04-30 村田機械株式会社 Thread loosening device for spinning machine

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436173A (en) * 1993-01-04 1995-07-25 Texas Instruments Incorporated Method for forming a semiconductor on insulator device
US5597739A (en) * 1994-01-19 1997-01-28 Sony Corporation MOS transistor and method for making the same
JP4082250B2 (en) * 2003-03-17 2008-04-30 村田機械株式会社 Thread loosening device for spinning machine

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