CN102117655A - Memory chip - Google Patents
Memory chip Download PDFInfo
- Publication number
- CN102117655A CN102117655A CN2010100002047A CN201010000204A CN102117655A CN 102117655 A CN102117655 A CN 102117655A CN 2010100002047 A CN2010100002047 A CN 2010100002047A CN 201010000204 A CN201010000204 A CN 201010000204A CN 102117655 A CN102117655 A CN 102117655A
- Authority
- CN
- China
- Prior art keywords
- memory chip
- input pad
- voltage source
- signal
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a memory chip. The memory chip is operated in a plurality of modes and comprises a select input pad and a judgment circuit, wherein the judgment circuit is coupled with the select input pad and used for generating a judgment signal according to the current state of the select input pad; the judgment signal indicates a mode in which the memory chip is being operated; the judgment circuit comprises a detection unit and a sampling unit; the detection unit is coupled with a first voltage source and the select input pad and is controlled by a control signal to generate at least one detection signal according to the current state of the select input pad; and the sampling unit receives the at least one detection signal and samples the at least one detection signal to generate the judgment signal after the control signal is enabled. When the control signal is enabled, the level of the at least one detection signal is changed by voltage provided by the first voltage source.
Description
Technical field
The present invention is relevant for a kind of memory chip, particularly relevant for a kind of decision circuitry, judges that in order to the state according to the selection input pad of a memory chip this memory chip is to be operating as single memory crystal grain or to stack one in the memory crystal grain.
Background technology
Fig. 1 represents the memory chip of 256Mb.Consult Fig. 1, memory chip 1 comprises that 23 address input pads (address pad) A0～A22, selects input pad OP and idle input pad NC.When memory chip 1 is operating as single memory crystal grain, select input pad OP and idle input pad NC all to be in floating state.Draw on memory chip 1 inside weak/pull-down circuit (weak pull high-lowcircuit) little by little will be connected in and select the internal node of input pad OP to be pulled to a high/low voltage quasi position.In the following description, be that pulling operation is that example illustrates a little less than reaching with weak pull-up circuit.
In some applications, the memory chip 1 of at least two Fig. 1 can stack and form a storage arrangement.As shown in Figure 2, be that example illustrates with 512Mb storage arrangement 2 with two 256Mb memory chips 20 that stack and 21.Each has the structure identical with the memory chip 1 of Fig. 1 in the memory chip 20 and 21 that stacks, and the idle input pad NC of memory chip 1 is as the 24th address input pad A23, with addressing two these memory chips 20 and 21.Top memory chip 20 stack below on the memory chip 21, and exist gap 23 between the two.Fig. 3 represents the connection state between between the input pad A0～A23 of the address of memory chip 20 and 21.In order clearly to represent this connection state, with and row arrangement present memory chip 20 and 21, yet in fact, top memory chip 20 stacks on below memory chip 21, as shown in Figure 2.Consult Fig. 3, the address input pad A0～A23 of the address input pad A0 of memory chip 20～A23 difference connected storage chip 21 is in address input pad A0 '～A23 '. Memory chip 20 and 21 is by address input pad A0 '～A23 ' receiver address signal.
In Fig. 3, the selection input pad OP of top memory chip 20 connects high voltage source VDD, and connects internal node of this selection input pad OP so be in high levle.The selection input pad OP of below memory chip 21 connects low-voltage source VSS, and connects internal node of this selection input pad OP so be in low level.Therefore, when address input pad A23 ' received a high logic accurate position signal (H), top memory chip 20 was enabled, and below memory chip 21 then is not enabled.On the contrary, when address input pad A23 ' received a low logic accurate position signal (L), below memory chip 21 was enabled, and top memory chip 20 then is not enabled.
Therefore, a memory chip (for example memory chip 20 and 21) selects the state of input pad to be operable under three patterns according to it.Under first pattern, when the selection input pad OP of memory chip is in floating state, memory chip is operating as single memory crystal grain.Under second pattern, when the selection input pad OP of memory chip was connected to high voltage source VDD, this memory chip was operating as the two top memory crystal grain that stack in the memory crystal grain.Under three-mode, when the selection input pad OP of memory chip was connected to low-voltage source VSS, this memory chip was operating as the two below memory crystal grain that stack in the memory crystal grain.Under these three patterns, the internal node of the selection input pad OP of connected storage chip is drawn (weakly pulled high), Qiang Shangla (strongly pulled high) respectively, reaches drop-down by force (strongly pulled low) by on weak.According to above-mentioned, when a memory chip is operated under first pattern and second pattern, connect its internal node of selecting input pad OP by on draw.Therefore, when internal node was in high levle, memory chip can't be judged and itself just is being operating as under the single memory crystal grain (first pattern) or is operating as the two top memory crystal grain (second pattern) that stack in the memory crystal grain.This situation may occur in as two and stack in the memory crystal grain on the demand of memory chip of top memory crystal grain, for example the top memory chip 20 of Fig. 2.
Suppose the selection input pad OP that weak pull-down circuit and weak pulling operation are applied to float.According to the above description, when a memory chip is operated, connect its internal node of selecting input pad OP under first pattern and three-mode by drop-down.Therefore, when internal node was in low level, memory chip can't be judged and itself just is being operating as under the single memory crystal grain (first pattern) or is operating as the two below memory crystal grain (three-mode) that stack in the memory crystal grain.This situation may occur in as two and stack in the memory crystal grain on the demand of memory chip of below memory crystal grain, for example the top memory chip 21 of Fig. 2.
Therefore, expectation provides a kind of decision circuitry, and it can judge that a memory chip just is being operating as single memory crystal grain or is stacking one in the memory crystal grain.
Summary of the invention
The invention provides a kind of memory chip, operate in a plurality of patterns.This memory chip comprises selects input pad (option pad) and decision circuitry.Select input pad to have a plurality of states.Decision circuitry couples the selection input pad, in order to produce the judgement signal according to the current state of selecting input pad.Judge that signal indicates memory chip and just operating under which pattern.Decision circuitry comprises detecting unit and sampling unit.Detecting unit couples first voltage source and selects input pad.Detecting unit is controlled by a control signal to produce at least one detection signal according to the current state of selecting input pad.Sampling unit receives this at least one detection signal.After this control signal was enabled, sampling unit was taken a sample to this at least one detection signal and is judged signal to produce.When control signal was enabled, the voltage that the accurate position of this at least one detection signal is provided by first voltage source changed.
According to technical scheme provided by the invention, can judge that a memory chip just is being operating as single memory crystal grain or is stacking in the memory crystal grain one of them.
Description of drawings
Fig. 1 represents the synoptic diagram of memory chip;
Fig. 2 represents to have two storage arrangements that stack memory chip;
Fig. 3 represents the connection state between between the input pad A0～A23 of the address of memory chip 20 and 21;
Fig. 4 represents the memory chip according to the embodiment of the invention;
The embodiment of decision circuitry 40 in Fig. 5 presentation graphs 4;
An embodiment of detecting unit 50 in Fig. 6 presentation graphs 5;
Fig. 7 a, Fig. 7 b to Fig. 7 c represent the oscillogram according to the embodiment of Fig. 6;
Another embodiment of detecting unit 50 in Fig. 8 presentation graphs 5;
Fig. 9 a, Fig. 9 b to Fig. 9 c represent the oscillogram according to the embodiment of Fig. 8;
The another enforcement of detecting unit 50 is sharp in Figure 10 presentation graphs 5;
Figure 11 a, Figure 11 b to Figure 11 c represent the oscillogram according to the embodiment of Figure 10;
Another enforcement of detecting unit 50 is sharp in Figure 12 presentation graphs 5;
Figure 13 a, Figure 13 b to Figure 13 c represent the oscillogram according to the embodiment of Figure 12.
Drawing reference numeral
1～memory chip; A0...A22～address input pad;
NC～idle input pad; OP～selection input pad;
2～storage arrangement; 20,21～memory chip;
23～gap; A0...A23～address input pad;
A0 ' ... A23 '～address input pad;
VDD～high voltage source; VSS～low-voltage source;
4～memory chip; 40～decision circuitry;
41～control circuit; A0...A23～address input pad;
OP～selection input pad; S40～judgement signal;
50～detecting unit; 51～sampling unit;
CS～control signal; VS1～voltage source;
50 '～detecting unit; 60～draw/drop down element on weak;
61～switching device; GND～low level voltage;
N60～node; S60～detection signal;
VS2～voltage source; VCC～high levle voltage;
VSS～low-voltage source;
T1, T2, T3, T4～time point;
P1, P2～during;
VDD～high voltage;
50 "～detecting unit; 90,91～switching device;
92～draw/drop down element on weak; N90, N91～node;
S90, S91～detection signal;
T1, T2, T3, T4～time point.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Fig. 4 represents the memory chip according to the embodiment of the invention.Consult Fig. 4, memory chip 4 comprises a plurality of positions input pad, selects input pad OP, decision circuitry 40 and control circuit 41.Select input pad OP to have different states.In this embodiment, select input pad OP to have three kinds of states: the floating state under three patterns, strong high levle state, strong low level state respectively.For instance, when selecting input pad OP to float, select input pad OP to be in floating state.When selecting input pad OP to be connected to high voltage source VDD, select input pad OP to be in strong high levle state.When selecting input pad to be connected to low-voltage source VSS, select input pad OP to be in strong low level state.In this embodiment, memory chip 4 is memory chips of a 256Mb.Because memory chip 4 is operable as two of single memory crystal grain or 512Mb and stacks one in the memory crystal grain.In further embodiments, the address input pad quantity of memory chip is decided according to the size of memory chip.
The embodiment of decision circuitry 40 in Fig. 5 presentation graphs 4.Consult Fig. 5, decision circuitry 40 comprises detecting unit 50 and sampling unit 51.Detecting unit 50 couples voltage source V S1 and selects input pad OP.Judging unit 50 is controlled by control signal CS, to produce at least one detection signal according to the current state of selecting input pad OP.When control signal was enabled, the voltage that the accurate position of this at least one detection signal is provided by voltage source V S1 changed.Sampling unit 51 receives this at least one detection signal, and this at least one detection signal of sampling is judged signal S40 to produce after control signal CS is enabled.
An embodiment of detecting unit 50 in Fig. 6 presentation graphs 5.Consult Fig. 6, detecting unit 50 ' couples selects input pad OP in node N60.Draw/drop down element 60 and switching device 61 on a little less than detecting unit 50 ' comprises.Draw on weak/drop down element 60 is coupled between voltage source V S2 and the node N60.Switch unit 61 is coupled between node N60 and the voltage source V S1, and by the control signal CS institute conducting that is enabled.Suppose just be operating as single memory crystal grain when memory chip 4, promptly just operating in for first pattern following time when memory chip 4, select input pad OP to float, and with the node N60 quilt of selecting input pad OP to be connected a little less than be pulled to a high levle.Therefore, voltage source V S1 provides low level voltage, and for example ground voltage GND, and voltage source V S2 provide high levle voltage, for example operating voltage VCC.Suppose in the case, draw on weak/drop down element 60 is to realize with the PMOS transistor that it is in conducting state according to the control of low-voltage source VSS always, in addition, this PMOS transistor has long passage length.Switching device 61 is to realize with nmos pass transistor, and it is switched on according to the control signal CS that is enabled and have a high levle.In this embodiment, produce a detection signal S60 to take a sample at node N60 by sampling unit 51.
Fig. 7 a represents when memory chip 4 just is being operating as single memory crystal grain (first pattern), the waveform of the voltage of voltage source V CC (VS2), control signal CS, detection signal S60, and the logic value of judging signal S40.As mentioned above, when memory chip 4 is operating as single memory crystal grain, select input pad OP for floating.Consult Fig. 7 a, little by little draw on the high levle voltage VCC by voltage source V S2 the accurate position of detection signal S60.At time point T1, control signal CS is switched to high levle by low level, and promptly control signal CS is enabled.According to being enabled and having the control signal CS of high levle, switch unit 61 is switched in time point T1.Therefore, detection signal S60 is pulled down to the accurate position of the low level voltage GND of voltage source V S1 at once.Detection signal S60 is in the accurate position of the low level voltage GND of voltage source V S1 constantly, switches to low level (be control signal during at time point T2 by counter enabled) to close switching device 61 in time point T2 by high levle up to control signal CS.In other words, when between control signal CS is by time point T1 to T2, being enabled, judge that signal S60 is in the accurate position of the low level voltage GND of voltage source V S1 constantly.After time point T2, detection signal S60 little by little draws on the high levle voltage VCC by voltage source V S2 once more.By the anti-back that enables at interval between a short-term on the time point T3 of P1, because detection signal S60 is little by little by drawing on the low level, 51 couples of detection signal S60 of sampling unit take a sample to obtain first logic value " 0 " at control signal CS.On the time point T4 of P2, sample circuit 51 is taken a sample to obtain second logic value to detection signal S60 once more between distance behind the time point T3 one is long-term.Because detection signal S60 is in the accurate position of the high levle voltage VCC of voltage source V S2, therefore second logic value is " 1 ".First logic value " 0 " forms with second logic value " 1 " judges signal S40.
According to the narration of Fig. 7 a, when memory chip 4 was operating as single memory crystal grain, decision circuitry 40 produced the judgement signal S40 of " 01 " according to the floating state of selecting input pad OP.
Fig. 7 b represents just be operating as two when stacking in the memory crystal grain top memory crystal grain (second pattern), the waveform of the voltage of voltage source V CC (VS2), control signal CS, detection signal S60, and the logic value of judging signal S40 when memory chip 4.In second pattern, select input pad OP to be connected to high voltage source VDD.According to above-mentioned, control signal CS is enabled between time point T1 to T2, and sampling unit 51 is taken a sample to obtain first logic value and second logic value respectively to detection signal S60 on time point T3 and T4 respectively.Shown in Fig. 7 b, under second pattern, first logic value is that " 1 " judges signal S40 with second logic value for " 1 " forms.According to the narration of Fig. 7 b, when memory chip 4 is operating as two when stacking in the memory crystal grain top memory crystal grain, decision circuitry 40 produces the judgement signal S40 of " 11 " according to the strong high levle state of selecting input pad OP.
Fig. 7 c represents just be operating as two when stacking in the memory crystal grain below memory crystal grain (three-mode), the waveform of the voltage of voltage source V CC (VS2), control signal CS, detection signal S60, and the logic value of judging signal S40 when memory chip 4.In three-mode, select input pad OP to be connected to low-voltage source VSS.According to above-mentioned, control signal CS is enabled between time point T1 to T2, and sampling unit 51 is taken a sample to obtain first logic value and second logic value respectively to detection signal S60 on time point T3 and T4 respectively.Shown in Fig. 7 c, under three-mode, first logic value is that " 0 " judges signal S40 with second logic value for " 0 " forms.According to the narration of Fig. 7 c, when memory chip 4 is operating as two when stacking in the memory crystal grain below memory crystal grain, decision circuitry 40 produces the judgement signal S40 of " 00 " according to the strong low level state of selecting input pad OP.
In the embodiment of Fig. 6, when memory chip 4 is operating as single memory crystal grain (first pattern), select input pad OP to float, and connection select the node N60 of input pad OP to be drawn by on weak.In certain embodiments, when memory chip 4 is operating as single memory crystal grain (first pattern), select input pad OP to float, and connection select the node N60 of input pad OP by weak drop-down.
Therefore, voltage source V S1 provides high levle voltage, and for example operating voltage VCC, and voltage source V S2 provide low level voltage, ground voltage GND for example, as shown in Figure 8.In the case, draw on weak/drop down element 60 is to realize with nmos pass transistor, it is in conducting state according to the control of high voltage source VDD always, and in addition, this nmos pass transistor has long passage length.Switching device 61 is to realize with the PMOS transistor, and it is switched on according to the control signal CS that is enabled and have a low level.According to the sequential of control signal CS and the sampling operation of sampling unit 51 among Fig. 9 a, Fig. 9 b to Fig. 9 c, the sampling unit 51 of decision circuitry 40 can produce according to the state of selecting input pad OP judges signal S40, is operating in which pattern with instruction memory chip 4.Especially, judge that signal S40 can clearly indicate memory chip 4 and just stack below memory crystal grain (three-mode) in the memory crystal grain for single memory crystal grain (first pattern) or two.Note, first and three-mode in, connect to select the node N90 of input pad OP all to be pulled down to low level at last.
Another enforcement of detecting unit 50 is sharp in Figure 10 presentation graphs 5.Consult Figure 10, detecting unit 50 " couple and select input pad OP in node N90.Detecting unit 50 " comprise switching device 90 and 91 and weak on draw/drop down element 92.Switching device 90 is coupled between node N90 and the voltage source V S1, and it comes conducting by the control signal CS that is enabled.Switching device 91 is coupled between node N90 and the node N91.Draw on weak/drop down element 92 is coupled between voltage source V S2 and the node N91.Suppose when memory chip 4 is operating as single memory crystal grain, when promptly memory chip 4 operates in first pattern, select input pad OP to float, and be pulled to a high levle a little less than being connected in the node N90 quilt of selecting input end OP.Therefore voltage source V S1 provides low level voltage, ground voltage GND for example, and voltage source V S2 provides high levle voltage, for example operating voltage VCC.Suppose in the case, draw on weak/drop down element 92 is to realize with the PMOS transistor that it is in conducting state according to the control of low-voltage source VSS always, in addition, this PMOS transistor has long passage length.Switching device 90 is to realize with nmos pass transistor, and it is switched on according to the control signal CS that is enabled and have a high levle.In this embodiment, produce a detection signal S90 at node N90, and produce another detection signal S91 at node N91.Detection signal S90 and S91 are taken a sample by sampling unit 51.
Figure 11 a represents when memory chip 4 just is being operating as single memory crystal grain (first pattern), the waveform of the voltage of voltage source V CC (VS2), control signal CS, detection signal S90 and S91, the on off state of switching device 91 and the logic value of judging signal S40.As mentioned above, when memory chip 4 is operating as single memory crystal grain, select input pad OP to float.Consult Figure 11 a, switching device 91 is conducting state (ON) during before the time point T1.Detection signal S90 and S91 little by little draw on the high levle voltage by voltage source V S2, and arrive the accurate position of high levle voltage VCC before time point T1.When time point T1, switching device 91 is closed (OFF).Detection signal S90 is in the accurate position of high levle voltage VCC constantly, switches to high levle (be control signal CS in time point T2 be enabled) in time point T2 by low level up to control signal CS and comes conducting switching device 90.At time point T2, because control signal CS is enabled, detection signal S90 is pulled down to the accurate position of the low level voltage GND of voltage source V S1 at once.At time point T3, control signal CS switches to low level (being that control signal CS is enabled by counter in time point T3) by high levle and closes switching device 90.At this moment, because switching device 91 still is in closed condition, detection signal S90 can not drawn on the high levle voltage VCC, and is in the accurate position of the low level voltage GND of voltage source V S1 constantly.Sampling unit 51 is taken a sample to obtain first logic value " 0 " to detection signal S90 in time point T3 (after control signal CS is enabled).At time point T4, switching device 91 conductings.Because the conducting of switching device 91, the accurate position of detection signal S90 is little by little drawn on the high levle voltage VCC.In addition, shown in Figure 11 a, during time point T1 to T4, because switching device 91 is closed, detection signal S91 can not be subjected to the influence of low level voltage GND, and detection signal S91 is in the accurate position of high levle voltage VCC constantly.Sampling unit 51 is taken a sample to obtain second logic value " 1 " to detection signal S91 at time point T4.First logic value " 0 " forms with second logic value " 1 " judges signal S40.
According to the narration of Figure 11 a, when memory chip 4 was operating as single memory crystal grain, decision circuitry 40 produced the judgement signal S40 of " 01 " according to the floating state of selecting input pad OP.
Figure 11 b represents just be operating as two when stacking in the memory crystal grain top memory crystal grain (second pattern), the logic value of the waveform of the voltage of voltage source V CC (VS2), control signal CS, detection signal S90 and S91, the on off state of switching device 91 and judgement signal S40 when memory chip 4.In second pattern, select input pad OP to be connected to high voltage source VDD.According to above-mentioned, control signal CS is enabled between time point T2 to T3, the state switching of switching device 91 occurs in time point T1 and T4, and sampling unit 51 is taken a sample to obtain first logic value and second logic value respectively to detection signal S90 and S91 respectively on time point T3 and T4.Shown in Figure 11 b, under second pattern, first logic value is that " 1 " judges signal S40 with second logic value for " 1 " forms.According to the narration of Figure 11 b, when memory chip 4 is operating as two when stacking in the memory crystal grain top memory crystal grain, decision circuitry 40 produces the judgement signal S40 of " 11 " according to the strong high levle state of selecting input pad OP.
Figure 11 c represents just be operating as two when stacking in the memory crystal grain below memory crystal grain (three-mode), the logic value of the waveform of the voltage of voltage source V CC (VS2), control signal CS, detection signal S90 and S91, the on off state of switching device 91 and judgement signal S40 when memory chip 4.In three-mode, select input pad OP to be connected to low-voltage source VSS.According to above-mentioned, control signal CS is enabled between time point T2 to T3, the state switching of switching device 91 occurs in time point T1 and T4, and sampling unit 51 is taken a sample to obtain first logic value and second logic value respectively to detection signal S90 and S91 respectively on time point T3 and T4.Shown in Figure 11 c, under three-mode, first logic value is that " 0 " judges signal S40 with second logic value for " 1 " forms.According to the narration of Figure 11 c, when memory chip 4 is operating as two when stacking in the memory crystal grain below memory crystal grain, decision circuitry 40 produces the judgement signal S40 of " 00 " according to the strong low level state of selecting input pad OP.
According to above-mentioned enforcement profit, the sampling unit 51 of decision circuitry 40 produces according to the state of selecting input pad OP judges signal S40, is operating under which pattern with instruction memory chip 4.Especially, judge that signal S40 can clearly indicate memory chip 4 and stack below memory crystal grain (second pattern) in the memory crystal grain as single memory crystal grain (first pattern) or two.Note, in first and second pattern, connect and select the node N90 of input pad OP all to be pulled to high levle at last.
In the embodiment of Figure 10, when memory chip 4 is operating as single memory crystal grain (first pattern), select input pad OP to float, and connection select the node N90 of input pad OP to be drawn by on weak.In certain embodiments, when memory chip 4 is operating as single memory crystal grain (first pattern), select input pad OP to float, and connection select the node N90 of input pad OP by weak drop-down.
Therefore, voltage source V S1 provides high levle voltage, and for example operating voltage VCC, and voltage source V S2 provide low level voltage, ground voltage GND for example, as shown in figure 12.In the case, draw on weak/drop down element 92 is to realize with nmos pass transistor, it is in conducting state according to the control of high voltage source VDD always, and in addition, this nmos pass transistor has long passage length.Switching device 90 is to realize with the PMOS transistor, and it is switched on according to the control signal CS that is enabled and have a low level.According to the sequential of control signal CS among Figure 13 a, Figure 13 b to Figure 13 c, the blocked operation of switching device 91 and the sampling operation of sampling unit 51, the sampling unit 51 of decision circuitry 40 can produce according to the state of selecting input pad OP judges signal S40, is operating in which pattern with instruction memory chip 4.Especially, judge that signal S40 can clearly indicate memory chip 4 and stack below memory crystal grain (three-mode) in the memory crystal grain as single memory crystal grain (first pattern) or two.Note, first and three-mode in, connect to select the node N90 of input pad OP all to be pulled down to low level at last.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claim institute confining spectrum.
Claims (12)
1. a memory chip is characterized in that, described memory chip operates in a plurality of patterns,, described memory chip comprises:
One selects input pad, has a plurality of states; And
One decision circuitry couples described selection input pad, produces one in order to the current state according to described selection input pad and judges signal, and wherein, described judgement signal indicates described memory chip and just operating under which pattern, and described decision circuitry comprises:
One detecting unit couples one first voltage source and described selection input pad, and is controlled by a control signal and produces at least one detection signal with the current state according to described selection input pad; And
One sampling unit in order to receiving described at least one detection signal, and is taken a sample to produce described judgement signal to described at least one detection signal after described control signal is enabled;
Wherein, when described control signal was enabled, the voltage that the accurate position of described at least one detection signal is provided by described first voltage source changed.
2. memory chip as claimed in claim 1 is characterized in that described memory chip more comprises a control circuit, in order to receive described judgement signal and to control described memory chip according to described judgement signal.
3. memory chip as claimed in claim 1 is characterized in that, described detecting unit couples described selection input pad in a first node and comprise:
Draw/drop down element on a little less than in the of one, be coupled between one second voltage source and the described first node; And
One switches element, be coupled between described first node and described first voltage source, and by the described control signal institute conducting that is enabled;
Wherein, one first detection signal results from described first node with as described at least one detection signal.
4. memory chip as claimed in claim 3, it is characterized in that, describedly draw on weak/drop down element realizes with a PMOS transistor that is in conducting state always, the voltage that described first voltage source is provided has a low level, and the voltage that described second voltage source is provided has a high levle.
5. memory chip as claimed in claim 3, it is characterized in that, describedly draw on weak/drop down element realizes with a nmos pass transistor that is in conducting state always, the voltage that described first voltage source is provided has a high levle, and the voltage that described second voltage source is provided has a low level.
6. memory chip as claimed in claim 3 is characterized in that, after described control signal was enabled, described sampling unit was taken a sample twice of described first detection signal to produce two logic value, and described logic value forms described judgement signal.
7. memory chip as claimed in claim 1 is characterized in that, described judging unit couples described selection input pad in a first node and comprise:
One first switching device is coupled between described first node and described first voltage source, and by the described control signal institute conducting that is enabled;
One second switching device is coupled between a described first node and the Section Point, and wherein, described second switching device is switched on and is closed in a second phase between a first phase; And
Draw/drop down element on a little less than in the of one, be coupled between one second voltage source and the described Section Point;
Wherein, one first detection signal results from described first node, and one second detection signal results from described Section Point.
8. memory chip as claimed in claim 7, it is characterized in that, describedly draw on weak/drop down element realizes with a PMOS transistor that is in conducting state always, the voltage that described first voltage source is provided has a low level, and the voltage that described second voltage source is provided has a high levle.
9. memory chip as claimed in claim 7, it is characterized in that, describedly draw on weak/drop down element realizes with a nmos pass transistor that is in conducting state always, the voltage that described first voltage source is provided has a high levle, and the voltage that described second voltage source is provided has a low level.
10. memory chip as claimed in claim 7, it is characterized in that, described control signal was enabled in the described second phase, and after described control signal is enabled, described sampling unit is taken a sample obtaining one first logic value and described second detection signal is taken a sample to obtain one second logic value to described first detection signal, and described first logic value and described second logic value form described judgement signal.
11. memory chip as claimed in claim 1 is characterized in that, described selection input pad has a floating state, a strong high levle state and a strong low level shape respectively and visits under three patterns.
12. memory chip as claimed in claim 11, it is characterized in that, under described three states, described memory chip is operating as a single memory crystal grain, two and stacks that a top memory crystal grain and two stacks a below memory crystal grain in the memory crystal grain in the memory crystal grain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010000204.7A CN102117655B (en) | 2010-01-04 | 2010-01-04 | Memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010000204.7A CN102117655B (en) | 2010-01-04 | 2010-01-04 | Memory chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102117655A true CN102117655A (en) | 2011-07-06 |
| CN102117655B CN102117655B (en) | 2014-04-09 |
Family
ID=44216375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010000204.7A Active CN102117655B (en) | 2010-01-04 | 2010-01-04 | Memory chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102117655B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001218A1 (en) * | 2000-06-30 | 2002-01-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device enabling selective production of different semiconductor memory devices operating at different external power-supply voltages |
| CN1505046A (en) * | 2002-12-02 | 2004-06-16 | 三星电子株式会社 | Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level |
| CN101197569A (en) * | 2006-12-07 | 2008-06-11 | 立锜科技股份有限公司 | Circuit built in chip for initializing its operation mode and method thereof |
-
2010
- 2010-01-04 CN CN201010000204.7A patent/CN102117655B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001218A1 (en) * | 2000-06-30 | 2002-01-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device enabling selective production of different semiconductor memory devices operating at different external power-supply voltages |
| CN1505046A (en) * | 2002-12-02 | 2004-06-16 | 三星电子株式会社 | Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level |
| CN101197569A (en) * | 2006-12-07 | 2008-06-11 | 立锜科技股份有限公司 | Circuit built in chip for initializing its operation mode and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102117655B (en) | 2014-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9971505B2 (en) | Memory systems including an input/output buffer circuit | |
| US7257047B2 (en) | Page buffer circuit of flash memory device with improved read operation function and method of controlling read operation thereof | |
| US8611124B2 (en) | Semiconductor memory device including plurality of memory chips | |
| US8675421B2 (en) | Semiconductor memory device | |
| US7298180B2 (en) | Latch type sense amplifier | |
| CN109671464A (en) | Memory module operates its method and the test macro of memory module | |
| KR101605747B1 (en) | Semiconductor memory device having physically shared data path and test device for the same | |
| WO2009079752A1 (en) | Dual function compatible non-volatile memory device | |
| CN105989878A (en) | Memory cell and content addressable memory with the same | |
| CN102169874B (en) | Semiconductor integrated circuit | |
| US9208834B2 (en) | Latch circuit, nonvolatile memory device and integrated circuit | |
| US9997256B2 (en) | Semiconductor memory devices and methods of testing open failures thereof | |
| CN105489237A (en) | Strobe signal interval detection circuit and memory system including the same | |
| CN101529520A (en) | Memory bus output driver of a multi-bank memory device and method therefor | |
| TWI523013B (en) | Tile-level snapback detection through coupling capacitor in a cross point array | |
| US9140743B2 (en) | Semiconductor system that tests the connectivity between a metal and a bump that are formed in the upper portion of a penetrating electrode | |
| CN102117655B (en) | Memory chip | |
| US20140347909A1 (en) | Semiconductor device and semiconductor memory device | |
| TWI426519B (en) | Memory chips and judgment circuits thereof | |
| US8649237B2 (en) | Power-up signal generation circuit | |
| US8588020B2 (en) | Sense amplifier and method for determining values of voltages on bit-line pair | |
| KR101102865B1 (en) | Memory chips and judgment circuits thereof | |
| EP2341504B1 (en) | Memory chips and judgment circuits thereof | |
| US20110026561A1 (en) | Temperature information outputting circuit and a semiconductor memory apparatus using the same | |
| US20110157950A1 (en) | Memory chips and judgement circuits thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |