CN102117480A - Function-level evolvable hardware-based image spatial filtering system and method - Google Patents

Function-level evolvable hardware-based image spatial filtering system and method Download PDF

Info

Publication number
CN102117480A
CN102117480A CN 201110054608 CN201110054608A CN102117480A CN 102117480 A CN102117480 A CN 102117480A CN 201110054608 CN201110054608 CN 201110054608 CN 201110054608 A CN201110054608 A CN 201110054608A CN 102117480 A CN102117480 A CN 102117480A
Authority
CN
China
Prior art keywords
circuit
image
reconfigurable
filtering
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN 201110054608
Other languages
Chinese (zh)
Inventor
李元香
刘罡
王峰
聂鑫
雷新
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan University WHU
Original Assignee
Wuhan University WHU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan University WHU filed Critical Wuhan University WHU
Priority to CN 201110054608 priority Critical patent/CN102117480A/en
Publication of CN102117480A publication Critical patent/CN102117480A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Image Processing (AREA)

Abstract

The invention relates to the technical field of image spatial filtering, in particular to a function-level evolvable hardware-based image spatial filtering system and a function-level evolvable hardware-based image spatial filtering method. The system comprises a reconfigurable module circuit, an evolution strategy algorithm module and a central control module, wherein the reconfigurable module circuit is used for configuring an image spatial filtering circuit; the evolution strategy algorithm module is used for performing evolvable solution and producing the configuration of the reconfigurable module circuit; and the central control module is used for coordinating software and hardware to filter an image. The system and the method are highly efficient and highly applicable; and in the system and the method, an applicable circuit can be obtained directly without additional downloading, and the circuit structure is adaptively changed by the configuration, so adaptive configuration is realized.

Description

Image space territory filtering system and method based on function level evolution hardware
Technical field
The present invention relates to image space territory technical field of filtering, relate in particular to a kind of image space territory filtering system and method based on function level evolution hardware.
Background technology
(Evolvable Hardware is a kind of mutual by with environment EHW) to evolution hardware, can change the hardware circuit of himself structure and behavior dynamically.It has the ability of self-organization, self-adaptation, selfreparing, can adapt to the varying environment requirement and improve self performance.Evolution hardware is divided into 2 big classes according to the difference of assessment mode, and a class is that off-line develops, and a class is an online evolution.The general process that off-line develops is: adopt earlier to operate in the configuration string that the evolution algorithmic on the PC develops and hardware circuit, find out satisfactory configuration string then and then go here and there configuring hardware circuit with this configuration.The general process of online evolution is: evolution algorithmic is assessment configuration string on hardware circuit directly, and the signal that returns according to hardware circuit develops and satisfactory configuration string, and then with this configuration string configuring hardware circuit.Whole process does not need exterior PC to participate in, and is finished by evolution hardware fully.The application of online evolution is wider, and speed is faster, does not need exterior PC, and applicability is better.The main application fields of evolution hardware has: the automatic design of ball bearing made using, solve the problem of difficult definition, and create adaptive system, create the design innovation of tolerant system and indigestibility design field.Aspect Flame Image Process, the main application has application such as Design of Digital Filter and Image Edge-Detection, P. Nirmal Kumar has designed virtual reconfigurable circuit (evolution hardware) on FPGA, is applied to image filtering and has obtained good effect (referring to document 1).
The filtering of image space territory is directly the pixel of image to be carried out Filtering Processing, recovers original image from the image that contains noise.Image filtering is widely used, and various imaging systems all need filtering technique that picture is carried out Filtering Processing, and then carries out other processing.Be exactly the mean filter method widely wherein in the spatial domain filtering application, the statistical filtering method, the sharpening filtering method can't adapt to different noises but these method structures are fixing, can not be adaptive to picture shape, can make image blurring after wherein preceding 2 kinds of method filtering.In order to improve filter effect, Tomasi C has proposed famous double-side band filter method, and this method is adaptive to the equal value coefficient weight of local shape adjustment (referring to document 2) of image.Buades A has proposed non local average filter method, and this method adopts image overall information to carry out filtering, filter effect be greatly improved (referring to document 3).But all these methods must be introduced extra weight coefficient, and filter structure can't adaptively changing.Utilize function level evolution hardware to carry out spatial domain filtering and effectively raise filtering operation speed, filter structure is more flexible, can expand its application simultaneously.
Document 1:P. Nirmal Kumar, S. Suresh, J. Raja Paul Perinbam:Digital Image Filter Design using Evolvable Hardware. In Proceedings of the Fourth Annual ACIS International Conference on Computer and Information Scien
Document 2:Tomasi C, Manduchi R:Bilateral filtering for gray and color images. In:Proceedins of the Sixth Interatinal Conference on Computer Vision, 1998:839-846.
Document 3:Buades A, Coll B, Morel J M.A review of image denoising algorithms, with a new one. Multiscale Modeling ﹠amp; Simulation, 2005,4 (2): 490-530.
Summary of the invention
Technical matters at above-mentioned existence, the purpose of this invention is to provide a kind of image space territory filtering system and method, to solve the fixing problem of traditional images spatial domain filter construction and can't dynamically adjust filter construction to adapt to the problem of different noise types based on function level evolution hardware.
For achieving the above object, the present invention adopts following technical scheme:
A kind of image space territory filtering system based on function level evolution hardware comprises:
The reconfigurable module circuit is used for configuration image spatial domain filtering circuit, and described reconfigurable module circuit is made of the capable n row of m basic modular unit, and each basic modular unit is carried out function level arithmetic operation;
The evolutionary strategy algoritic module, the configuration string that is used to develop and finds the solution and produce the reconfigurable module circuit, and will dispose the string be configured on the reconfigurable module circuit; Described configuration string comprises the basic modular unit that the input of the interconnected information of each basic modular unit in the reconfigurable module circuit, selection that each basic modular unit is carried out function performance, view data is selected;
Central control module is used for collaboration software and hardware and realizes image is carried out filtering, and described central control module is by read-write register and reconfigurable module circuit communication;
Wherein, described reconfigurable modular circuit input data owner will comprise view data input and the input of configuration string, and output data is the image of filtering; Reconfigurable modular circuit produces the filtering circuit of different structure according to different configuration strings, the filtering circuit of different structure carries out filtering to image, the filtering result returns to the evolutionary strategy algoritic module, and the evolutionary strategy algoritic module is finished the assessment of configuration string according to return results.
Basic modular unit in the described reconfigurable module circuit has output of two inputs, each input is selected one from the output of the basic modular unit of previous column, wherein last row have only a basic modular unit, are executed in parallel in row, are that serial is carried out between row;
Wherein, the first row basic modular unit is as data input module, and last row have only the data outputting module of a basic modular unit as reconfigurable modular circuit;
The function of described basic modular unit is by the function decision of basic modular unit, and type function is by the decision of configuration string.
According to the configuration string, the reconfigurable module circuit produces the image space area filter circuit; The view data that contains noise is input in the reconfigurable module circuit, and the reconfigurable module circuit is output as the view data behind the removal noise.
The input register of described reconfigurable modular circuit comprises reset signal position, start bit, view data input position and configuration displacement; Output register comprises filtering data item position and finishes signal bits.
A kind of filtering method of the image space territory filtering system based on function level evolution hardware comprises:
3 * 3 matrix template is set, and this template covers on the image, and the image slices vegetarian refreshments that template covers is as the input data of reconfigurable modular circuit;
Template is each mobile pixel on image, the image slices vegetarian refreshments that covers with the matrix template is imported as pending data item at every turn, and the input data calculate the new value of matrix central pixel point and replace original center point value through the filtering circuit of configuration string configuration;
Template continues other view data are input in the filtering circuit, the data that filtering image has been passed through in filtering circuit output.
Is variable according to the configuration string at the filter circuit construction that reconfigurable modular circuit produces, and different configuration strings produces different filter circuit constructions; When the configuration falsification became, the filter circuit construction that produces in reconfigurable modular circuit can be replaced by new filter circuit construction.
The download and the assessment of configuration string are directly finished on reconfigurable modular circuit, and the evolutionary strategy algorithm receives the adaptive value of reconfigurable modular circuit calculating and develops according to adaptive value, and evaluation process does not rely on exterior PC.
A kind of method based on single configuration string configuring hardware circuit in the image space territory filtering system of function level evolution hardware:
Central control module calls the configuration string that the evolutionary strategy algoritic module develops and finds the solution reconfigurable modular circuit, the configuration string that each evolution is obtained is configured in the reconfigurable modular circuit, the reconfigurable modular circuit of this configuration string configuration, determine the interconnect architecture and the function performance of each modular unit, determine to accept the module of input image pixels point data simultaneously by the configuration string;
Central control module read treat filtering contain the noise image file, then image file is provided with 3 * 3 filtering matrix template, when initial, this template edge and image border overlap, the pixel of the 2nd row the 2nd row overlaps in matrix center and the image, and the image pixel data that template covers is the original input data of the reconfigurable modular circuit of input;
Central control module writes the view data register of reconfigurable modular circuit with the current data of filtering for the treatment of, the commencing signal register in reconfigurable modular circuit writes ' 1 ' then;
Circulation mobile filter template, each template center laterally moves a pixel along image, and the pixel after this template is moved is input in the reconfigurable modular circuit as new input data; When template center moves to the horizontal inverse of image the 2nd row pixel, finish Filtering Processing after, template center moves down 1 pixel and turns back to the pixel of horizontal the 3rd row the 2nd row of image, circulation successively is up to complete image of template scanning;
After handling the view picture image, preserve the output image result, and preserve the configuration string.The sign register of finishing in reconfigurable modular circuit writes ' 1 '.
The present invention has the following advantages and good effect:
1) efficient height of the present invention, applicability is good, and the circuit that can directly obtain being suitable for need not other download;
2) the present invention has realized adaptive configuration by the adaptive change circuit structure of configuration string.
Description of drawings
Fig. 1 is the system global structure figure of embodiment provided by the invention.
Fig. 2 is a reconfigurable modular circuit structural drawing in the embodiment of the invention.
Fig. 3 is the structural drawing of reconfigurable modular circuit IP kernel in the embodiment of the invention.
Fig. 4 is a primary control program control flow chart in the embodiment of the invention.
Fig. 5 is a filtering process flow diagram in the embodiment of the invention.
Fig. 6 uses reconfigurable modular circuit IP kernel filtering figure in the embodiment of the invention.
Embodiment
A kind of image space territory filtering system provided by the invention based on function level evolution hardware, this system is an adaptive system, wherein comprise with the lower part on the platform that FPGA makes up: reconfigurable modular circuit operates in PowerPC and goes up evolutionary strategy algoritic module and the central control module of realizing.
Reconfigurable modular circuit is used for configuration image spatial domain filtering circuit, carries out image spatial domain filtering circuit function, and wherein, each basic modular unit in the reconfigurable module circuit is carried out function level arithmetic operation; Operate in PowerPC and go up evolutionary strategy algoritic module and the central control module of realizing, the configuration string is assessed by the reconfigurable module circuit.Total system does not rely on exterior PC, adopts the online evaluation method that the configuration string is assessed, and realizes adaptive control.This reconfigurable modular circuit is made of 8 row, 7 row basic modular unit.The input of each row basic modular unit comes from the output of its previous column basic modular unit.But the input of the 1st row basic modular unit is the original input signal of system.The function that interconnected and definite each basic modular unit of each basic modular unit is carried out has realized image space territory filtering system.Reconfigurable modular circuit input data owner will comprise view data input and the input of configuration string, and output data is the image of filtering.
Go up the evolutionary strategy algoritic module generation configuration string of realizing by operating in PowerPC, will dispose string and be configured on the reconfigurable module circuit.The configuration string comprises the interconnected information of each basic modular unit in the reconfigurable module circuit, and each basic modular unit is carried out the selection of function performance, the basic modular unit that the input of view data is selected.According to the configuration string, the reconfigurable module circuit produces the image space area filter circuit; The view data that contains noise is input in the reconfigurable module circuit, and the reconfigurable module circuit is output as the view data behind the removal noise.The combination of evolutionary strategy algorithm and reconfigurable module circuit makes system have adaptivity.
Be to constitute in the reconfigurable modular circuit by the capable n row of m basic modular unit, each basic modular unit has output of two inputs, each input is selected one from the output of the basic modular unit of previous column, wherein last row have only a basic modular unit.In row is executed in parallel, is that serial is carried out between row.Wherein, the first row basic modular unit is as data input module, and last row have only the data outputting module of a basic modular unit as reconfigurable modular circuit.The function of each basic modular unit is by the function decision of predefined basic modular unit.
Each basic modular unit function is all pre-defined identical collection of functions, execution function level arithmetic operation, i.e. coarseness computing.The function that each basic modular unit is carried out at work is by selecting pre-defined function decision in basic modular unit.
The input of reconfigurable modular circuit comprises the configuration string that noise image data and evolutionary strategy algoritic module are provided that contains that reads from Compact Flash, be output as the view data of removing noise, and this view data leaves in the Compact Flash.Reconfigurable modular circuit is the hardware components in the adaptive system.
The evolutionary strategy algoritic module produces the configuration string, and reconfigurable modular circuit is according to the filtering circuit of different configuration string generation different structures, and the filtering circuit of different structure carries out filtering to image, and the filtering result returns to the evolutionary strategy algoritic module.The evolutionary strategy algoritic module is finished the assessment of configuration string according to return results.
The configuration string that the evolutionary strategy algoritic module is used to develop and finds the solution the reconfigurable module circuit, central control module are used for collaboration software and hardware is realized image is carried out filtering.The configuration string comprises the interconnect architecture of basic modular unit in the reconfigurable module circuit, and the module of view data input is selected and accepted to each basic modular unit power function.
The configuration string directly sends to reconfigurable modular circuit by the evolutionary strategy algoritic module, reconfigurable modular circuit is according to the concrete filtering circuit of configuration string configuration, input image data carried out filtering after configuration was finished, calculate the adaptive value of configuration string and return to the evolutionary strategy algoritic module, the evolutionary strategy algoritic module is according to the new configuration string of adaptive value evolution.
The invention will be further described in conjunction with the accompanying drawings with specific embodiment below:
This example is to realize on XC2VP30 FPGA development board, uses PowerPC as processor, adopts the CF card as the nonvolatile memory stores view data.The image and the filtered view data that contain noise all leave in the CF card.Because internal memory BRAM is limited on the sheet of FPGA platform, increase the memory bar DDR SDRAM of a 512MB, can be used for depositing the storehouse of software project and read in view data.
Shown in Fig. 1 is the overall construction drawing of system, has comprised the PowerPC as processor, reconfigurable module circuit, exterior storage CF card, Memory Controller Hub.Evolutionary strategy algoritic module and the central control module on PowerPC, realized.
For the ease of implementing reference, provide the each several part specific design of embodiment as follows:
Fig. 2 shows the structure of the circuit that a kind of reconfigurable modular circuit IP kernel provided.This circuit is made of 8 row, 7 row basic modular unit, and basic modular unit is labeled as PE among the figure JinBasic modular unit has output of two inputs, and each imports in the output (totally 8) of optional previous column basic modular unit one, the concrete selection by configuration string (Configuration) decision.Wherein last row have only a basic modular unit.If the input selective value is n in the configuration string of the some inputs of basic modular unit, the value of just representing this input of basic modular unit is the output of the capable basic modular unit of previous column n.The function of basic modular unit is by the function decision of basic modular unit, and type function is by the decision of configuration string.Every input is no more than two, output equal one type function all can, but in order to simplify calculating, increase travelling speed, can select some better simply type function.The corresponding relation (A, B are respectively two inputs) as shown in the table of function numerical value and function type in the configuration string in the present embodiment:
Functional value Type function Explanation Functional value Type function Explanation
0 A Straight-through 8 A<<1 A moves to left 1
1 (A+B)>>1 A+B moves to right 1 9 A⊕B XOR gate
2 (A+B+1)>>1 A+B+1 moves to right 1 10 B Straight-through
3 Max(A,B) A, maximal value among the B 11 A·(~=C)+B·C Two the tunnel select
4 Min(A,B) A, minimum value among the B 12 A & B With door
5 A | B Or door 13 ~A Not gate
6 B<<1 B moves to left 1 14 A+B Summation
7 A &0x0F Get low 4 of A 15 A &0xF0 It is high 4 to get A
Central control module is communicated by letter with reconfigurable modular circuit by read-write register.The input register of reconfigurable modular circuit comprises reset signal position, start bit, view data input position and configuration displacement; Output register comprises filtering data item position and finishes signal bits.
Supposing to contain noise image is A, and filtering template scale is 3 * 3, and then the data item of the view data input register of reconfigurable modular circuit is that 9 pixels of template are 72, and the filtering data item of output register is that 1 pixel is 8.
The method that is produced reconfigurable filtering circuit by the configuration string is:
1. with the reconfigurable module circuit in this configuration string configuration reconfigurable module circuit.In the specific embodiment: central control module at first writes ' 1 ' in the reset signal position of the input register of reconfigurable module circuit, writes ' 0 ' then, finishes the reset operation of this IP kernel.Configuration displacement at the input register of reconfigurable module circuit writes the configuration string that the evolutionary strategy algorithm provides then.
2. the noise image data that contain that cover with 3 * 3 templates are successively imported data item, calculation of filtered data item as the image of reconfigurable module circuit input register.In the specific embodiment: central control module at first writes ' 1 ' in the start bit of the input register of reconfigurable module circuit I P nuclear, finish signal bits in this IP kernel output register of cycle detection then, in case detecting and finishing signal bits is ' 1 ', expression is calculated and is finished, and central control module reads the data of filtering data item in the output register.
3. after the filtering data item of whole 256 * 256 image pixel data items calculated and finishes, central control module left filtered image in the Compact Flash in.
After the reconfigurable module electric circuit inspection be ' 1 ' to the start bit of its input register, calculate the 1st row successively under the control of this IP kernel internal clock signal (being the system clock of FPGA), the 2nd row are to the output of the 8th each basic modular unit that is listed as.When calculating a certain row, 8 elementary cells of these row are to carry out computing simultaneously.Can set the computing time of every row in concrete the enforcement according to the time delay situation of FPGA, be set at 1 clock period in the present embodiment, calculate the value of next column after a column count is finished.After last column count finishes, with last row (the 7th row, the 7th row have only a basic modular unit) the output valve of basic modular unit be written to the filtering data item position of the output register of reconfigurable module circuit, and the signal bits of finishing of putting output register is ' 1 ';
Described evolution hardware chart image space area filter circuit based on the function level serves as basic with the spatial domain template filtered version in the existing filtering technique, but its filter circuit construction is variable, does not need extra weight coefficient.Among the embodiment, adopt hardware evolution mode to realize the image space area filter circuit, view data register, configuration string data register are set, commencing signal register, result register and finish sign register; What being input as of image space area filter circuit treated filtering contains the noise image data, is output as the result to image filtering.Fig. 3 shows the structural drawing of reconfigurable module circuit.Being input as of this circuit disposed string configuration, contained noise image data indata and commencing signal start; Be output as after the filtering view data outdata and finish signal finish, configuration string register, view data register, commencing signal register, the result register in the corresponding respectively program and finish sign register; The function of finishing is that the image in the view data register is carried out spatial domain filtering, and the filtering result is placed in the result register.FPGA platform meeting clock signal clk and reset signal reset are so that provide work clock and support reset operation.
The image space area filter circuit is the filtering basic technology with spatial domain template filtering technique, draws the new filter circuit construction that is adapted to noise by evolution.
Fig. 4 illustrates the control flow chart of the central control module of embodiment.Central control module is carried out the evolutionary strategy algorithm, reads in view data to the view data register, begins to carry out filtering work.
Fig. 5 illustrates filtering.The embodiment of evolution reconfigurable module circuit is: the data that contain noise image that comprise with the configuration string and the filtering template of reconfigurable module circuit are as the individuality of evolutionary strategy algorithm, the evolutionary strategy algoritic module is selected the basic logic unit of view data input usefulness by the interconnect architecture and the function performance of basic logic unit in the evolutionary strategy algorithm evolution reconfigurable module circuit.The evolutionary strategy algorithm is a kind of intelligent algorithm that is in daily use, and the present invention will not give unnecessary details.Individuality in the evolutionary strategy algorithm is sent to the reconfigurable module circuit and is estimated its adaptive value.The configuration string that central control module provides according to the evolutionary strategy algoritic module produces corresponding filtering circuit in the reconfigurable module circuit, the reconfigurable module circuit returns this individual adaptive value and gives evolutionary strategy algoritic module (in the present embodiment with the mean pixel difference of filtered image and the original image adaptive value as evolutionary strategy algorithm individuality).When certain individual adaptive value hour, show that filtering image and original image are the most approaching, should individuality as optimum individual, the evolutionary strategy algoritic module reconfigurable module circuit that stops to develop.Central control module as configuration string configuration reconfigurable module circuit, produces filtering circuit with optimum individual.
When the reconfigurable module circuitry evaluates was individual, the noise image data that contain that cover with 3 * 3 templates were imported data item as the image of reconfigurable module circuit I P nuclear input register successively, use the data item of the filtering circuit calculation of filtered image that obtains according to evolution.After the filtering data item of whole 256 * 256 image pixel data items calculated and finishes, central control module left the filtering image image in the Compact Flash in.
Wherein, comprise following steps for single configuration string configuring hardware circuit:
Step 2.1, central control module are called the configuration string that the evolutionary strategy algoritic module develops and finds the solution reconfigurable modular circuit, and the configuration string that each evolution is obtained is configured in the reconfigurable modular circuit.This configuration string disposes reconfigurable modular circuit, determines the interconnect architecture and the function performance of each modular unit, is determined to accept the module of input image pixels point data simultaneously by the configuration string, promptly determines the data input module of reconfigurable modular circuit;
Step 2.2, central control module read treat filtering contain the noise image file, then image file is provided with 3 * 3 filtering matrix template.When initial, this template edge and image border overlap, and the pixel of the 2nd row the 2nd row overlaps in matrix center and the image, and the image pixel data that template covers is the original input data of the reconfigurable modular circuit of input;
Step 2.3, central control module writes the view data register of reconfigurable modular circuit with the current data of filtering for the treatment of, and the commencing signal register in reconfigurable modular circuit writes ' 1 ' then;
Step 2.4, circulation mobile filter template, each template center laterally moves a pixel along image, and the pixel after this template is moved is input in the reconfigurable modular circuit as new input data; When template center moves to the horizontal inverse of image the 2nd row pixel, finish Filtering Processing after, template center moves down 1 pixel and turns back to the pixel of horizontal the 3rd row the 2nd row of image.Circulation successively is up to complete image of template scanning.
Step 2.5 after handling the view picture image, is preserved the output image result, and preserves the configuration string.The sign register of finishing in reconfigurable modular circuit writes ' 1 ';
Fig. 6 shows and uses the course of work of reconfigurable module circuit to be: at first write the configuration string before to entire image filtering in the configuration string register of reconfigurable module circuit; In the view data register, write the current data segment for the treatment of filtering then; Putting the start bit at the beginning register again is ' 1 ', i.e. commencing signal start=1; Central control module constantly detects finishing of reconfigurable module circuit I P nuclear and finishes signal finish in the sign register afterwards, in case detect to finish and finish signal finish=1 in the sign register, show that then filtering finishes, the data in the reconfigurable module circuit result register are the result of image filtering.Circuit in the reconfigurable module circuit I P nuclear is exactly the optimal filtering circuit of coming out that develops.
Wherein, entire system operation evolutionary strategy algorithm is configured hardware circuit and comprises following steps:
Step 3.1, a plurality of configuration string series arrangement are in reconfigurable modular circuit; Control by the evolutionary strategy algoritic module, do not rely on exterior PC fully;
Step 3.2, the reconfigurable modular circuit of configuration string configuration is concrete hardware circuit, promptly begins input image data and carry out Filtering Processing after configuring circuit.This moment image data processing be the circuit that configures, the evolutionary strategy algoritic module is only waited for the signal that reconfigurable modular circuit is returned, and does not interfere the work of treatment of reconfigurable modular circuit, promptly is online evolution completely;
Step 3.3, behind an intact image of configuration string manipulation, next configuration string reconfigures reconfigurable modular circuit IP kernel, produces new configuration circuit.And handle image with new configuration circuit.And for each configuration string is preserved filtered image data.
Step 3.4 after all configuration strings are all handled image, compares the result, selects the best configuration string of filter effect.It is configured in the modular circuit IP kernel that can heavily purchase.
Step 3.5, after image filtering finished, the evolutionary strategy algoritic module was out of service, and the circuit that configures continues to use;
The present invention combines evolution hardware and the filtering of image space territory, with the FPGA Platform Implementation image is carried out spatial domain filtering, because evolution hardware is reconfigurable, different filtering circuits so it can develop, and has increased the reusability of hardware.Image space provided by the present invention territory filtering system develops with the evolutionary strategy algorithm and the filtering circuit of different structure, do not need to introduce extra weight coefficient, because adopt all filter circuit constructions of evolution hardware to have good fault-tolerance and adaptivity, be easy to expansion.
Above embodiment is only for the usefulness that the present invention is described, but not limitation of the present invention, person skilled in the relevant technique; under the situation that does not break away from the spirit and scope of the present invention; can also make various conversion or modification, so all technical schemes that are equal to, all fall into protection scope of the present invention.

Claims (8)

1. the image space territory filtering system based on function level evolution hardware is characterized in that, comprising:
The reconfigurable module circuit is used for configuration image spatial domain filtering circuit, and described reconfigurable module circuit is made of the capable n row of m basic modular unit, and each basic modular unit is carried out function level arithmetic operation;
The evolutionary strategy algoritic module, the configuration string that is used to develop and finds the solution and produce the reconfigurable module circuit, and will dispose the string be configured on the reconfigurable module circuit; Described configuration string comprises the basic modular unit that the input of the interconnected information of each basic modular unit in the reconfigurable module circuit, selection that each basic modular unit is carried out function performance, view data is selected;
Central control module is used for collaboration software and hardware and realizes image is carried out filtering, and described central control module is by read-write register and reconfigurable module circuit communication;
Wherein, described reconfigurable modular circuit input data owner will comprise view data input and the input of configuration string, and output data is the image of filtering; Reconfigurable modular circuit produces the filtering circuit of different structure according to different configuration strings, the filtering circuit of different structure carries out filtering to image, the filtering result returns to the evolutionary strategy algoritic module, and the evolutionary strategy algoritic module is finished the assessment of configuration string according to return results.
2. the image space territory filtering system based on function level evolution hardware according to claim 1 is characterized in that:
Basic modular unit in the described reconfigurable module circuit has output of two inputs, each input is selected one from the output of the basic modular unit of previous column, wherein last row have only a basic modular unit, are executed in parallel in row, are that serial is carried out between row;
Wherein, the first row basic modular unit is as data input module, and last row have only the data outputting module of a basic modular unit as reconfigurable modular circuit;
The function of described basic modular unit is by the function decision of basic modular unit, and type function is by the decision of configuration string.
3. the image space territory filtering system based on function level evolution hardware according to claim 1 and 2 is characterized in that:
According to the configuration string, the reconfigurable module circuit produces the image space area filter circuit; The view data that contains noise is input in the reconfigurable module circuit, and the reconfigurable module circuit is output as the view data behind the removal noise.
4. according to each described image space territory filtering system among the claim 1-3, it is characterized in that based on function level evolution hardware:
The input register of described reconfigurable modular circuit comprises reset signal position, start bit, view data input position and configuration displacement; Output register comprises filtering data item position and finishes signal bits.
5. the filtering method of the image space territory filtering system based on function level evolution hardware as claimed in claim 1 is characterized in that, according to the configuration string, produces the filtering circuit according to the configuration string descriptor in reconfigurable modular circuit, may further comprise the steps:
3 * 3 matrix template is set, and this template covers on the image, and the image slices vegetarian refreshments that template covers is as the input data of reconfigurable modular circuit;
Template is each mobile pixel on image, the image slices vegetarian refreshments that covers with the matrix template is imported as pending data item at every turn, and the input data calculate the new value of matrix central pixel point and replace original center point value through the filtering circuit of configuration string configuration;
Template continues other view data are input in the filtering circuit, the data that filtering image has been passed through in filtering circuit output.
6. filtering method according to claim 5 is characterized in that:
Is variable according to the configuration string at the filter circuit construction that reconfigurable modular circuit produces, and different configuration strings produces different filter circuit constructions; When the configuration falsification became, the filter circuit construction that produces in reconfigurable modular circuit can be replaced by new filter circuit construction.
7. according to claim 5 or 6 described filtering methods, it is characterized in that:
The download and the assessment of configuration string are directly finished on reconfigurable modular circuit, and the evolutionary strategy algorithm receives the adaptive value of reconfigurable modular circuit calculating and develops according to adaptive value, and evaluation process does not rely on exterior PC.
8. the method based on single configuration string configuring hardware circuit in the image space territory filtering system of function level evolution hardware as claimed in claim 1 is characterized in that, may further comprise the steps:
Central control module calls the configuration string that the evolutionary strategy algoritic module develops and finds the solution reconfigurable modular circuit, the configuration string that each evolution is obtained is configured in the reconfigurable modular circuit, the reconfigurable modular circuit of this configuration string configuration, determine the interconnect architecture and the function performance of each modular unit, determine to accept the module of input image pixels point data simultaneously by the configuration string;
Central control module read treat filtering contain the noise image file, then image file is provided with 3 * 3 filtering matrix template, when initial, this template edge and image border overlap, the pixel of the 2nd row the 2nd row overlaps in matrix center and the image, and the image pixel data that template covers is the original input data of the reconfigurable modular circuit of input;
Central control module writes the view data register of reconfigurable modular circuit with the current data of filtering for the treatment of, the commencing signal register in reconfigurable modular circuit writes ' 1 ' then;
Circulation mobile filter template, each template center laterally moves a pixel along image, and the pixel after this template is moved is input in the reconfigurable modular circuit as new input data; When template center moves to the horizontal inverse of image the 2nd row pixel, finish Filtering Processing after, template center moves down 1 pixel and turns back to the pixel of horizontal the 3rd row the 2nd row of image, circulation successively is up to complete image of template scanning;
After handling the view picture image, preserve the output image result, and preserve the configuration string, write ' 1 ' at the sign register of finishing of reconfigurable modular circuit.
CN 201110054608 2011-03-08 2011-03-08 Function-level evolvable hardware-based image spatial filtering system and method Pending CN102117480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201110054608 CN102117480A (en) 2011-03-08 2011-03-08 Function-level evolvable hardware-based image spatial filtering system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201110054608 CN102117480A (en) 2011-03-08 2011-03-08 Function-level evolvable hardware-based image spatial filtering system and method

Publications (1)

Publication Number Publication Date
CN102117480A true CN102117480A (en) 2011-07-06

Family

ID=44216233

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201110054608 Pending CN102117480A (en) 2011-03-08 2011-03-08 Function-level evolvable hardware-based image spatial filtering system and method

Country Status (1)

Country Link
CN (1) CN102117480A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102567585A (en) * 2011-12-31 2012-07-11 重庆邮电大学 Intrinsic evolvable hardware system and method based on multi-core virtual reconfigurable structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090313191A1 (en) * 2001-03-15 2009-12-17 Xin Yao Hardware design using evolution algorithms
CN101609443A (en) * 2009-07-31 2009-12-23 中国人民解放军总参谋部第六十一研究所 Evolvable hardware controller and control method thereof
CN101783924A (en) * 2010-01-27 2010-07-21 武汉大学 Image encrypting and decrypting system and method based on field programmable gate array (FPGA) platform and evolvable hardware

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090313191A1 (en) * 2001-03-15 2009-12-17 Xin Yao Hardware design using evolution algorithms
CN101609443A (en) * 2009-07-31 2009-12-23 中国人民解放军总参谋部第六十一研究所 Evolvable hardware controller and control method thereof
CN101783924A (en) * 2010-01-27 2010-07-21 武汉大学 Image encrypting and decrypting system and method based on field programmable gate array (FPGA) platform and evolvable hardware

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
《LNCS》 20031231 Lukáš Sekanina Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware 第187-195页 1-8 第2606卷, 2 *
《Proceedings of the Fourth Annual ACIS International Conference on Computer and Information Science》 20051231 P. Nirmal Kumar et al. Digital Image Filter Design using Evolvable Hardware 全文 1-8 , 2 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102567585A (en) * 2011-12-31 2012-07-11 重庆邮电大学 Intrinsic evolvable hardware system and method based on multi-core virtual reconfigurable structure

Similar Documents

Publication Publication Date Title
CN109784489B (en) Convolutional neural network IP core based on FPGA
EP3494521B1 (en) Binary neural networks on progammable integrated circuits
US11775836B2 (en) Hand pose estimation
Cong et al. Minimizing computation in convolutional neural networks
US7634137B2 (en) Unfolded convolution for fast feature extraction
JP6773568B2 (en) Arithmetic system and neural network arithmetic method
US20150310311A1 (en) Dynamically reconstructable multistage parallel single instruction multiple data array processing system
DE112020003128T5 (en) DILATED CONVOLUTION WITH SYSTOLIC ARRAY
CN102665049A (en) Programmable visual chip-based visual image processing system
Sledevic Adaptation of convolution and batch normalization layer for CNN implementation on FPGA
EP3388981B1 (en) Convolutional processing system
CN104112053A (en) Design method of reconfigurable architecture platform oriented image processing
US20200074285A1 (en) Artificial neural network and method of controlling fixed point in the same
Dobai et al. Low-level flexible architecture with hybrid reconfiguration for evolvable hardware
CN110738317A (en) FPGA-based deformable convolution network operation method, device and system
Sanny et al. Energy-efficient median filter on FPGA
Kim et al. A neural network accelerator for mobile application processors
Sommer et al. Efficient hardware acceleration of sparsely active convolutional spiking neural networks
Gong et al. Research and implementation of multi-object tracking based on vision DSP
Chinchanikar et al. Design of binary neural network soft system for pattern detection using HDL tool
Bhadouria et al. A novel image impulse noise removal algorithm optimized for hardware accelerators
CN102117480A (en) Function-level evolvable hardware-based image spatial filtering system and method
Natale et al. On how to design dataflow FPGA-based accelerators for convolutional neural networks
JPWO2018135516A1 (en) Neural network learning apparatus, neural network learning method, and neural network learning program
Pantho et al. Pixel-parallel architecture for neuromorphic smart image sensor with visual attention

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20110706