CN102117230B - Data writing method, flash memory controller and a flash memory memorizing device - Google Patents
Data writing method, flash memory controller and a flash memory memorizing device Download PDFInfo
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- CN102117230B CN102117230B CN 200910215388 CN200910215388A CN102117230B CN 102117230 B CN102117230 B CN 102117230B CN 200910215388 CN200910215388 CN 200910215388 CN 200910215388 A CN200910215388 A CN 200910215388A CN 102117230 B CN102117230 B CN 102117230B
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Abstract
The invention provides a data writing method, a flash memory controller and a flash memory memorizing device. The data writing method comprises the following steps of firstly receiving data by a mainframe system, subsequently segmenting the data into at least one code frame, subsequently generating an error correction code corresponding to the code frame so as to enable the code frame and the corresponding error correction code to form at least one error correction code frame, subsequently segmenting the error correcting code frame into a plurality of code frame segments, and finally writing the code frame segments in a flash memory chip in a non-sequential way.
Description
Technical field
The present invention relates to a kind of method for writing data for flash memory, and be particularly related to a kind of flash controller and flash memory that data are evenly write to the method for writing data in the flash memory and use the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that the consumer is to the also rapidly increase of storage requirements of digital content.Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and the characteristic of machinery-free structure etc., suitable user carries the Storage Media as digital document transmission and exchange.Solid state hard disc (Solid State Drive, SSD) is exactly with the example of flash memory as Storage Media, and has been widely used in the computer host system as Primary Hard Drive.
General flash memory comprises a plurality of physical blocks, and each physical blocks has comprised a plurality of pages, and the page is the minimum unit of data writing or reading out data.Each page generally includes user data field and redundant area.The user data field is in order to storing user's data, and redundant area is in order to the data (for example, error-correcting code (Error Checking and Correcting Code, ECC Code)) of stocking system.
And highdensity flash memory can be because of inhomogeneous processing procedure, so that different zones produces different fiduciary levels in the flash memory.Along with service time, the increase of read-write number of times of flash memory, the quantity of misdata also can be along with increase.When an error-correcting code is stored in low fiduciary level regional, the situation of nonrecoverable data will more early occur, can not be used again so that comprise the storer of the minimum management unit in this zone.And along with memory span is increasing, the storage space of minimum management unit is also increasing.Yet, a shared space of error-correcting code may only account for the per mille of minimum management unit storer, when one of them error-correcting code is irrecoverable, storage space of this minimum management unit area just can't re-use, and so will give up 999/1000ths spendable storage space also.
Summary of the invention
The invention provides a kind of method for writing data, flash controller and flash memory, it can on average be written in data in the flash chip, uses the up time that increases flash chip.
The present invention proposes a kind of flash memory, is used for storing the data that come from host computer system.Flash memory comprises connector, flash chip and flash controller.Wherein, connector is electrically connected to host computer system, with from main frame system receive data.Flash controller is electrically connected to flash memory and connector, it is used for Data Segmentation is at least one yard frame, and the generation error-correcting code corresponding with above-mentioned code frame, so that above-mentioned code frame error-correcting code corresponding with it formed the error-correcting code frame, again above-mentioned error-correcting code frame is divided into a plurality of yards frame fragments, afterwards these yards frame fragment is write in the flash chip after arranging with non-sequentially putting in order.
The present invention proposes a kind of flash controller, writes in the flash chip in order to the data that will come from host computer system.Wherein, flash controller comprises microprocessor unit, flash interface unit, host interface unit, error correction unit and Memory Management Unit.The flash interface unit is electrically connected to microprocessor unit, and is electrically connected to flash chip.Host interface unit is electrically connected to microprocessor unit, and is electrically connected to host computer system, is used for receiving the data from host computer system.Memory Management Unit is electrically connected to microprocessor unit, is used for data are write in the flash chip.Error correction unit is electrically connected to microprocessor unit, is used for data are produced error-correcting code.Wherein, Memory Management Unit is at least one yard frame with Data Segmentation, produces the error-correcting code corresponding with above-mentioned code frame by error correction unit again, and Memory Management Unit forms the error-correcting code frame with above-mentioned code frame error-correcting code corresponding with it.And Memory Management Unit is divided into a plurality of yards frame fragments with above-mentioned error-correcting code frame, and these yards frame fragment is write in the flash chip after arranging with non-sequentially putting in order.
The present invention proposes a kind of method for writing data, writes to flash chip for the data that will come from host computer system.At first, from main frame system receive data.Then, be at least one yard frame with Data Segmentation.Afterwards, produce the error-correcting code corresponding with above-mentioned code frame, so that above-mentioned code frame error-correcting code corresponding with it formed at least one error-correcting code frame.Then, above-mentioned error-correcting code frame is divided into a plurality of yards frame fragments.At last, these yards frame fragment is write in the flash chip with non-sequentially putting in order.
Based on above-mentioned, the present invention can be written in the code frame fragment of each error-correcting code frame in the different zones equably, to avoid that the code frame fragment of same error-correcting code frame is written into adjacent position, use the chance that error-correcting code frame of prevention does not have recovery fully.Thus just can be so that the impact that made flash memory device causes under non-homogeneous processing procedure, and then increase up time of flash memory device.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Figure 1A is the calcspar that uses the host computer system of flash memory shown in the embodiment of the invention;
Figure 1B is the schematic diagram of the computing machine shown in the embodiment of the invention, input/output device and flash memory;
Fig. 1 C is the schematic diagram of the host computer system shown in another embodiment of the present invention and flash memory;
Fig. 2 is the calcspar of the flash memory shown in the embodiment of the invention;
Fig. 3 is the summary calcspar of the flash controller shown in another embodiment of the present invention;
Fig. 4 is the process flow diagram of the method for writing data shown in the embodiment of the invention;
Fig. 5 is that the error-correcting code frame shown in the embodiment of the invention is cut apart schematic diagram;
Fig. 6 is the error-correcting code frame shown in the embodiment of the invention and the schematic diagram of character line;
Fig. 7 is the schematic diagram of the wrong figure place in the character line zone shown in the embodiment of the invention;
Fig. 8 is the schematic diagram of the table that puts in order in the character line zone shown in the embodiment of the invention;
Fig. 9 is the schematic diagram of the wrong figure place in the character line zone shown in another embodiment of the present invention;
Figure 10 is the schematic diagram of the table that puts in order shown in another embodiment of the present invention;
Figure 11 is the schematic diagram of the table that puts in order shown in further embodiment of this invention.
Description of reference numerals:
1000: host computer system;
1100: computing machine;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system bus;
1110: data transmission interface;
1202: mouse;
1204: keyboard;
1206: display;
1208: printer;
1212: flash disk;
1214: memory card;
1216: solid state hard disc;
1310: digital camera;
The 1312:SD card;
The 1314:MMC card;
The 1316:CF card;
1318: memory stick;
1320: embedded MMC;
100: flash memory;
203: connector;
205: flash controller;
207: flash chip;
209: microprocessor unit;
211: host interface unit;
213: Memory Management Unit;
215: the flash interface unit;
217: memory buffer;
219: error correction unit;
223: mistake figure place statistic unit;
501～516,601,603,605: the error-correcting code frame;
S405～S425: each step of the method for writing data of the embodiment of the invention.
Embodiment
Flash controller mistake in using correcting code technical protection is stored in the data in the flash chip.Yet highdensity flash chip can produce because of inhomogeneous processing procedure the different zone of fiduciary level.Because the zone that fiduciary level is lower easily produces more wrong figure place, it will cause this zone to restore, therefore when data storing when hanging down fiduciary level regional, the situation of nonrecoverable data just can more early occur.Accordingly, the invention provides method for writing data and controller and a storage device that is used for flash memory, reduce the impact that non-homogeneous processing procedure causes, and then increase the up time of flash memory.
Figure 1A is the calcspar of the host computer system of the use flash memory shown in the embodiment of the invention.Figure 1B is the schematic diagram of the computing machine shown in the embodiment of the invention, input/output device and flash memory.Fig. 1 C is the schematic diagram of the host computer system shown in another embodiment of the present invention and flash memory.
Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 such as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
Generally speaking, but host computer system 1000 can be any system of storage data substantially.Although in the present embodiment, host computer system 1000 is to describe with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, reproducing apparatus for phonotape or video signal player in another embodiment of the present invention.For example, be digital camera (video camera) 1310 o'clock in host computer system, 100 of flash memories are its employed secure digital (secure digital, SD) card 1312, Multi Media Card (Multi Media Card, MMC) 1314, compact flash (Compact Flash, CF) card 1316, memory stick (Memory Stick, MS) 1318 or embedded
Storage device 
1320 (shown in Fig. 1 C).Embedded
Storage device 
1320 comprise embedded multi-media card (EmbeddedMMC, eMMC).It is worth mentioning that, embedded multi-media card is directly to be electrically connected on the substrate of host computer system 1000.
Fig. 2 is the calcspar of the flash memory shown in the embodiment of the invention.Please refer to Fig. 2, flash memory 100 comprises connector 203, flash controller 205 and flash chip 207.Wherein, flash controller 205 is electrically connected between connector 203 and the flash chip 207, and flash controller 205 sees through connector 203 and be electrically connected to host computer system 1000, writes in the flash chip 207 with the data that will come from host computer system 1000.
At this, connector 203 for example is the SD connector.Yet, it must be appreciated and the invention is not restricted to this, connector 203 also can be advanced annex (the Serial Advanced TechnologyAttachment of sequence, SATA) connector, universal serial bus (Universal Serial Bus, USB) connector, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 connectors, high-speed peripheral component connecting interface (Peripheral Component InterconnectExpress, PCI Express) connector, the MS connector, the MMC connector, the CF connector, the connector of integrated driving electrical interface (Integrated Device Electronics, IDE) connector or other data transmission that are fit to.
In the present embodiment, flash controller 205 comprises microprocessor unit 209, host interface unit 211, Memory Management Unit 213 and flash interface unit 215.Wherein, host interface unit 211, Memory Management Unit 213 and flash interface unit 215 are electrically connected to respectively microprocessor unit 209.
In another embodiment of the present invention, the steering order of Memory Management Unit 213 also can the procedure code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the flash memory) of flash chip 207.Same, when flash memory 100 running, a plurality of steering orders of Memory Management Unit 213 can be carried out by microprocessor unit 209.In addition, in another embodiment of the present invention, Memory Management Unit 213 also can a hardware pattern be embodied in the flash controller 205.
In another embodiment of the present invention, flash controller 205 also can also comprise other functional module group.Fig. 3 is the summary calcspar of the flash controller shown in another embodiment of the present invention.Please refer to Fig. 3, except microprocessor unit 209, Memory Management Unit 213, host interface unit 211 and flash interface unit 215, flash controller 205 also comprises memory buffer 217, error correction unit 219.
Error correction unit 219 is electrically connected to microprocessor unit 209 and encodes to guarantee the correctness of data in order to carry out an error recovery.Specifically, when Memory Management Unit 213 receives main frame and writes instruction from host computer system 1000, error correction unit 219 can write for corresponding this main frame error-correcting code (the Error Checking and Correcting Code corresponding to data writing generation of instruction, ECCCode), and Memory Management Unit 213 this data writing can be write in the flash chip 207 with corresponding error-correcting code.Afterwards, when Memory Management Unit 213 can read error-correcting code corresponding to these data during reading out data simultaneously from flash chip 207, and error correction unit 219 can be according to the data execution error correction program of this error-correcting code to reading.
And in the present embodiment, when flash controller 205 receives data, Memory Management Unit 213 can be first a plurality of yards frames (frame) with Data Segmentation, afterwards, error correction unit 219 produces error-correcting code corresponding to each yard frame again, with these yards frame and its separately corresponding error-correcting code encode respectively and form error-correcting code frame (ECC frame).At this, the size of error-correcting code frame is to cut apart according to the size of unit of transfer, and the size of this unit of transfer is that the specifications according to flash chip decide, and that is to say each unit of transfer must what (bit) of protection (protect).For example unit of transfer is 1Kbyte, protects 24 positions, and it is 1Kbyte that flash controller 205 can be cut into per unit with data.Error correction unit 219 then can be carried out the error recovery coding for the data of every 1Kbyte, so each error-correcting code frame is exactly 1Kbyte, but the invention is not restricted to this, and the error-correcting code frame also can be 512byte or 2Kbyte.
Afterwards, Memory Management Unit 213 just can be divided into the error-correcting code frame a plurality of yards frame fragments, and with these yards frame fragment with non-sequentially put in order the ordering after write in the flash chip 207.
Memory buffer 217 is to be electrically connected to microprocessor unit 209 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from flash chip 207.At this, memory buffer 217 also can be used to the temporary transient code frame fragment that stores, so that flash controller 205 captures each yard frame fragment according to non-sequentially putting in order one by one from memory buffer 217, after finishing, arrangement again each yard frame fragment is write in the flash chip 207.
In the present embodiment, flash controller 205 also comprises mistake figure place statistic unit 223.Mistake figure place statistic unit 223 is the wrong figure places of adding up each zone of flash chip, and the wrong figure place according to each zone sorts, and uses to determine that code frame fragment writes to the putting in order of flash chip (that is to say to begin to arrange and to arrange from which yard frame fragment and write after finishing again).Afterwards, putting in order of this yard frame fragment is updated to the table that puts in order.
It is worth mentioning that, in other embodiments, error correction unit 219 also can be disposed at flash memory 100 with wrong figure place statistic unit 223, and is electrically connected with flash controller 205 respectively.
The above-mentioned flash memory 100 of below namely arranging in pairs or groups describes the detailed step of method for writing data in detail.
Fig. 4 is the process flow diagram of the method for writing data shown in the embodiment of the invention.Please be simultaneously with reference to Fig. 2～Fig. 4, at first, in step S405,1000 receptions write instruction and data from the main frame system.Particularly, flash controller 205 receives through host interface unit 211 and writes instruction and data.
Then, in step S410, be at least one yard frame with Data Segmentation.Afterwards, shown in step S415, produce the error-correcting code corresponding with above-mentioned code frame, so that above-mentioned code frame error-correcting code corresponding with it formed the error-correcting code frame.With Fig. 2 and Fig. 3, error correction unit 219 can be carried out error recovery coding to each yard frame data, to form the error-correcting code frame.Say further, when flash memory 100 receives data, Memory Management Unit 213 can be first a plurality of yards frames (cutting apart as the basis take unit of transfer) with Data Segmentation, produce error-correcting code corresponding to each yard frames by error correction unit 219 again, with these yards frame and its separately corresponding error-correcting code form respectively the error-correcting code frame.That is to say, above-mentioned data can be formed many error-correcting code frames, and each error-correcting code frame can have the error-correcting code of a correspondence.
Then, in step S420, respectively these error-correcting code frames are divided into a plurality of yards frame fragments.That is to say, the Memory Management Unit 213 in the flash controller 205 can be divided into a plurality of yards frame fragments with these error-correcting code frames respectively, and these a little code frame fragments are temporary in the memory buffer 217.
For instance, suppose in the flash chip 207 it is with the unit of a page as data access, and a page is 8Kbyte, character line of primary access (word line) is page of access.Suppose that unit of transfer is 0.5Kbyte, then Memory Management Unit 213 can be divided into 16 error-correcting code frames with a page, each error-correcting code frame is divided into the code frame fragment of 16 five equilibriums again.Yet, not limiting the quantity that the error-correcting code frame is wanted to cut apart at this, each error-correcting code frame also may be partitioned into the code frame fragment of 32 five equilibriums or 64 five equilibriums.
At last, in step S425, code frame fragment is write in the flash chip 207 after arranging with non-sequentially putting in order.In detail, the Memory Management Unit in the flash controller 205 213 can write to code frame fragment in the flash chip 207 after arranging with non-sequentially putting in order.That is to say, flash controller 205 can come acquisition code frame fragment from memory buffer 217 according to non-ly sequentially putting in order of recording in the table that puts in order, and these yards frame fragment is write in the flash chip 207 again.Accordingly, flash controller 205 just can on average be written in each error-correcting code frame in the same character line.
For instance, Fig. 5 is that the error-correcting code frame shown in the embodiment of the invention is cut apart schematic diagram.In the present embodiment, suppose to have 16 error-correcting code frames 501～516, each error-correcting code frame is split into respectively the code frame fragment of 16 five equilibriums.And suppose that non-sequentially putting in order begins to sort for first yard frame fragment from each error-correcting code frame, again second code frame fragment of each error-correcting code frame sorted afterwards, according to this rule until a code frame fragment write to again in the flash chip 207 after being booked a character line.
In detail, from first yard frame fragment F of first error-correcting code frame 501
1,1Begin, sequentially capture first yard frame fragment (F of each error-correcting code frame
1,1, F
2,1, F
3,1, F
4,1..., F
16,1).Then, sequentially capture again second code frame fragment (F of each error-correcting code frame
1,2, F
2,2, F
3,2, F
4,2..., F
16,2).Afterwards, sequentially capture again the 3rd code frame fragment (F of each error-correcting code frame
1,3, F
2,3, F
3,3, F
4,3..., F
16,3).By that analogy, until a code frame fragment write to again in the flash chip 207 after being booked a character line.Yet, it must be appreciated that non-sequentially putting in order of the present invention is not limited to this.
In addition, generally speaking, flash chip 207 has in many character lines and each the bar character line and has a plurality of memory cells.Accordingly, code frame fragment then is to be stored in these character lines.It is worth mentioning that, also can add up by the wrong figure place statistic unit 223 in the flash controller 205 the wrong figure place (summation of each yard frame fragment that this wrong figure place can be the alphabet line also can be the mean value of each yard frame fragment of alphabet line) of each yard frame segment area of each the bar character line in the flash chip 207.Afterwards, mistake figure place statistic unit 223 just can determine that code frame fragment writes to putting in order in the flash chip 207 according to wrong figure place, and will put in order and be updated to the table that puts in order, with as follow-up in flash chip 207 foundation of read error correcting code frame.Above-mentioned putting in order namely determines to begin to arrange from which yard frame fragment.For example, be up to minimum these zones of sorting by wrong figure place, and begun to arrange by the highest zone of wrong figure place, then begun to arrange in high zone for several times by error bit, by that analogy.Afterwards, mistake figure place statistic unit 223 will put in order and be updated to the table that puts in order.Accordingly, flash controller 205 carry out data write fashionable, can putting in order data write in the flash chip 207 according to the table that puts in order.
For instance, Fig. 6 is the error-correcting code frame shown in the embodiment of the invention and the schematic diagram of character line.The present embodiment is take three error-correcting code frames 601,603,605 as example, and supposes that maximum error recovery (correct) figure place of each error-correcting code frame is 16 (bit).For convenience of description, at this, error-correcting code frame 601,603,605 is divided into respectively three code frame fragments, namely S01, S02, S03, S11, S12, S13, S21, S22, S23.Corresponding also the wherein character line 610 of flash chip 207 is divided into 9 regional F1～F9, to store the code frame fragment of error-correcting code frame 601,603,605.
Below represent relation between the putting in order of the wrong figure place in character line 610 each zone and code frame fragment for an embodiment.
Fig. 7 is the schematic diagram of the wrong figure place in the character line zone shown in the embodiment of the invention.Fig. 8 is the schematic diagram of the table that puts in order in the character line zone shown in the embodiment of the invention.In the present embodiment, writing yard frame fragment to character line, read the wrong figure place that these yards frame fragment is added up each yard frame fragment in the character line, use the wrong figure place of learning each zone in the character line.Accordingly, sort these character lines zone according to wrong figure place and the order that obtains is F1 (the mistake figure place is 10), F2 (the mistake figure place is 9), F9 (the mistake figure place is 8), F8 (the mistake figure place is 4), F3 (the mistake figure place is 3), F7 (the mistake figure place is 2), F6 (the mistake figure place is 1), F4 (the mistake figure place is 0), F5 (the mistake figure place is 0).Yet, it must be appreciated that of the present invention putting in order is not limited to this, in other embodiments also can be by float to large.Therefore, when wanting again to write yard frame fragment to flash chip, just can arrange these yards frame fragment according to these wrong figure places, to put in order according to this code frame fragment be write to flash chip 207.For example, with reference to Fig. 8, first yard frame fragment S01, S11 and the S21 of each error-correcting code frame correspond to respectively F1, F2 and F9, second code frame fragment S02, S12 and the S22 of each error-correcting code frame correspond to respectively F8, F3 and F7, and the 3rd code frame fragment S03, S13 and the S23 of each error-correcting code frame correspond to respectively F6, f4 and f5.Accordingly, putting in order of above-mentioned code frame fragment then is S01, S11, S12, S13, S23, S03, S22, S02, S21.
It should be noted that because the maximum error recovery figure place of each error-correcting code frame is 16, should be noted therefore whether the summation of the wrong figure place in the zone that the code frame fragment of each error-correcting code frame writes can exceed 16.Below illustrate for another embodiment again.
Fig. 9 is the schematic diagram of the wrong figure place in the character line zone shown in another embodiment of the present invention.Figure 10 is the schematic diagram of the table that puts in order shown in another embodiment of the present invention.In the present embodiment, arranging the order that these character line zones obtain according to wrong figure place is F1, F2, F9, F3, F4, F8, F7, F6, F5.If decide putting in order of yard frame fragment according to said sequence, then first yard frame fragment S01, S11 and the S21 of each error-correcting code frame are that correspondence writes to F1, F2 and F9 respectively, second code frame fragment S02, S12 and the S22 of each error-correcting code frame then are that correspondence writes to F3, F4 and F8 respectively, and the 3rd code frame fragment S03, S13 and the S23 of each error-correcting code frame then are that correspondence writes to F7, F6, F5 respectively.At this, the summation of the wrong figure place in the zone that the code frame fragment of each error code frame writes can not exceed 16.With error-correcting code frame 601, the summation of the wrong figure place of S01, S02 and S03 is less than or equals 16, and error-correcting code frame 603 and 605 also by that analogy.Yet if according to above-mentioned putting in order, the summation of the wrong figure place of S01, S02 and S03 (F1, F3 and F7) will be greater than 16, i.e. 10+6+2=18.Accordingly, just readjust putting in order of yard frame fragment.
For example, first yard frame fragment S01, S11 and the S21 of each error-correcting code frame correspond to respectively F1, F2 and F9, F1 (its wrong figure place is still first little by draining into greatly).Come, second code frame fragment S02, S12 and the S22 of each error-correcting code frame then correspond to respectively F8, F4 and F3 again, then are to large by float in the wrong figure place of this F8, F4 and F3.Afterwards, the 3rd of each error-correcting code frame the code frame fragment S03, S13 and S23 then correspond to respectively F7, F6, F5 (its wrong figure place is still first little by draining into greatly).Accordingly, error-correcting code frame 601,603 and 605 wrong figure place summation then are respectively 16 (10+4+2), 15 (9+5+1) and 14 (8+6+0).
In addition, in another embodiment of the present invention, above-mentioned putting in order also can be random adjustment, so that error-correcting code frame 601,603 and 605 wrong figure place summation are less than or equal to 16 and get final product.Below illustrate for an embodiment again.Figure 11 is the schematic diagram of the table that puts in order shown in further embodiment of this invention.After through adjustment, the wrong figure place of each error-correcting code frame then is respectively 16,16 and 13.But the present invention is not limited to this, as long as any arrangement mode can be so that the wrong figure place summation of each error-correcting code frame be no more than 16 of its error recovery (correct) ability within the scope of the present invention.
Then, when flash controller 205 is wanted read error correcting code frame, just can read out according to the table that puts in order the code frame fragment of same error-correcting code frame, to reduce.
In sum, the present invention forms a plurality of error-correcting code frames with Data Segmentation and coding first, again each error-correcting code frame is divided into a plurality of yards frame fragments, sequentially puts in order according to non-afterwards, and a plurality of yards frame fragments are write in the flash chip.Be written in adjacent position because each error-correcting code frame is also discontinuous, but be written in equably in the different zones, use error-correcting code frame of prevention in case damage, then do not recover the chance of data fully.Just can solve the impact that flash memory made under non-homogeneous processing procedure causes thus, and then increase the up time of flash memory device.
Although the present invention discloses as above with embodiment; but it is not to limit the present invention; those skilled in the art should do a little change and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be as the criterion with the content of claim.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (24)
1. a method for writing data writes to flash chip for the data that will come from host computer system, it is characterized in that, this method for writing data comprises:
From this host computer system receive data;
Cutting apart these data is at least one yard frame;
Produce the error-correcting code corresponding with this at least one yard frame, should at least one yard frame error-correcting code corresponding with it forming at least one error-correcting code frame;
Should be divided into a plurality of yards frame fragments by at least one error-correcting code frame; And
Described code frame fragment is write in this flash chip after arranging with non-sequentially putting in order.
2. method for writing data according to claim 1 is characterized in that, after the step that described error-correcting code frame is divided into described code frame fragment, also comprises:
Described code frame fragment is temporary in the memory buffer.
3. method for writing data according to claim 2 is characterized in that, the step according to writing to after this non-arrangement that sequentially puts in order in this flash chip comprises:
Capture each described code frame fragment according to this non-sequentially putting in order from this memory buffer, and will write in this flash chip after the described code frame arrangement of fragments.
4. method for writing data according to claim 1 is characterized in that, also comprises:
The foundation table that puts in order, this non-ly sequentially puts in order with record.
5. method for writing data according to claim 4 is characterized in that, this flash chip has many character lines and each described character line has a plurality of memory cells, and this method for writing data also comprises:
Described code frame fragment is stored in the described character line;
Read described code frame fragment to add up the wrong figure place of each described code frame fragment in the described character line;
Determine that according to this mistake figure place described code frame fragment writes to putting in order of described character line; And
Upgrading this puts in order to this table that puts in order.
6. method for writing data according to claim 5 is characterized in that, determines that according to this mistake figure place described code frame fragment writes to this step that puts in order of described character line, comprising:
Cutting apart each described character line is a plurality of zones;
According to the wrong figure place in each described zone, from large to small or from small to large ordering decide that described code frame fragment writes to described character line this put in order.
7. method for writing data according to claim 6 is characterized in that, according to the wrong figure place in each described zone, arranges from large to small or from small to large the step of described code frame fragment, comprising:
Maximum error recovery figure place according to this at least one error-correcting code frame, determine putting in order of described code frame fragment, wherein, the summation of the wrong figure place in the zone that writes of the described code frame fragment of this at least one error-correcting code frame is less than or equal to this maximum error recovery figure place.
8. method for writing data according to claim 1 is characterized in that, wherein,
When these data are split into a plurality of yards frames, produce a plurality of error-correcting codes corresponding with described a plurality of yards frames, so that corresponding described a plurality of error-correcting codes form a plurality of error-correcting code frames with it with described a plurality of yards frames, and described a plurality of error-correcting code frames are divided into a plurality of yards frame fragments;
Wherein, this non-sequentially putting in order comprises:
First first yard frame fragment of described a plurality of error-correcting code frames is arranged, again the next code frame fragment of described a plurality of error-correcting code frames is arranged, until the described a plurality of yards frame fragments of described a plurality of error-correcting code frames all arrange complete till.
9. a flash controller writes in the flash chip in order to the data that will come from host computer system, it is characterized in that, this flash controller comprises:
Microprocessor unit;
The flash interface unit is electrically connected to this microprocessor unit, and is electrically connected to this flash chip;
Host interface unit is electrically connected to this microprocessor unit, and is electrically connected to this host computer system, is used for receiving these data from this host computer system;
Memory Management Unit is electrically connected to this microprocessor unit, is used for these data are write to this flash chip; And
Error correction unit is electrically connected to this microprocessor unit, in order to these data are produced error-correcting code;
Wherein, it is at least one yard frame that this Memory Management Unit is cut apart these data, and this error correction unit produces corresponding error-correcting code to this at least one yard frame, should at least one yard frame error-correcting code corresponding with it forming at least one error-correcting code frame,
This Memory Management Unit should be divided into a plurality of yards frame fragments by at least one error-correcting code frame, and described code frame fragment is write in this flash chip after arranging with non-sequentially putting in order.
10. flash controller according to claim 9 is characterized in that, also comprises:
Memory buffer is electrically connected to this microprocessor unit, is used for temporarily storing described code frame fragment.
11. flash controller according to claim 10 is characterized in that, this Memory Management Unit captures each described code frame fragment according to this non-sequentially putting in order from this memory buffer, writing in this flash chip after the described code frame arrangement of fragments.
12. flash controller according to claim 9, it is characterized in that, when these data are split into a plurality of yards frames, produce a plurality of error-correcting codes corresponding with described a plurality of yards frames, so that corresponding described a plurality of error-correcting codes form a plurality of error-correcting code frames with it with described a plurality of yards frames, and described a plurality of error-correcting code frames are divided into a plurality of yards frame fragments; At this moment, this Memory Management Unit is arranged first yard frame fragment of described a plurality of error-correcting code frames first, again the next code frame fragment of described a plurality of error-correcting code frames is arranged, until described a plurality of yards frame fragments all arrange complete till.
13. flash controller according to claim 9 is characterized in that, this this non-sequentially putting in order to the table that puts in order of Memory Management Unit record.
14. flash controller according to claim 13 is characterized in that, this flash chip has many character lines and each described character line has a plurality of memory cells, and described code frame fragment is stored in the described character line, and this flash controller also comprises:
Mistake figure place statistic unit is read described code frame fragment adding up the wrong figure place of each described code frame fragment in the described character line, and is determined putting in order of described code frame fragment according to this mistake figure place,
Wherein, this Memory Management Unit puts in order this and is updated to this table that puts in order.
15. flash controller according to claim 14, it is characterized in that, this Memory Management Unit is divided into a plurality of zones with each described character line, and according to described zone wrong figure place separately, from large to small or from small to large ordering decide that described code frame fragment writes to described character line this put in order.
16. flash controller according to claim 15, it is characterized in that, this Memory Management Unit is according to the maximum error recovery figure place of this at least one error-correcting code frame, determine putting in order of described code frame fragment, wherein, the summation of the wrong figure place in the zone that writes of the described code frame fragment of this at least one error-correcting code frame is less than or equal to this maximum error recovery figure place.
17. a flash memory is used for storing the data that come from host computer system, it is characterized in that, this flash memory comprises:
Connector is electrically connected to this host computer system, and this host computer system receives this data certainly;
Flash chip; And
Flash controller, be electrically connected to this flash memory and this connector, being used for cutting apart these data is at least one yard frame, and the generation error-correcting code corresponding with this at least one yard frame, should at least one yard frame this error-correcting code corresponding with it forming at least one error-correcting code frame, should be divided into a plurality of yards frame fragments by at least one error-correcting code frame again, afterwards described code frame fragment be write in this flash chip after arranging with non-sequentially putting in order.
18. flash memory according to claim 17 is characterized in that, also comprises:
Memory buffer is used for temporarily storing described code frame fragment.
19. flash memory according to claim 18 is characterized in that, this flash controller captures each described code frame fragment according to this non-sequentially putting in order from this memory buffer, and will write in this flash chip after each described code frame arrangement of fragments.
20. flash memory according to claim 17, it is characterized in that, when these data are split into a plurality of yards frames, produce a plurality of error-correcting codes corresponding with described a plurality of yards frames, so that corresponding described a plurality of error-correcting codes form a plurality of error-correcting code frames with it with described a plurality of yards frames, and described a plurality of error-correcting code frames are divided into a plurality of yards frame fragments; At this moment, this flash controller is arranged first yard frame fragment of described a plurality of error-correcting code frames first, the more next code frame fragment of described a plurality of error-correcting code frames is arranged, until described a plurality of yards frame fragments all arrange complete till.
21. flash memory according to claim 17 is characterized in that, this this non-sequentially putting in order to the table that puts in order of flash controller record.
22. flash memory according to claim 21 is characterized in that, this flash chip has many character lines and each described character line has a plurality of memory cells, and described code frame fragment is stored in the described character line, and this flash memory also comprises:
Mistake figure place statistic unit, read described code frame fragment to add up the wrong figure place of each described code frame fragment in the described character line, and determine putting in order of described code frame fragment according to this mistake figure place, afterwards, this is put in order is updated to this table that puts in order.
23. flash memory according to claim 22, it is characterized in that, this flash controller is divided into a plurality of zones with each described character line, and according to described zone wrong figure place separately, from large to small or from small to large ordering decide that described code frame fragment writes to described character line this put in order.
24. flash memory according to claim 23, it is characterized in that, this flash controller is according to the maximum error recovery figure place of this at least one error-correcting code frame, determine putting in order of described code frame fragment, wherein, the summation of the wrong figure place in the zone that writes of the described code frame fragment of this at least one error-correcting code frame is less than or equal to this maximum error recovery figure place.
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| CN 200910215388 CN102117230B (en) | 2009-12-31 | 2009-12-31 | Data writing method, flash memory controller and a flash memory memorizing device |
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Citations (3)
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|---|---|---|---|---|
| CN1279482A (en) * | 1999-06-28 | 2001-01-10 | 株式会社东芝 | Flash memory |
| CN1551244A (en) * | 2003-04-03 | 2004-12-01 | ���ǵ�����ʽ���� | Non-volatile memory with error correction for page copy operation and method thereof |
| CN1713302A (en) * | 2004-06-22 | 2005-12-28 | 群联电子股份有限公司 | Converting circuit for preventing from fault of correcting code |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1279482A (en) * | 1999-06-28 | 2001-01-10 | 株式会社东芝 | Flash memory |
| CN1551244A (en) * | 2003-04-03 | 2004-12-01 | ���ǵ�����ʽ���� | Non-volatile memory with error correction for page copy operation and method thereof |
| CN1713302A (en) * | 2004-06-22 | 2005-12-28 | 群联电子股份有限公司 | Converting circuit for preventing from fault of correcting code |
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