CN1021145C - Address transmission method and apparatus - Google Patents

Abstract

The present invention relates to an address path which transmits addresses from a plurality of sources, and the address path comprises an incremental circuit; the addresses comprise a plurality of address bits and integral bits. When the address bits are added to the incremental circuit, the integral bits are added to a programmable logic device (PLD); when the addresses are transmitted or increased according to requirements, the PLD independently generates a plurality of transformation bits so as to determine the characteristics of the address bit number which indicates the state of transition in advance; subsequently, the transformation bits are used for transforming the integral bits of addresses so that the integral bits of the addresses and the increased addresses are transmitted together. The increased addresses, the transformation bits and the integral bits are logically combined so as to verify that the transmitted and/or increased addresses do not have errors.

Description

Address transmission method and apparatus

The present invention relates to address transmission device, relate in particular to and be used to verify that there is not the method and apparatus of mistake in the address information of transmitting.

In the ordinary course of things, especially when the address of transmission was used for reference-to storage equipment, many data handling systems did not comprise the device of checking address transfer.In order under this class situation, to guarantee correctly to carry out that memory addressing, one of method of prior art are joining the address parity check bit in the memory devices and the address combination of data, and object information is stored into the position of addressing.

During the cycle subsequently, the result bits of being stored is used for signaling, and relevant mistake or the fault condition in position with visit appears in expression.The example of this scheme is at United States Patent (USP) 3,789, describes in 204, and this article is entitled as " self checking numeral storage system ", is invented by George Ding Ba Lou.

Though such scheme is to detection of stored device fault or effectively wrong, it just carries out indirect detection to the mistake that takes place between the transmission period of address.The increment circuit part is passed through in address in transmission, and the verification of this class transmission becomes and is even more important.In this class scheme, do not add a large amount of circuit redundancies, be difficult to guarantee that result address is effective.That is to say that universal scheme is for providing two address incrementers and a comparer.By the incremental address that is relatively produced by two increment circuits, comparer can not make a mistake in the operation of verification increment.After this, the incremental address that can be after the verification produces new parity.

Except increasing repetition, the address transfer that such scheme requires the plenty of time verification not make a mistake.In current high-speed data disposal system, adopt the sort address verification obviously to greatly reduce system performance.When the address of being transmitted experienced comprise further delay to such as the generation of the check bit of the address transfer of the such storage pipeline equipment of cache from virtual during to physical address translations, this problem becomes more serious.In this class scheme, the greatly different difference that generates between the operate as normal efficient of the work efficiency of the parity check bit relevant with physical address and physical address has in time produced more adverse influence to system performance, thereby causes that the virtual storage management device of carrying out this address translation is had strict more requirement.

Therefore, a fundamental purpose of the present invention provides a kind of improved method and apparatus, to have the address path transport address of increment circuit and relevant integrality position thereof by one.

Furtherly, more special purpose of the present invention provides a kind of improved method and apparatus, and whether the transmission that is used for the verification address does not exist mistake.

Above-mentioned and other purpose of the present invention reaches in a preferred embodiment.It is particularly useful that method of the present invention and device (are for example being stated in the common pending application application of this W of nurse base profit etc. disclosed) in the pipeline cache memory system.In this system, the part virtual memory management unit of processing means (VMMU) conversion or be used as the request of visit cache data from the address that a system bus receives.In order to make the cache pipeline stages safeguard high-performance, must in particular time interval, receive these requests, otherwise will lose useful cache cycle.Another important condition is need be the address increment that offers cache memory system.Because to have high reliability is very important in this system, so, integrality position or parity check bit be used as certain partly be included in the sort address.

Method and apparatus provided by the invention is used to the address path transport address by having increment circuit to generate the integrality position, and whether the transmission that verification is carried out does not exist mistake.Accomplish that this step will separate the integrality position from each address, and generate the conversion position of respective numbers, the predetermined properties that the prediction of some state changes in these indication addresses, conversion positions.Then, with these conversion positions the original complete bit map is become to be used for the integrality position of incremental address.

The integrality position of address is transformed to the integrality position of the address that is used for increment respectively, in the minimum time, can finishes this two operations.In addition, the present invention allows the difference on time of arrival between address and the integrality position thereof.This has reduced the time restriction of forcing on the address source (for example VMMU).That is to say that it has safeguarded the high performance level of (for example cache of preferred embodiment) in the receiving arrangement of the address.

The error free address increment of verification that provided is provided in the present invention and/or the method and the device of transmission promoted reliability.This is the address of wearing or featuring stage armour increment, the conversion position, and the integrality position of incremental address does not logically combine and finishes.When pointing out out an error, then this logical consequence is used to discarded this cache catalogue cycle, and forces a cache error state.In order to allow address and integrality position thereof the more big-difference on time of arrival, the integrality position of the not incremental address of Dao Daing is incorporated in the combined result of incremental address and conversion position at last.

In a preferred embodiment, the computing that generates the conversion position is carried out by a programmable logical device (PLD).According to the present invention, PLD generates the conversion position, and its method is to judge predetermined properties from the address that receives, and is to judge owing to address increment expects whether the figure place that changes is an odd number in this preferred embodiment.

In the system that those addresses and integrality position thereof arrive simultaneously, PLD can be with being the integrality bit map of the address that receives the complete bit of value-added address with quadrat method.In this case, PLD carry out to generate the conversion position and according to the operation to the integrality position supplement of receiver address of the state of conversion position.

Can understand the novelty among its architecture and the method for operating of showing that embodies characteristic of the present invention better with reference to following explanation and accompanying drawing thereof.And other purpose of the present invention and advantage.The purpose of accompanying drawing, is intended to the definition of example and description rather than limitation of the present invention.

Fig. 1 is the piece figure of a cache subsystem, and it combines method and apparatus of the present invention.

Fig. 2 a and 2b have partly made diagram to the cache subsystem of Fig. 1 in further detail.

Fig. 3 (comprising Fig. 3-1 and Fig. 3-2) and 4 is flow process and timing diagrams of explaining the operation of method and apparatus of the present invention respectively.

Fig. 1 provides with block diagram form, combines the structure of the cache subsystem 14-6 of method and apparatus of the present invention.As shown in the figure, cache subsystem 14-6 is from 14-1 to the 14-5 reception memorizer request of a plurality of sources.These sources comprise a pair of CPU (central processing unit) (CPU) subsystem 14-2 and 14-4, system bus source 14-1 and a relocated address register (RAR) source 14-5.

All comprise a virtual memory management unit (VMMU) among each cpu subsystem 14-2 and the 14-4, be used for the CPU virtual address is converted to physical address, submit to cache subsystem 14-6 as the part of memory requests.System bus source 14-1 comprises a FIFO subsystem that is coupled on system bus and relocated address register (RAR) the source 14-5.This FIFO subsystem also receives information transmitted between any unit that is connected on the bus except reception comes from any new data result of memory requests (it is sent to system bus by cache subsystem 14-6).

Cache subsystem 14-6 is incorporated into a source address generating portion and two pipeline stages of separating, and wherein, each grade has decoding and the control circuit of oneself.The source address generating portion comprises the piece 14-62 to 14-65 that carries out source address selection and systematic function.As shown in the figure, first pipeline stages is an address level, and it comprises catalogue and relevant memory circuitry piece 14-66 to 14-76.This one-level is carried out the source address that latchs generation, directory search and hit the function of comparison.First pipeline stages provides output information with the form of level number and column address.The timing signal timing that the operation of first pipeline stages is generated by the timing and control circuits among the subsystem 14-6.

Be transferred to second pipeline stages immediately from the information of first order output, make the first order give over to the request of next source and use.Second pipeline stages is data level, and comprises data buffer and relevant memory circuitry piece 14-80 to 14-87 as shown in the figure.This one-level realizes that visit is from the request msg of memory buffer 14-88 and 14-90 or use the function of the data replacement/storage data from system bus 14-1.Second pipeline stages provides 36 words, is used for the transmission to one of cpu subsystem 14-2 and 14-4.The timing signal timing that the operation of second pipeline stages is still generated by cache subsystem timing and control circuits.

The basic timing in each subsystem source of Fig. 1 is set up by cache subsystem timing and control circuits.This control allows cpu subsystem 14-2 and 14-4 and comprises that the bus 14-1 of RAR source 14-5 shares the no conflict of cache subsystem 14-6.These circuit have been done more detailed description in relevant patented claim, briefly, these circuit comprise the address selection logic circuit, they produce control signal, the specified address selector switch 14-62 chooser 14-2 of system, among 14-4 or the 14-1/14-5 one is as the request address source.

Timing circuit also comprises the pipeline clock circuit, is used for the dissimilar of the definite cache cycle that streamline can be started.This causes comprising signal WRTPLS according to each, and the request of PIPEOA+OA and PIPEOB+OA produces a prearranged signal sequence.That is to say that first and second signals are represented the cache services request that proposed by CPUO subsystem 14-2 and CPU1 subsystem 14-4 respectively, and other signal indication is thought the cache services request that line 14-1 proposes by system.

The different masses of first and second pipeline stages is made of the standard integrated circuit, described in circuit and senior micro equipment company published nineteen eighty-three as described in for example " TTL databook " the 3rd volume of being published by Texas Instruments Inc 1984 was gone up " the programmable array logic handbook of senior micro equipment ".For example, the address selector circuit of piece 14-62 is made of six 74AS857 traffic pilot chips of two groups of cascades, to select one of four addresses.The latch of piece 14-68 and 14-72 is made of 74AS843 latch chip.

Catalog memory 14-74 and 14-76 are that the 8 bit slice cache address comparator circuit of TMS2150JL constitute by parts number, and this circuit is produced by the Texas Instruments Inc.The part number that address register 14-80 and 14-84 are produced by the Texas Instruments Inc is that 9 interface triggers of SM74AS823 constitute.The address incrementer of piece 14-64 is that the standard A LU chip of 74AS181A constitutes by part number.

As shown in Figure 1, cache subsystem 14-6 is made up of the strange part of even summation, and these parts allow according to strange or even storage address two data words to be conducted interviews simultaneously.The solution of the present invention makes the transmission of the parity check bit in the strange storage address of even summation that is provided by the cache pipeline stages by address source be achieved.That is to say, when increment circuit 14-64 carries out the increment operation of being asked, load address signal APLOAO of device response of parity transformation circuit 14-65 form produces a plurality of conversion position (FLPA08, FLPA16), be stored on the parity checking bit position of the address bit that requires increment that receives from selector circuit 14-62.AND gate 14-63 is with composite signal WRTPLS and PTPEOA+OA and produce signal ADLOAD.

Forward sight circuit shown in increment circuit 14-64 comprises among Fig. 2 a in more detail, it produces an increment carry signal INCRYO as output.This signal is added to translation circuit 14-65 as input, and it is also expressed in Fig. 2 a in more detail.Translation circuit 14-65 is that programmable array logic (PAL) element of AMPAL16L8B constitutes by part number, and this element is produced by senior micro equipment company.As what elaborate at this, PAL circuit 14-65 programs especially according to the present invention or fires, to produce desired conversion position.

In preferred embodiment, a part (promptly 10 a) increment with whole physical address, and remaining address bit by the transmission of cache store punching pin system flow pipeline stage with changing.Thus, corresponding from the address that selector circuit 14-62 receives low byte and 10 address bits (CMAD13-22) of the part of time low byte be added to translation circuit 14-65 as input.And the parity check bit (CMAPEX, CMAPOO, CMAPO8 and CMAP16) of the address of selecting is separated with source address, and is loaded into parity address latch 14-66 according to timing signal PIPEOA+OA.

In addition, cache subsystem 14-6 also comprises parity checker 14-69 and 14-70,, a pair of OR-gate 14-71 and 14-73, and a pair of pipeline stages trigger 14-86 and 14-87, it is arranged as shown in the figure.According to the present invention, these circuit checks are carried out by address transfer or address increment operation that circuit 14-64 carries out error freely.Checking circuit 14-69 and 14-70 produce desired error signal for whole 4 address bytes that make up in OR-circuit 14-71 and 14-73.Response timing signal PIPEOB+OA, the parity error signal ODAPER and the EVAPER that send from OR-gate 14-71 and 14-73 are deposited in error trigger 14-86 and 14-87.

Parity checker 14-69 and 14-70 are that the standard parity generator circuit of 74AS280 constitutes by part number, and the error trigger is that the standard clocked flip-flop of 74AS1823 constitutes by part number.Door 14-71 and 14-73 is taken as single OR-gate and represents that these can be the standard NAND door structure of 74S20 by part number for convenience of explanation, operates as negative input OR-gate.

Fig. 2 b illustrates the part of even parity check circuit 14-70 in more detail.This part of corresponding parity generator circuit 14-700 produces a parity error signal EVAPEIA for the inferior low byte address bit EVAD08-15 that is stored among the even latch 14-72, its method is with these signals and corresponding conversion position FLAPO8 combination, to produce output signal EVAPE1.Then, signal EVAPE1 makes up with address parity check bit signal CMAPO8 in XOR circuit 14-702, to produce output error signal EVAP1A.This signal is added to OR circuit 14-73 with other three signals that other circuit produced of parity checker 14-70.

Referring to figs. 1 through the timing and the process flow diagram of 2b and Fig. 3 and 4, explanation is comprised the operation of the cache subsystem 14-6 of method of the present invention and device here.As mentioned above, the present invention makes cache subsystem 14-6 keep integrality completely in the address tunnel that includes the increment circuit.The cache subsystem has the address of parity check bit or integrality position by address selector circuit 14-62 any one reception from the 14-1 to 14-5 of source.In order to originate putting on these, the time restriction that particularly puts on CPUVMMU minimizes, and the solution of the present invention allows to produce the time of arrival of address shown in Figure 4 and integrality position time lag.In other words, the integrality position of VMMU generation can be delayed to almost half of catalogue cycle.At this moment, they be timed signal PIPEOA+OA the negative sense peak or the back along lock.According to the signal ADLOAD that packs into, address bit is more early latched, for example, and in four of catalogue cycle/for the moment.With address bit, two conversion positions also are latched.Subsequently, according to timing signal PIPEOB+OA, the address bit of increment, position, odd address and error signal (if detected words) are latched.

In the increment operating period of PAL circuit 14-65, the conversion position produces simultaneously.Seen in from Fig. 2 a, except increment carry signal INCRYO is a low level or for the binary zero (ZERO), if address bit CMAD17-22 is high level or equals scale-of-two one (ONES) that then the circuit reception cache address signal CMAD13-CMAD22 corresponding with address bit 13-22 imports as it.PAL circuit 14-65 produces corresponding with interchange address parity check bit 08 and 16 respectively signal FLPAO8 and FLPA16 and exports as it.

The state of signal FLPAL08 and FLPAL16 forms according to following table:

FLPAP08 FLPAP16

CCC CI F CCCCCC C F

MMM MN L MMMMMM M L

AAA AC P AAAAAA A P

DDD DR A DDDDDD D A

111 1Y P 111122 2 P

345 60 0 678901 2 1

8 6

（0）XXX XH L （0）XXXXXX L L

（0）XXX LL L （2）XXXXXL H L

（1）XXL HL H （3）XXXXLH H H

（2）XLH HL L （4）XXXLHH H L

（3）LHH HL H （5）XXLHHH H H

（3）HHH HL H （6）XLHHHH H L

（7）LHHHHH H H

（7）HHHHHH H H

As shown in Table, when input carry signal INCRYO was high level, promptly the no increment of expression took place.On the contrary, when signal INCRYO is low level, rise in value.Whether the state of signal INCRYO and CMAD16 has determined the low byte carry from the address.When the prediction of result odd number address bit CMAD13-15 as carry changed state, conversion position signal FLPAP08 was put ONE.As address bit 22(CMAD22) when being low, i.e. expression is not rised in value.Otherwise, when address bit 22 is high, will rise in value.Numerical table in the left side bracket of each table shows the figure place of prediction change state.

From above-mentioned table, boolean or the logical equation of signal FLPA08 and FLPA16 are as follows:

FLPAP08＝INCRYO+ CMAD16+ CMAD14·CMAD15。

FLPAP16＝ CMAD22+ CMAD21+ CMAD19·CMAD20+ CMAD17·CMAD18·CMAD20。

Between the time of arrival of address and integrality position, have only under the situation of very little difference, also can directly use the parity check bit or the integrality position of PAL circuit 14-65 address substitute.In this case, integrality position or parity check bit signal CMAP08 and CMAP16 also can be used as input and are added to PAL circuit 14-65, and integrality position CMAP08E after the conversion and the state of CMAP16E generate according to following table.

CMAP08E CMAP16E

CCC CI C C CCCCCC C C C

MMM MN M M MMMMMM M M M

AAA AC A A AAAAAA A A A

DDD DR P P DDDDDD D P P

111 1Y 0 0 111122 2 1 1

345 60 8 8 678901 2 6 6

E E

（0）XXX XH L L （0）XXXXXX L L L

（0）XXX XH H H （0）XXXXXX L H H

（0）XXX LL L L （2）XXXXXL H L L

（0）XXX LL H H （2）XXXXXL H H H

（1）XXL HL L H （3）XXXXLH H L H

（1）XXL HL H L （3）XXXXLH H H L

（2）XLH HL L L （4）XXXLHH H L L

（2）XLH HL H H （4）XXXLHH H H H

（3）LHH HL L H （5）XXLHHH H L H

（3）LHH HL H L （5）XXLHHH H H L

（3）HHH HL L H （6）XLHHHH H L L

（3）HHH HL H L （6）XLHHHH H H H

（7）LHHHHH H H L

（7）HHHHHH H L H

As can be seen, signal CMAP08 and CMAP08E are the functions of address bit 8-15.And signal CMAP16 and CMAP16E are the functions of address bit 16-22.

From last table, boolean or the logical equation of signal CMAP08E and CMAP16E are as follows:

CMAP08E＝ CMAP08·INCRYO+ CMAD16· CMAD08+ CMAD15·CMAD16·CMAP08· INCRYO+ CMAD14·CMAD15· CMAP08+CMAD14·CMAD16·CMAP08· INC RYO

CMAP16E＝ CMAD22· CMAP16+ CMAD21· CMAD16+ CMAD20·CMAD21·CMAD22·CMAP16+ CMAD19·CMAD20· CMAD16+ CMAD18·CMAD19·CMAD21·CMAD22·CMAD16+ CMAD17·CMAD18·CMAD20· CMAD16+

CMAD16·CMAD17·CMAD19·CMAD21·CMAD22·CMAP16。

Referring now to Fig. 3, presumptive address selector circuit 14-62 has selected CPU O VMMU 14-2 as address source.When the cache cycle that the cache timing circuit is set up begins, some part of 36 bit address of selecting is used as input and offers odd address latch 14-68, even address latch 14-72, increment circuit 14-64 and parity checking translation circuit 14-65.In preferred embodiment, the appearance of 4 integrality position CMAPEX and CMAP00 to CMAP16 can be delayed.Therefore, 32 source address positions are latched to odd address latch 14-68.That is address bit 22(CMAD22) be strange/even start address position.If it is binary zero (ZERO), promptly indicating selected source address has been even number, does not need to add one again.If address bit 22 is scale-of-two one (ONE), then expression need add one, and selected source address is an odd number.

As shown in Figure 3, as the function of the state of address bit 22 and add the selected source address position (CMAD16-21) of one low byte, on the throne 22 keep intact when being a binary zero is transferred to even address latch 14-72.When position 22 be scale-of-two for the moment, this low byte address bit CMAD16-21 is added 1 by circuit 14-64.

Adding in one, whether PAL translation circuit 14-65 operates according to the state of low byte address bit CCMAD16-21 and will hang down conversion position FPLA16 and put to indicate owing to add one to a state and predict that the number of the low byte address bit that will change state is an odd number.If this number is an odd number, then position FLPA16 is changed to scale-of-two ONE, otherwise when the figure place of prediction change was even number, this position was changed to scale-of-two ZERO.

As shown in Figure 3, PAL translation circuit 14-65 is arranged to such state with time low conversion position FLPA08, and whether this state indicates because to add the number that a part that indicates inferior LO address byte will change the address bit (CMAD13) of state be odd number.Adding one is that the state that adds a carry signal INCRYO that the NOT-AND gate 14-640 by Fig. 2 a sends is set up.When signal INCRYO was scale-of-two ONE, expression did not add one.Otherwise when signal INCRYO was scale-of-two ZERO, presentation address signal CMAD17-22 was ONES entirely, promptly adds one.

As can be seen from Figure 3, if the quantity odd number of the inferior low byte address bit CMAD13-15 of prediction change state, then conversion position FLAP08 is changed to scale-of-two ONE.Otherwise if the number of the position of prediction change state is an even number, then conversion position FLAP08 is changed to scale-of-two ZERO.

The response address signal ADLOAD that packs into comprises that the address bit of 10 value-added address bits and 2 conversion positions is latched to even address latch 14-72.Simultaneously, not value-added 32 address bits are latched to odd address latch 14-68.From Fig. 3, the conversion position of latching is used as supplement or late byte integrity position CMAP08 that reaches of conversion and the state of CMAP16, and these two integrality positions are latched among the parity checking address latch 14-66 according to timing signal PIPEOA+OA.After this, parity checker 14-69 and 14-70 are used to the transmission of verification source address and/or add one whether do not have an error.

Shown in Fig. 2 b, at first the address bit and the conversion bit pattern that add one, to postpone time of arrival to greatest extent, perhaps in other words, perhaps in other words, the integrality position that reaches provides the time as much as possible in order to be late according to the solution of the present invention.Then, intermediate result is combined to the integrality position that postpones arrival by anticoincidence circuit 14-702, this circuit is carried out desired integrality position and is done the not supplement or the conversion of the function of the state of correspondent transform position, because supplement and verification all are exclusive-OR operations, thereby can obtain identical result with any order execution.

As shown in Figure 3, the result of verification or checked operation is deposited in streamline trigger 14-86 and 14-87.In other words, if any one that is stored in 4 address bytes among strange and even address latch 14-68 and the 14-72 produces error signal, promptly cause among OR-gate 14-71 and the 14-73 corresponding one to force to export a scale-of-two ONE.Successively, it forces among error trigger 14-86 and the 14-87 one to be converted to a scale-of-two ONE state according to timing signal PIPEOB+OA.OR-gate 14-71 and 14-73 generate an error signal and force the cache hit circuit to send out a miss state signal.To prevent cache subsystem 14-6 read error data from its memory buffer 14-88 and 14-90.Thus, integrality term of execution of the cycle detected error replaced the catalogue cycle of setting up the cache miss state.

Can see from the above description method of the present invention and device are how to provide the very effective high speed of integrality position to generate for requiring by the address of increment path transmission.This generative process allows address and integrality position to there are differences on time of arrival.In addition, for the purpose to reliability, the present invention can and/or add an operation to address transfer and carry out verification.

Obviously, those skilled in the art can do many modifications to preferred embodiment of the present invention.For example, can be the byte generation integrality position of arbitrary number in the source of other type with the present invention, for the use of various miscellaneous equipments.The present invention also can utilize programmable logical device of other type.

Be based on the viewpoint that figure place is an odd number though change the feature of state, this feature can be revised.Equally, though increment operation relates to and adds and equal 1 constant, the increment operation of other type also can be carried out in a similar manner by the present invention.

Below with regulations optimised form of the present invention is described and diagram according to the rules, yet, for the staff in the present technique field, the spirit that is proposed in can be according to the present invention appended claim is carried out multiple modification, and in some cases, can advantageously use some characteristic of the present invention and not use other characteristic.

Claims (5)

1, a kind of method that the integrality of address path any one address transfer that receives from a plurality of sources by having increment circuit is carried out verification, described address comprises some integralities position, and described method comprises the following steps:

(a) described some integralities position is separated from the address of described reception;

(b) some integralities position of the described reception of storage;

(c) produce some conversion position, as the address of described reception whether by the function of described increment circuit increment;

(d) the described some conversion of storage position;

(e) according to the state of described conversion position to the position supplement of described integrality; And

(f) address of described increment is transferred to application apparatus with the integrality position of conversion.

2, according to the process of claim 1 wherein that described method comprises step:

(g) the integrality position of the address of the described increment of checking procedure (f) and described conversion, with the address of verifying described reception be transmit error freely and/or increment.

3, according to the process of claim 1 wherein that described step (g) comprises step:

(1) logical combination is carried out in the address and the described conversion position of described increment, to produce first result; And

(2) the described integrality position of the address of described first result and described reception is logically made up, so that allow the delay to greatest extent on time of arrival between described address and the described relevant complete bit.

4, a kind of device that is used for a storage address integrality of verification, this address can be by an increment circuit (14-64) increment, described address is received by the part of described device as an address location, address location comprises n position and m integrality position of representing described address, and said apparatus is characterised in that and comprises:

First circuit (14-62) is used for the described n position of at least a portion (CMAD13-22) is added to described increment circuit;

A translation circuit (14-65), be used for receiving a described part (CMAD13-22) and a plurality of binary output signal (FLPA08 of corresponding generation of described n position, 16), the binary value of described binary output signal depends on the figure place of the described part of the described n position of will be reversed by described increment circuit, and

An integrity check circuit (14-70), be used for receiving representative by the signal of the address portion of increment (EVAD08-15), described output signal and described m integrality position, and corresponding generation one shows that whether described integrality position and described binary output signal have correctly been represented described by the signal of the address portion of increment together.

5, according to the device of claim 4, wherein said checking circuit Be Controlled must work after the parallel work-flow of being carried out by described increment circuit and translation circuit.

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