CN102111175A - CDMA (code division multiple access) module - Google Patents
CDMA (code division multiple access) module Download PDFInfo
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- CN102111175A CN102111175A CN2011100232382A CN201110023238A CN102111175A CN 102111175 A CN102111175 A CN 102111175A CN 2011100232382 A CN2011100232382 A CN 2011100232382A CN 201110023238 A CN201110023238 A CN 201110023238A CN 102111175 A CN102111175 A CN 102111175A
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Abstract
The invention discloses a CDMA (code division multiple access) module which comprises a CPU (central processing unit) chip, an audio circuit interface, a video circuit interface and a power unit, wherein the audio circuit interface is connected with the CPU chip and used for transmitting audio data to the CPU chip; the video circuit interface is connected with the CPU chip and used for transmitting video data to the CPU chip; and the power unit is connected with the CPU chip and used for supplying power for the CPU chip. The volume of the CDMA module is relatively small.
Description
Technical field
The present invention relates to code division multiple access (CDMA, Code Division Multiple Access) technology, relate in particular to a kind of realization circuit of CDMA module.
Background technology
The CDMA module is meant the communication module based on the CDMA platform, and it is integrated in communication chip, storage chip etc. on the circuit board, and it is had by functions such as CDMA platform transmitting-receiving short message, voice call, transfer of data.The CDMA module can realize the main communication function of common CDMA mobile phone, also can be described as the mobile phone of " scaled-down version ".Computer, single-chip microcomputer, ARM can link to each other with the CDMA module by the RS232 serial ports, realize various voice communications versus data communications functions by the AT instruction control module.
CDMA module of the prior art, generally the cpu chip QSC6010 that produces based on Qualcomm realizes, but, the CDMA functions of modules is less, therefore, and in design during based on the equipment of CDMA module, realize functions such as voice call if desired, need carry out circuit design in addition, thereby the volume of equipment is bigger, and cost is higher; And therefore the general more complicated of the power circuit of CDMA module, has also caused the bigger problem of CDMA module volume.
Summary of the invention
In view of this, the technical problem to be solved in the present invention is, a kind of CDMA module is provided, and volume is less relatively.
For this reason, the embodiment of the invention adopts following technical scheme:
The embodiment of the invention provides a kind of CDMA module, comprises cpu chip; Also comprise: voicefrequency circuit interface, video circuit interface and power subsystem, wherein,
The voicefrequency circuit interface is connected with cpu chip, be used for and cpu chip between carry out the transmission of voice data;
The video circuit interface is connected with cpu chip, be used for and cpu chip between carry out the transmission of video data;
Power subsystem is connected with cpu chip, is used to the cpu chip power supply.
Described voicefrequency circuit interface comprises:
The pin HPH_OUT of cpu chip is by the tenth electric capacity and the 4th grounding through resistance of serial connection, and the pin HPH_OUT of connection voicefrequency circuit interface is as one tunnel single-ended earphone interface.
Described voicefrequency circuit interface also comprises:
The pin MIC_BIAS of cpu chip is by first capacity earth, meets the pin MIC1_P of voicefrequency circuit interface by first resistance, also meets the pin MIC2_P of voicefrequency circuit interface by second resistance;
The pin MIC1P of cpu chip connects the pin MIC1_P of voicefrequency circuit interface by second electric capacity;
The pin MIC1N of cpu chip is by the pin MIC1_N of the 3rd electric capacity connection voicefrequency circuit interface, also by the 3rd grounding through resistance;
The pin MIC2P of cpu chip is by the pin MIC2_P of the 4th electric capacity connection voicefrequency circuit interface, also by the 5th capacity earth;
The pin MIC2N of cpu chip is by the 6th capacity earth;
The pin CCOMP of cpu chip is by the 7th capacity earth;
The pin SPKR_IN_P of cpu chip connects the pin AUXDP of cpu chip by the 8th electric capacity;
The pin SPKR_IN_M of cpu chip connects the pin AUXDN of cpu chip by the 9th electric capacity;
Five resistance and ten one capacity earth of the pin SPKR_OUT_P of cpu chip by connecting, and, the pin SPKR_OUT_P of connection voicefrequency circuit interface;
The pin EAR1OP of cpu chip connects the pin EAR1OP of voicefrequency circuit interface;
The pin EAR1ON of cpu chip connects the pin EAR1ON of voicefrequency circuit interface.
Power subsystem comprises:
The pin VREG_RFRX of cpu chip connects the pin VREG_RFRX of power subsystem, and, by the capacity earth of 3 parallel connections;
The pin VREG_MSMP of cpu chip connects the pin VREG_MSMP of power subsystem, and, by the capacity earth of 2 parallel connections;
The pin VREG_MSME2 of cpu chip connects the pin VREG_MSME2 of power subsystem, and, by the capacity earth of 2 parallel connections;
The pin VREG_RFTX1 of cpu chip connects the pin VREG_RFRX of power subsystem, and by 1 capacity earth;
The pin VREG_MSMA of cpu chip connects the pin VREG_MSMA of power subsystem, and, by the capacity earth of 2 parallel connections;
The pin VREG_MSMC of cpu chip connects the pin VREG_MSMC of power subsystem, and, by the capacity earth of 2 parallel connections.
Power subsystem also comprises:
Pin VDD_RFRX1, the VDD_RFRX2 of cpu chip, VDD_RFRX3, VDD_RFRX4 are connected with the pin VREG_RFRX of cpu chip;
Pin VDD_P2, the VREG_MSME1 of cpu chip and VDD_P1 all are connected with the pin VREG_MSME2 of cpu chip;
Pin VREG_RFTX2, the VREG_RFTX4 of cpu chip is connected with the pin VREG_RFTX1 of cpu chip.
Power subsystem also comprises:
The pin REF_BYP of cpu chip connects the pin REF_BYP of power subsystem;
The pin REF_ISET of cpu chip connects the pin REF_ISET of power subsystem;
The pin VREG_RUIM of cpu chip connects the pin VREG_RUIM of power subsystem, and the pin VREG_RUIM and the pin VREG_USB of cpu chip pass through capacity earth respectively; The pin VREG_TCXD of cpu chip connects the pin VREG_TCXD of power subsystem, and, pass through capacity earth;
The pin VDD_P3 of cpu chip connects the pin VREG_MSMP of power subsystem;
The pin VDD_RFTX of cpu chip connects the pin VREG_RFTX of power subsystem, and, pass through capacity earth;
The pin VDD_RFTX5 of cpu chip passes through the pin VREG_RFTX that first inductance connects power subsystem, and, by first inductance and a capacity earth;
The pin VDD_RFTX3 of cpu chip passes through the pin VREG_RFTX that second inductance connects power subsystem, and, pass through capacity earth;
The pin VDD_A_AN and the VDD_B_AN of cpu chip interconnect, and, the pin VREG_MSMA of connection power subsystem;
The pin VSW_MSMC of cpu chip connects the pin VREG_MSMC of cpu chip by the 3rd inductance;
The pin VDD_CORE of cpu chip connects the pin VREG_MSMC of power subsystem.
Described cpu chip is QSC6010, perhaps, and QSC6020, perhaps, QSC6030.
The packaged type of described CDMA module is: the BGA packaged type.
Technique effect for technique scheme is analyzed as follows:
The voicefrequency circuit interface is connected with cpu chip, be used for and cpu chip between carry out the transmission of voice data; The video circuit interface is connected with cpu chip, be used for and cpu chip between carry out the transmission of video data; Power subsystem is connected with cpu chip, is used to the cpu chip power supply.Thereby in the CDMA module of the embodiment of the invention, voicefrequency circuit interface, video circuit interface are provided, have made during based on the equipment of CDMA module, to need not to realize functions such as voice call and video demonstration in design, do not need to carry out circuit design, thereby reduced the volume and the cost of equipment; And, a kind of power subsystem is provided, compared to existing power subsystem, circuit structure is simple, has reduced the realization volume and the cost of CDMA module.
Description of drawings
Fig. 1 is the implementation structure schematic diagram of embodiment of the invention CDMA module;
Fig. 2 is an embodiment of the invention voicefrequency circuit interface circuit schematic diagram;
Fig. 3 is the realization circuit diagram of embodiment of the invention power subsystem;
Fig. 4 a～Fig. 4 d is that embodiment of the invention video circuit interface is realized circuit diagram.
Embodiment
Below, be described with reference to the accompanying drawings the realization of the realization circuit of embodiment of the invention CDMA module.
In embodiment of the invention CDMA module, circuit structure is finished based on the cpu chip design of the QSC60X0 series of Qualcomm, and the cpu chip of wherein said QSC60X0 series can comprise: QSC6010, QSC6020 and QSC6030 etc.Chip QSC60X0 has integral baseband, radio frequency, unit such as power management, in the CDMA module of the embodiment of the invention, increased the electric power management circuit of peripheral audio interface circuit, video interface circuit and optimization for this chip, constituted the CDMA module of the embodiment of the invention, thereby guaranteed to have dwindled the realization volume of CDMA module under the more full situation of the function of CDMA module own.
Below, be described with reference to the accompanying drawings the realization of embodiment of the invention CDMA module.
Fig. 1 is the structural representation of the CDMA module of the embodiment of the invention, as shown in Figure 1, comprises cpu chip 110; Also comprise: voicefrequency circuit interface 120, video circuit interface 130 and power subsystem 140, wherein,
Wherein, as shown in Figure 2, described voicefrequency circuit interface 120 can comprise:
The pin HPH_OUT of cpu chip 110 is by the tenth capacitor C 210 and the 4th resistance R 204 ground connection of serial connection, and the pin HPH_OUT of connection voicefrequency circuit interface 120 is as a road single-ended earphone interface in the voicefrequency circuit interface.
By this structure, for the CDMA module provides earphone interface.
In addition, described voicefrequency circuit interface 120 also comprises:
The pin MIC_BIAS of cpu chip 110 is by first capacitor C, 201 ground connection, meets the pin MIC1_P of voicefrequency circuit interface 120 by first resistance R 201, also meets the pin MIC2_P of voicefrequency circuit interface 120 by second resistance R 202;
The pin MIC1P of cpu chip 110 connects the pin MIC1_P of voicefrequency circuit interface 120 by second capacitor C 202;
The pin MIC1N of cpu chip 110 is by the pin MIC1_N of the 3rd capacitor C 203 connection voicefrequency circuit interfaces 120, also by the 3rd resistance R 203 ground connection;
The pin MIC2P of cpu chip 110 is by the pin MIC2_P of the 4th capacitor C 204 connection voicefrequency circuit interfaces 120, also by the 5th capacitor C 205 ground connection;
The pin MIC2N of cpu chip 110 is by the 6th capacitor C 206 ground connection;
Wherein, pin MIC1_P, MIC1_N and MIC2_P are as the two-way microphone interface.
As shown in Figure 2, described voicefrequency circuit interface 120 also comprises:
The pin CCOMP of cpu chip 110 is by the 7th capacitor C 207 ground connection;
The pin SPKR_IN_P of cpu chip 110 connects the pin AUXDP of cpu chip 110 by the 8th capacitor C 208;
The pin SPKR_IN_M of cpu chip 110 connects the pin AUXDN of cpu chip 110 by the 9th capacitor C 209;
Five resistance R 205 and ten one capacitor C 211 ground connection of the pin SPKR_OUT_P of cpu chip 110 by connecting, and, the pin SPKR_OUT_P of connection voicefrequency circuit interface 120;
The pin SPKR_OUT_M of cpu chip 110 connects the pin SPKR_OUT_M of voicefrequency circuit interface 120;
The pin EAR1OP of cpu chip 110 connects the pin EAR1OP of voicefrequency circuit interface 120;
The pin EAR1ON of cpu chip 110 connects the pin EAR1ON of voicefrequency circuit interface 120.
Wherein, pin SPKR_OUT_P and SPKR_OUT_M constitute horn interface;
And pin EAR1OP and pin EAR1ON constitute the receiver interface.
Described earphone interface, microphone interface, horn interface and receiver interface have constituted described voicefrequency circuit interface 120.Thereby, when carrying out the design of equipment, need not to realize in addition functions such as voice call, but directly use corresponding voicefrequency circuit interface to get final product based on the CDMA module of the embodiment of the invention.
Preferably, as shown in Figure 2, the value of first capacitor C 201 can be 100nF; The value of first resistance R 201, second resistance R 202, the 3rd resistance R 203 can be 2.2k Ω; The value of second capacitor C 202, the 3rd capacitor C 203, the 4th capacitor C 204 and the 6th capacitor C 206 can be 82nF; The value of the 5th capacitor C 205, the 7th capacitor C 207, the 8th capacitor C 208, the 9th capacitor C 209, the 11 capacitor C 211 can be 100nF; The value of the tenth capacitor C 210 can be 220nF; The value of the 4th resistance R 204 can be 22 Ω.
As shown in Figure 3, the power subsystem in the embodiment of the invention 140 can comprise:
Pin VREG_RFRX～the VDD_RFRX4 of cpu chip 110 interconnects, and all connects the pin VREG_RFRX of power subsystem 140, and the pin VREG_RFRX of cpu chip 110 passes through capacitor C 101～C103 capacity earth of totally 3 parallel connections;
Preferably, the capacitance of capacitor C 101 is 2.2uF, and the capacitance of capacitor C 102 is 100pF, and the capacitance of capacitor C 103 is 100pF.
The pin VREG_MSMP of cpu chip 110 connects the pin VREG_MSMP of power subsystem 140, and the pin VREG_MSMP of cpu chip 110 is by capacitor C 111 and the C112 capacity earth of totally 2 parallel connections;
Preferably, the capacitance of capacitor C 111 can be 100nF, and the capacitance of capacitor C 112 can be 2.2uF.
The pin VREG_MSME2 of cpu chip 110 connects the pin VREG_MSME2 of power subsystem 140, and the pin VREG_MSME2 of cpu chip 110 is by capacitor C 115 and the C116 capacity earth of totally 2 parallel connections; Pin VDD_P2, the VREG_MSME1 of cpu chip 110 and VDD_P1 all are connected with the pin VREG_MSME2 of cpu chip 110;
Wherein, the capacitance of capacitor C 115 can be 100nF, and the capacitance of capacitor C 116 can be 2.2uF.
Pin VREG_RFTX1, the VREG_RFTX2 of cpu chip 110, VREG_RFTX4 interconnect, and connect the pin VREG_RFRX of power subsystem 140, and by capacitor C 123 ground connection;
Wherein, the capacitance of capacitor C 123 can be 100pF.
The pin VREG_MSMA of cpu chip 110 connects the pin VREG_MSMA of power subsystem 140, and the pin VREG_MSMA of cpu chip 110 also passes through capacitor C 127 and the C128 capacity earth of totally 2 parallel connections;
Wherein, the capacitance of capacitor C 127 and C128 is respectively 2.2uF and 100nF.
The pin VREG_MSMC of cpu chip 110 connects the pin VREG_MSMC of power subsystem 140, and the pin VREG_MSMC of cpu chip 110 also passes through capacitor C 134 and the C135 capacity earth of totally 2 parallel connections;
Wherein, the capacitance of capacitor C 134 and C135 is respectively 4.7uF, 100nF.
In addition, the pin REF_BYP of cpu chip 110 connects the pin REF_BYP of power subsystem 140;
The pin REF_ISET of cpu chip 110 connects the pin REF_ISET of power subsystem 140;
The pin VREG_RUIM of cpu chip 110 connects the pin VREG_RUIM of power subsystem 140, and the pin VREG_RUIM of cpu chip 110 and pin VREG_USB are respectively by capacitor C 106 and C107 ground connection; The pin VREG_TCXD of cpu chip 110 connects the pin VREG_TCXD of power subsystem 140, and, by capacitor C 108 ground connection;
The pin VDD_P3 of cpu chip 110 connects the pin VREG_MSMP of power subsystem 140;
The pin VDD_RFTX of cpu chip 110 connects the pin VREG_RFTX of power subsystem 140, and, by capacitor C 120 ground connection;
The pin VDD_RFTX5 of cpu chip 110 passes through the pin VREG_RFTX that first inductance L 101 connects power subsystems 140, and, by first inductance L 101 and capacitor C 125 ground connection;
The pin VDD_RFTX3 of cpu chip 110 passes through the pin VREG_RFTX that second inductance L 102 connects power subsystems 140, and, by capacitor C 126 ground connection;
The pin VDD_A_AN and the VDD_B_AN of cpu chip 110 interconnect, and, the pin VREG_MSMA of connection power subsystem 140;
The pin VSW_MSMC of cpu chip 110 connects the pin VREG_MSMC of cpu chip 110 by the 3rd inductance L 103;
The pin VDD_CORE of cpu chip 110 connects the pin VREG_MSMC of power subsystem 140.
For power subsystem as shown in Figure 3, few with respect to the employed device of power subsystem of the prior art, therefore, reduced circuit complexity, reduced the realization volume of CDMA module.
Shown in Fig. 4 a～Fig. 4 c, in the video circuit interface for the embodiment of the invention, with the backlight drive interface on the cpu chip (comprising pin LCD_DRV_N1), IIC interface (comprising pin LCD_CLK and pin LCD_DATA) and frame synchronization interface (comprise pin LCD_RS, LCD_EN, LCD_CS_N, EBI_WE_N and EBI_DE_N) be connected with video circuit interface in the embodiment of the invention, and, with (the EBI_D00～EBI_D15) be connected of 16 bit data pins on the cpu chip with the corresponding data pin of video circuit interface, thereby constituted the video circuit interface in the embodiment of the invention, it comprises: 16 data wire, the sheet choosing, reset, frame synchronization, control signals such as read-write also have backlight drive circuit.
Shown in Fig. 4 d, in video circuit interface in the embodiment of the invention, the annexation in the pin of cpu chip and the video circuit interface between the respective pins is not given unnecessary details here.
Wherein, above-described cpu chip 110 can be QSC6010, perhaps, and QSC6020, perhaps, QSC6030.
In addition, the described CDMA module of the embodiment of the invention can encapsulate by the BGA packaged type in actual applications, then can further reduce the volume of CDMA module.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. a CDMA module is characterized in that, comprises cpu chip; Also comprise: voicefrequency circuit interface, video circuit interface and power subsystem, wherein,
The voicefrequency circuit interface is connected with cpu chip, be used for and cpu chip between carry out the transmission of voice data;
The video circuit interface is connected with cpu chip, be used for and cpu chip between carry out the transmission of video data;
Power subsystem is connected with cpu chip, is used to the cpu chip power supply.
2. CDMA module according to claim 1 is characterized in that, described voicefrequency circuit interface comprises:
The pin HPH_OUT of cpu chip is by the tenth electric capacity and the 4th grounding through resistance of serial connection, and the pin HPH_OUT of connection voicefrequency circuit interface is as one tunnel single-ended earphone interface.
3. CDMA module according to claim 2 is characterized in that, described voicefrequency circuit interface also comprises:
The pin MIC_BIAS of cpu chip is by first capacity earth, meets the pin MIC1_P of voicefrequency circuit interface by first resistance, also meets the pin MIC2_P of voicefrequency circuit interface by second resistance;
The pin MIC1P of cpu chip connects the pin MIC1_P of voicefrequency circuit interface by second electric capacity;
The pin MIC1N of cpu chip is by the pin MIC1_N of the 3rd electric capacity connection voicefrequency circuit interface, also by the 3rd grounding through resistance;
The pin MIC2P of cpu chip is by the pin MIC2_P of the 4th electric capacity connection voicefrequency circuit interface, also by the 5th capacity earth;
The pin MIC2N of cpu chip is by the 6th capacity earth;
The pin CCOMP of cpu chip is by the 7th capacity earth;
The pin SPKR_IN_P of cpu chip connects the pin AUXDP of cpu chip by the 8th electric capacity;
The pin SPKR_IN_M of cpu chip connects the pin AUXDN of cpu chip by the 9th electric capacity;
Five resistance and ten one capacity earth of the pin SPKR_OUT_P of cpu chip by connecting, and, the pin SPKR_OUT_P of connection voicefrequency circuit interface;
The pin EAR1OP of cpu chip connects the pin EAR1OP of voicefrequency circuit interface;
The pin EAR1ON of cpu chip connects the pin EAR1ON of voicefrequency circuit interface.
4. CDMA module according to claim 1 is characterized in that power subsystem comprises:
The pin VREG_RFRX of cpu chip connects the pin VREG_RFRX of power subsystem, and, by the capacity earth of 3 parallel connections;
The pin VREG_MSMP of cpu chip connects the pin VREG_MSMP of power subsystem, and, by the capacity earth of 2 parallel connections;
The pin VREG_MSME2 of cpu chip connects the pin VREG_MSME2 of power subsystem, and, by the capacity earth of 2 parallel connections;
The pin VREG_RFTX1 of cpu chip connects the pin VREG_RFRX of power subsystem, and by 1 capacity earth;
The pin VREG_MSMA of cpu chip connects the pin VREG_MSMA of power subsystem, and, by the capacity earth of 2 parallel connections;
The pin VREG_MSMC of cpu chip connects the pin VREG_MSMC of power subsystem, and, by the capacity earth of 2 parallel connections.
5. CDMA module according to claim 4 is characterized in that power subsystem also comprises:
Pin VDD_RFRX1, the VDD_RFRX2 of cpu chip, VDD_RFRX3, VDD_RFRX4 are connected with the pin VREG_RFRX of cpu chip;
Pin VDD_P2, the VREG_MSME1 of cpu chip and VDD_P1 all are connected with the pin VREG_MSME2 of cpu chip;
Pin VREG_RFTX2, the VREG_RFTX4 of cpu chip is connected with the pin VREG_RFTX1 of cpu chip.
6. CDMA module according to claim 5 is characterized in that power subsystem also comprises:
The pin REF_BYP of cpu chip connects the pin REF_BYP of power subsystem;
The pin REF_ISET of cpu chip connects the pin REF_ISET of power subsystem;
The pin VREG_RUIM of cpu chip connects the pin VREG_RUIM of power subsystem, and the pin VREG_RUIM and the pin VREG_USB of cpu chip pass through capacity earth respectively; The pin VREG_TCXD of cpu chip connects the pin VREG_TCXD of power subsystem, and, pass through capacity earth;
The pin VDD_P3 of cpu chip connects the pin VREG_MSMP of power subsystem;
The pin VDD_RFTX of cpu chip connects the pin VREG_RFTX of power subsystem, and, pass through capacity earth;
The pin VDD_RFTX5 of cpu chip passes through the pin VREG_RFTX that first inductance connects power subsystem, and, by first inductance and a capacity earth;
The pin VDD_RFTX3 of cpu chip passes through the pin VREG_RFTX that second inductance connects power subsystem, and, pass through capacity earth;
The pin VDD_A_AN and the VDD_B_AN of cpu chip interconnect, and, the pin VREG_MSMA of connection power subsystem;
The pin VSW_MSMC of cpu chip connects the pin VREG_MSMC of cpu chip by the 3rd inductance;
The pin VDD_CORE of cpu chip connects the pin VREG_MSMC of power subsystem.
7. according to each described CDMA module of claim 1 to 6, it is characterized in that described cpu chip is QSC6010, perhaps, QSC6020, perhaps, QSC6030.
8. according to each described CDMA module of claim 1 to 6, it is characterized in that the packaged type of described CDMA module is: the BGA packaged type.
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| CN2011100232382A CN102111175A (en) | 2011-01-20 | 2011-01-20 | CDMA (code division multiple access) module |
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| CN2011100232382A CN102111175A (en) | 2011-01-20 | 2011-01-20 | CDMA (code division multiple access) module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104244144A (en) * | 2014-07-25 | 2014-12-24 | 山东中鸿云计算技术有限公司 | Audio module for cloud terminal |
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| CN101202557A (en) * | 2007-11-14 | 2008-06-18 | 青岛海信移动通信技术股份有限公司 | Wireless communication module and terminal equipment having the same |
| CN101277377A (en) * | 2008-04-22 | 2008-10-01 | 青岛海尔软件有限公司 | Wireless digital set-top box |
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2011
- 2011-01-20 CN CN2011100232382A patent/CN102111175A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202557A (en) * | 2007-11-14 | 2008-06-18 | 青岛海信移动通信技术股份有限公司 | Wireless communication module and terminal equipment having the same |
| CN101277377A (en) * | 2008-04-22 | 2008-10-01 | 青岛海尔软件有限公司 | Wireless digital set-top box |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104244144A (en) * | 2014-07-25 | 2014-12-24 | 山东中鸿云计算技术有限公司 | Audio module for cloud terminal |
| CN104244144B (en) * | 2014-07-25 | 2017-08-18 | 山东中鸿云计算技术有限公司 | A kind of cloud terminal audio-frequency module |
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