CN102110077A

CN102110077A - Reverse order address generator

Info

Publication number: CN102110077A
Application number: CN2009102515196A
Authority: CN
Inventors: 汪健; 刘小淮; 刘霞; 陈亚宁; 张瑾
Original assignee: No 214 Institute of China North Industries Group Corp
Current assignee: No 214 Institute of China North Industries Group Corp
Priority date: 2009-12-25
Filing date: 2009-12-25
Publication date: 2011-06-29
Anticipated expiration: 2029-12-25
Also published as: CN102110077B

Abstract

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a reverse order address generator, which solves the problem of out of order of a memory address in FFT (fast Fourier transformation) operation and can output the data of the final operation result in order. The reverse order address generator consists of a special decoding logic unit, an operation length mark generator unit, a sequence intermediate address generation unit and a reverse order address generation unit, wherein both the sequence intermediate address generation unit and the reverse order address generation unit respectively adopt a selector structure. Therefore, the reverse order address generator not only has a simple structure but also has high superiority on the speed, and the hardware structure is simple and has a good actual effect when being applied in different environments.

Description

Inversion sequence address generator

Technical field:

The invention belongs to the SIC (semiconductor integrated circuit) technical field, relate to a kind of inversion sequence address generator.

Background technology:

Special-purpose fast Fourier transform (FFT) is generally used for the hardware of high-speed real-time FFT system and realizes, and is used for the very big fields of operand such as modern spectrum estimation, image processing more.When decimation in time commonly used carried out the FFT computing, if list entries x (n) deposits storage unit in according to natural order, the address of output terminal X (n) was out of order so.If it just in time is tactic wishing the order of output terminal, list entries x (n) then can not deposit storage unit in according to natural order so, the address arranging " confusing " that this fetches data when just making computing, this out of order reason come down to be undertaken by decimation in time that the principle of FFT computing causes.

Software realizes that the method for inversion preface is a lot, thunderous road algorithm (Rader) etc.In disclosed patent, the patent relevant with FFT has 43, wherein patent of invention is 42,1 of novel practical patent, mainly concentrate on the realization of FFT structure and method, fft processor and based on the application facet of FFT, as modulation-demo-demodulation method, frequency spectrum analysis method etc., the relevant patent that does not have the address to produce.

But along with the appearance of increasing special-purpose FFT hardware processor, and to the improving constantly of rate request, with inversion order function be placed on realize having become with hardware in the dedicated devices a kind of inevitable.But being implemented on structure and the speed of inversion preface function but varies.This patent has been realized a kind of simple and direct, hardware inversion preface implementation structure fast.

Summary of the invention:

The objective of the invention is to solve the out of order problem of storage address in 16～1024 FFT computings, make that the data output of final operation result is in proper order.

Be called one " PASS " if whole sequence is finished 4 FFT butterflies calculation, for the device that can finish at 16 ~ 1024, calculating process mostly is 5 PASS most so.

The FFT computing requires the data of input are sorted according to certain rules, just can draw correct result.If data had sequenced preface on request before entering device, do not need to sort again at device inside so, if but the data of entering apparatus are orders, before computing, need so the data rearrangement, and ordering reality is the bit reversal of address.For the convenience of follow-up computing, the final result of FFT equally also can be the output of Sequential output or inverted sequence.The inversion preface only can be read to carry out when the address produces at first PASS if desired, and perhaps the needs of handling for follow-up data carry out when in the end a PASS write address produces, and then have no truck with at remaining PASS.

During single PASS operation, SPASS=1 does not need the inversion order, and the address generator former state is exported.When the FFT computing, rearrangement if desired will need the inversion preface producing when first PASS reads address and last PASS write address, the write address of first PASS and last PASS read the address and all the other PASS do not need counter-rotating.

To achieve these goals, the present invention has adopted following technical scheme:

A kind of inversion sequence address generator is made up of special-purpose decoding logic unit, computing length mark generator unit, order intermediate address generation unit and inversion sequence address generation unit.

Single transform length CR＜10 〉, CR＜9, CR＜8 as the input signal of special-purpose decoding logic unit, CLK is a clock signal, and they have produced selection signal K1, K2, K3, K4, K5, K6, K7, K8, K9, the K10 of selector switchs at different levels jointly by combination and decoding logic circuit;

Single transform length CR＜10 〉, CR＜9, CR＜8 be again the input signal of computing length mark generator unit, according to CR＜10 〉, CR＜9, CR＜8 value different produce different computing length mark signal S2, S1, S0;

Order intermediate address generation unit is made up of with generation order intermediate address signal OUT＜9 the level Four selector switch 〉, OUT＜8 ..., OUT＜0.Its input signal is 10 normal count values of counter, length mark signal S2, S1, S0 and selection signal K1, K2, K3, K4, K5, K6, K7, K8, K9, K10 are as the selection signal of level Four selector switch, wherein the selection signal of first selector is computing length mark signal S2, S1, S0, second level selector switch is selected by K1, K2, K3, third level selector switch is selected by K4, K5, K6, K7, and fourth stage selector switch is selected by K8, K9, K10;

The selection conversion that inversion sequence address generation unit is made up of through selector switch six grades of selector switchs has just produced inversion sequence address signal AD＜9 〉, AD＜8 〉, AD＜0 〉, order intermediate address OUT＜9 〉, OUT＜8 〉, OUT＜0〉be its input signal, computing length mark signal S2, S1, S0 is as the selection signal of each selector switch, first, the level Four selector switch is selected by S1, second, the Pyatyi selector switch is selected by S0, the 3rd, six grades of selector switchs are selected by S2, through so simple conversion, inversion sequence address signal AD＜9 have just been produced 〉, AD＜8 〉, AD＜0 〉.

Advantage of the present invention:

The present invention compared with prior art, the principle novelty, hardware configuration is simple, because the device that adopts when circuit is realized mainly is a data selector, therefore this implementation method is not only structurally simpler and more direct, and also has bigger superiority on speed, and has stronger independence, can use in different applied environments, the inversion preface circuit that adopts above-mentioned principle to realize is realized in concrete the application, and has been obtained actual effect preferably.

Description of drawings:

Fig. 1 inversion sequence address produces theory diagram;

Fig. 2 inversion sequence control signal produces circuit block diagram;

Fig. 3 order intermediate address signal produces circuit block diagram

Fig. 4 inversion sequence address is realized circuit block diagram;

Fig. 5 inversion preface computing circuit figure.

Embodiment:

The inversion sequence address produces theory diagram as shown in Figure 1, is made up of special-purpose decoding logic unit, computing length mark generator unit, order intermediate address generation unit and inversion sequence address generation unit.

The inversion sequence control signal produces as shown in Figure 2, input signal FPASS_M represents that first PASS and last PASS need the control signal of inversion preface, input signal CR＜10 〉, CR＜9, CR＜8 expression single transform length, they are control signal by selection signal K1, K2, K3, K4, K5, K6, K7, K8, K9, the K10 that combination and decoding logic circuit have produced selector switchs at different levels jointly.

Whichever PASS has the inversion preface, and the process that the inversion preface takes place in the address that address generator produces is the same, and the address rearrangement is determined by the single transform length.The generation of order intermediate address signal as shown in Figure 3, input signal is 10 normal count values of counter, need altogether through the level Four selector switch, wherein the selection signal of first selector is computing length mark signal S2, S1, S0, they are by single transform length signal CR＜10 〉, CR＜9, CR＜8 generate, by CR＜10 〉, CR＜9, CR＜8 S2, the S1, the S0 truth table that produce be as shown in table 1.

Table 1 computing length mark signal S2, S1, S0 truth table

Count	CR1＜10 〉	CR1＜9 〉	CR1＜8 〉	S2	S1	S0
							16	1	1	0	1	1	0
64	1	0	0	1	0	0
							256	0	1	0	0	1	0
1024	0	0	0	0	0	0
							32	1	0	1	1	0	1
128	0	1	1	0	1	1
							512	0	0	1	0	0	1

The selection signal of totally three grades of selector switchs is then selected by the selection signal K1, K2, K3, K4, K5, K6, K7, K8, K9, the K10 that produce among Fig. 2 from the second level to the fourth stage, by K1, K2 ..., K10 segmentation count value that counter is produced selects control, wherein, second level selector switch is selected by K1, K2, K3, third level selector switch is selected by K4, K5, K6, K7, and fourth stage selector switch is selected by K8, K9, K10.Through the selection of level Four selector switch, just produced order intermediate address signal OUT＜9 like this 〉, OUT＜8 ..., OUT＜0.

Real reverse order address signal produces in Fig. 4.With order intermediate address OUT＜9 that produce among Fig. 3 〉, OUT＜8 ..., OUT＜0 input comes in, whole inversion preamble section has six grades of selector switchs, each grade selector switch is selected by computing length mark signal S2, S1, a S0, first, fourth grade of selector switch selected by S1, the second, the Pyatyi selector switch is selected by S0, three, six grades of selector switchs are selected by S2, through so simple conversion, just produced inversion sequence address signal AD＜9 〉, AD＜8 ..., AD＜0.

Address generate when narrating respectively below all lengths FFT conversion and the generation of reverse order address.

1, normally the count inversion preface of first or last PASS

Fig. 5 is seen in the computing of inversion preface.

(1) 16 point: S2=1, S1=1, S0=1,

The data of input first order MUX are: a ₉a ₈a ₇a ₆a ₅a ₄a ₃a ₂a ₁a ₀Through two-stage MUX, become a when entering the third level ₇a ₆a ₅a ₄a ₀a ₁a ₂a ₃a ₄a ₅Again through becoming a behind the two-stage MUX ₉a ₈a ₇a ₆a ₅a ₄a ₀a ₁a ₂a ₃The address of output that Here it is.

For example: the address of address generator is:

3?2?1?0?7?6?5?4?b?a?9?8……

Through becoming C 480 e 6 a 2 d 591 after the inversion preface ..., satisfied the requirement of data rearrangements.

(2) 64 point: S2=1, S1=0, S0=0,

Input a ₉a ₈a ₇a ₆a ₅a ₄a ₃a ₂a ₁a ₀

Enter a that is input as of the third level through two-stage MUX ₉a ₈a ₇a ₆a ₀a ₁a ₂a ₃a ₄a ₅

Then this data output is needed address.

The address of address generator is:

30?20?10?0?31?21?11?1……

Through becoming after the inversion order:

30?10?20?0?31?11?21?1……

(3) 256 point: S2=0, S1=1, S0=0,

Enter third level MUX after all the address high-low-position is put upside down, become a ₀a ₁a ₂a ₃a ₄a ₅a ₆a ₇a ₈a ₉, through becoming a behind the fourth stage MUX ₉a ₈a ₀a ₁a ₂a ₃a ₄a ₅a ₆a ₇, output is as the address after sorting then.

The address of address generator is:

C0?80?40?0?C1?81?41?1……

Through becoming after the inversion order:

C0?40?80?0?C1?41?81?1……

(4) 1024 point: S2=0, S1=0, S0=0,

Become a after the high-low-position of whole addresses put upside down ₀a ₁a ₂a ₃a ₄a ₅a ₆a ₇a ₈a ₉, export as the address.

The process of the inversion order of normal point transformation of variables, actual is still to be placed on address low 4 or 6 or least-significant byte or after all the position high-low-positions are all put upside down on the original low level and to realize.

The address of address generator is:

400?300?200?100?401?301?201?101……

Through becoming after the inversion preface: 400 200 300 100 401 201 301 101

The inversion preface of last PASS when counting in the middle of 2

(1) 32 point: S2=1, S1=0, S0=1,

INADD a ₉a ₈a ₇a ₆a ₅a ₄a ₃a ₂a ₁a ₀Through becoming a behind the one-level MUX ₉a ₈a ₇a ₆a ₀a ₁a ₂a ₃a ₄a ₅, through becoming a behind the MUX of the second level ₈a ₇a ₆a ₅a ₀a ₁a ₂a ₃a ₄a ₅, through becoming a after the level V MUX ₈a ₇a ₆a ₅a ₀a ₁a ₂a ₃a ₄, the address after the inversion order that Here it is.

As Input Address is 32107654

Through becoming 18 08 10 00 1C 0C 14 04 after the inversion preface

(2) 128 points: INADD a ₉a ₈a ₇a ₆a ₅a ₄a ₃a ₂a ₁a ₀All put upside down through high-low-position behind the third level MUX, become a ₀a ₁a ₂a ₃a ₄a ₅a ₆a ₇a ₈a ₉, through becoming a behind the fourth stage MUX ₈a ₇a ₀a ₁a ₂a ₃a ₄a ₅a ₆a ₇, through becoming a behind the level V MUX ₉a ₈a ₇a ₆a ₀a ₁a ₂a ₃a ₄a ₅a ₆, as OPADD.

(3) 512 points: after the INADD high-low-position all put upside down, replenish again highest order and become a ₉a ₀a ₁a ₂a ₃a ₄a ₅a ₆a ₇a ₈Output.

Can find out intermediate point inverse of a number position order actual be to hang down respectively 5, low 7 or 9 still are placed on after all putting upside down on the original low level and produce.

All inversion order requirements of the FFT computing from 16 point～1024 have so just been realized.

Claims

1. an inversion sequence address generator is characterized in that comprising: special-purpose decoding logic unit, computing length mark generator unit, order intermediate address generation unit and inversion sequence address generation unit;

Computing length mark generator unit according to the input single transform length CR＜10, CR＜9, CR＜8 different values, produce different computing length mark signal S2, S1, S0;

Order intermediate address generation unit is made up of the level Four selector switch, with generation order intermediate address signal OUT＜9 〉, OUT＜8 〉, OUT＜0 〉, its input signal is 10 normal count values of counter, length mark signal S2, S1, S0 and selection signal K1, K2, K3, K4, K5, K6, K7, K8, K9, K10 is as the selection signal of level Four selector switch, wherein the selection signal of first selector is computing length mark signal S2, S1, S0, second level selector switch is by K1, K2, K3 selects, third level selector switch is by K4, K5, K6, K7 selects, and fourth stage selector switch is by K8, K9, K10 selects;

Inversion sequence address generation unit is made up of six grades of selector switchs, order intermediate address OUT＜9 〉, OUT＜8 ..., OUT＜0 be its input signal, computing length mark signal S2, S1, S0 are as the selection signal of each selector switch, first, fourth grade of selector switch selected by S1, the second, the Pyatyi selector switch is selected by S0, three, six grades of selector switchs are selected by S2, have just produced inversion sequence address signal AD＜9 through the selection conversion of selector switch 〉, AD＜8 ..., AD＜0.