CN102110038B

CN102110038B - Hardware test circuit structure applied in security chip

Info

Publication number: CN102110038B
Application number: CN2009102434930A
Authority: CN
Inventors: 周鹏; 赵贵勇; 刘华茂
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2009-12-23
Filing date: 2009-12-23
Publication date: 2013-08-14
Anticipated expiration: 2029-12-23
Also published as: CN102110038A

Abstract

The invention discloses a hardware test circuit structure applied in a security chip. The hardware test circuit structure comprises two circuit structures, namely, a data downloading circuit structure and a data reading circuit structure. The circuit structure supports hardware encrypted writing in a chip memory and a hardware decrypted reading, software encryption is not required in the process of data downloading, and the efficiencies of downloading and reading/checking chip key data are improved.

Description

A kind of test circuit of security classes chip

Technical field

What the present invention relates to is the integrated circuit (IC) chip technical field; a kind of test circuit structure that is applied to the security classes chip; specifically; relate to a kind of be used to the chip that has storer and security algorithm or hardware protection mechanism; in chip testing and download phase, can carry out hardware encipher to the critical data in the storer and download the test circuit structure of reading with deciphering.Being that a kind of Jian is complete, controlled and convenient is the test circuit structure of one.

Background technology

Because the requirement of current chip data security is more and more higher, attack and physical attacks in order effectively to resist electron detection, at present the security classes chip of tape storage has added the method for designing of storage address and data encryption more and more, and namely the physical address of Memory storer and real data are address and the data after the encryption.Under chip normal use path, chip can be given Memory the logical address of CPU after encrypting, and when getting the Memory data, chip can be given CPU the Memory data after deciphering, and the CPU of chip could correct peek or executive routine like this.

Generally in chip, the address of Memory and data are transparent for test circuit, and will deposit enciphered data in Memory, just need be finished the process of encryption and decryption by software, also just need write the software crossover tool in advance.The address of Memory and data could be downloaded in the Memory storer by test circuit after the instrument conversion like this.

The mode of this software cryptography has been brought many problems:

(1) increased the intermediate link of downloading data, comprised software conversion (encryption) instrument of writing, enforcement conversion, confirm correctness of encrypting conversion etc.

(2) for the chip of different series, if the key difference, the software crossover tool must be write again.

(3) some critical datas such as the chip identification of chip, each chip has its unique chip identification, when downloading, downloads vector for one and can't deal with problems.Chip of every download just needs an independent vector.So just increase manpower and workload greatly, also be difficult to management.

For addressing the above problem and guarantee that chip CPU path can have access to correct data, can make things convenient for key message to write among the Memory again, this invention is now proposed, a kind of hardware testing circuit namely is provided, in certain test modes (enable signal TestMem_en is effective) following time, expressly being downloaded among the Memory through after the hardware encryption circuit, when reading, data are read through deciphering.What store among the Memory like this is ciphertext, has guaranteed the security of chip; Save the intermediate link of software cryptography again, finished the encryption and decryption process by hardware, also can improve the efficient of test download and verification.

Summary of the invention

What the present invention relates to is a kind of test circuit structure that is applied to the security classes chip of integrated circuit (IC) chip technical field.This test circuit structure is (the TestMem_en signal effectively is high level) under certain test modes, and support hardware is encrypted to write with hardware decryption and read the key agreement under the key of its encryption and decryption and the normal use path.Under this test pattern, the address date that the Memory store memory is put is ciphertext, and the address date on the test circuit module port is expressly.This has guaranteed the safety of chip data, has guaranteed that also CPU can correctly visit or carry out data and the program among the Memory.

Particular content comprises:

(1) downloads the data circuit structure, referring to Fig. 1

Downloading the data circuit structure comprises: the address signal (Mem_Addr) of address signal (TestMem_Addr), address encryption circuit and the key key0 of test module (Test) and memory module (Memory), test pattern enable signal (TestMem_en), Test port, outputting data signals (TestMem_Data), data encryption circuit and the key key1 of Test port and Memory storer and input data signal (Mem_Data_in).

As seen from Figure 1, when certain test modes enable signal (TestMem_en) is effective, address encryption circuit and data encryption circuit will be opened work, and the address of Memory storer and data are exactly address and the address date of data behind encrypted circuit on the Test port.And when test pattern enable signal (TestMem_en) was invalid, address encryption circuit and data encryption circuit can not opened work.

(2) sense data circuit structure is referring to Fig. 2

The sense data circuit structure comprises: the address signal (Mem_Addr) of address signal (TestMem_Addr), address encryption circuit and the key key0 of test module (Test) and memory module (Memory), certain test modes enable signal (TestMem_en), Test port, input data signal (MemTest_Data), data decrypt circuit and the key key2 of Test port and Memory storer and outputting data signals (Mem_Data_out).

As seen from Figure 2, when certain test modes enable signal (TestMem_en) is effective, address encryption circuit and data decrypt circuit will be opened work, the address of Memory storer is the address of OPADD after encrypting of test module, and the input data of test module are the data of Memory output data after deciphering.And when test pattern enable signal (TestMem_en) was invalid, address encryption circuit and data decrypt circuit can not opened work.

Description of drawings

Fig. 1 downloads the data circuit structural drawing

Fig. 2 sense data circuit structure diagram

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described.

Under specific test pattern, when test enable signal is effective, be 1 effective as the TestMem_en signal, then when data were downloaded, as seen from Figure 1, Mem_Addr was the address behind the address encryption circuit.The TestMem_en signal is the enable signal of address encryption decoding circuit, and the address encryption circuit is upset encryption to address signal, and key is key0.Corresponding, the data input signal Mem_Data_in of Memory is the data of TestMem_Data behind the data encryption circuit, the TestMem_en signal is the enable signal of data encryption decoding circuit, and the data encryption circuit is encrypted upset to data (TestMem_Data), and its key is key1.Under this certain test modes, behind the encrypted circuit through address and data, ciphertext after the address of Memory port memory (Mem_Addr) and data (Mem_Data_in) are encryption, and be expressly with data (TestMem_Data) in the address of test circuit port (TestMem_Addr).And when test enable signal is invalid, be 0 o'clock as the TestMem_en signal, address encryption circuit and data encryption circuit are not all opened work, and the path that the testing encryption of storer is downloaded has also namely turn-offed.This process that has guaranteed hardware encipher is controlled.

Under this certain test modes, when needs carry out the data reader check, as seen from Figure 2, if TestMem_en is 1 effective, address encryption circuit and data decrypt circuit unlatching work, Mem_Addr is the address behind the address encryption circuit, and key still is key0, so just can have access to the actual identical address that writes last time.Thereby the encrypted circuit among Fig. 1 and Fig. 2 on the address wire and key0 are multiplexing.And the data M emTest_Data that test circuit is read is the data behind the Memory output data M em_Data_out process decrypt circuit, and MemTest_Data reads as expressly.And when test enable signal is invalid, be 0 o'clock as the TestMem_en signal, address encryption circuit and data decrypt circuit are not all opened work, and the path of the test deciphering sense data of storer has also namely turn-offed, and this process that has guaranteed hardware decryption is controlled.

Disclosed in this invention is a kind of test circuit structure that is applied to the security classes chip, and support hardware is encrypted to write with deciphering and read; Both guaranteed that the data of actual storage in the Memory district were enciphered data, guaranteed chip data security; The key of encryption and decryption must with the normal use path under key agreement, could guarantee that CPU can correctly get needed data; Because the encryption and decryption process is finished by hardware circuit, improved test and downloaded and verification efficient, reduced intermediate link (saving the process of the artificial translation data of Test Engineer); Also made things convenient for and tested reciprocal process between the foundries; On the other hand, this circuit structure simply only increases a kind of certain test modes and address encryption circuit and data encrypting and deciphering circuit and part line, and the hardware enciphering and deciphering process has controllability, and the circuit cost is little, can ignore substantially on the cost.But can improve the efficient and the artificial probability of errors of minimizing of test download and verification.

Claims

1. the test circuit of a security classes chip is characterized in that comprising and downloads data circuit, sense data circuit, wherein:

Described download data circuit, further comprise test module, memory module, address encryption circuit, data encryption circuit, when the certain test modes enable signal is effective, address encryption circuit and data encryption circuit working, the address of memory module and data are exactly address and address and the data of data behind address encryption circuit and data encryption circuit on the test module port;

Described sense data circuit, further comprise test module, memory module, address encryption circuit, data decrypt circuit, when the certain test modes enable signal is effective, address encryption circuit and the work of data decrypt circuit, the address of memory module is the address of OPADD after the address encryption circuit is encrypted of test module, and the input data of test module are the data of memory module output data after the deciphering of data decrypt circuit; The input end of the test module address output signal link address encrypted circuit of described download data circuit, the test module data output signal connects the input end of data encrypted circuit, the address encryption circuit is input as the test module address output signal and encrypts enable signal, export to the memory module Input Address, the data encryption circuit, be input as the test module data output signal and encrypt enable signal, export to memory module input data;

Described data decrypt circuit is input as memory module output data and conciliates secret emissary's energy signal, data after the deciphering are exported to test module, the address encryption circuit is input as the test module OPADD and conciliates secret emissary's energy signal, and memory module is exported in the address after the encryption.

2. the test circuit of a kind of security classes chip as claimed in claim 1 it is characterized in that encrypting to write with deciphering at this test circuit support hardware reading, and the encrypt and decrypt process is finished by hardware circuit.

3. the test circuit of a kind of security classes chip as claimed in claim 1 is characterized in that address encryption circuit and data encryption circuit and data decrypt circuit all have Enable Pin, whether will open work by certain test modes enable signal control decipher circuit.